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From 9830f5ef340319f62ec334eb9b78d4088ee927f6 Mon Sep 17 00:00:00 2001
Date: Sun, 21 Oct 2018 21:41:55 +0300
Subject: [PATCH] Change copyright, rename macro to E2K, some fixes.
---
lib/librte_eal/common/arch/e2k/rte_cpuflags.c | 3 +-
.../common/include/arch/e2k/rte_atomic.h | 7 +-
.../common/include/arch/e2k/rte_atomic_32.h | 12 ++--
.../common/include/arch/e2k/rte_atomic_64.h | 9 +--
.../common/include/arch/e2k/rte_byteorder.h | 11 ++--
.../common/include/arch/e2k/rte_cpuflags.h | 7 +-
.../common/include/arch/e2k/rte_cpuflags_32.h | 42 ++++--------
.../common/include/arch/e2k/rte_cpuflags_64.h | 26 ++++----
.../common/include/arch/e2k/rte_cycles.h | 7 +-
.../common/include/arch/e2k/rte_cycles_32.h | 39 +++++------
.../common/include/arch/e2k/rte_cycles_64.h | 77 ++++++++++++----------
lib/librte_eal/common/include/arch/e2k/rte_io.h | 8 ++-
lib/librte_eal/common/include/arch/e2k/rte_io_64.h | 9 +--
.../common/include/arch/e2k/rte_memcpy.h | 7 +-
.../common/include/arch/e2k/rte_memcpy_32.h | 7 +-
.../common/include/arch/e2k/rte_memcpy_64.h | 7 +-
lib/librte_eal/common/include/arch/e2k/rte_pause.h | 7 +-
.../common/include/arch/e2k/rte_pause_32.h | 9 ++-
.../common/include/arch/e2k/rte_pause_64.h | 9 ++-
.../common/include/arch/e2k/rte_prefetch.h | 7 +-
.../common/include/arch/e2k/rte_prefetch_32.h | 10 ++-
.../common/include/arch/e2k/rte_prefetch_64.h | 10 ++-
.../common/include/arch/e2k/rte_rwlock.h | 13 ++--
.../common/include/arch/e2k/rte_spinlock.h | 8 ++-
lib/librte_eal/common/include/arch/e2k/rte_vect.h | 5 +-
25 files changed, 185 insertions(+), 171 deletions(-)
diff --git a/lib/librte_eal/common/arch/e2k/rte_cpuflags.c b/lib/librte_eal/common/arch/e2k/rte_cpuflags.c
index 6cfff21..b849586 100644
--- a/lib/librte_eal/common/arch/e2k/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/e2k/rte_cpuflags.c
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018.
* Copyright (C) Cavium, Inc. 2015.
* Copyright(c) 2015 RehiveTech. All rights reserved.
*
@@ -78,7 +79,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
// FEAT_DEF(SWP, REG_HWCAP, 0)
};
/*
- * Read AUXV software register and get cpu features for ARM
+ * Read AUXV software register and get cpu features for E2K
*/
static void
rte_cpu_get_features(hwcap_registers_t out)
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_atomic.h b/lib/librte_eal/common/include/arch/e2k/rte_atomic.h
index f3f3b6e..9d099cf 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_atomic.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_atomic.h
@@ -1,6 +1,7 @@
/*-
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2015 RehiveTech. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_ATOMIC_ARM_H_
-#define _RTE_ATOMIC_ARM_H_
+#ifndef _RTE_ATOMIC_E2K_H_
+#define _RTE_ATOMIC_E2K_H_
#ifdef RTE_ARCH_64
#include <rte_atomic_64.h>
@@ -39,4 +40,4 @@
#include <rte_atomic_32.h>
#endif
-#endif /* _RTE_ATOMIC_ARM_H_ */
+#endif /* _RTE_ATOMIC_E2K_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_atomic_32.h b/lib/librte_eal/common/include/arch/e2k/rte_atomic_32.h
index 5ff5ea3..ff18e66 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_atomic_32.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_atomic_32.h
@@ -1,6 +1,7 @@
/*-
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2015 RehiveTech. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_ATOMIC_ARM32_H_
-#define _RTE_ATOMIC_ARM32_H_
+#ifndef _RTE_ATOMIC_E2K32_H_
+#define _RTE_ATOMIC_E2K32_H_
#ifndef RTE_FORCE_INTRINSICS
# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
@@ -49,7 +50,8 @@ extern "C" {
* Guarantees that the LOAD and STORE operations generated before the
* barrier occur before the LOAD and STORE operations generated after.
*/
-#define rte_mb() __sync_synchronize()
+//#define rte_mb() __sync_synchronize()
+#define rte_mb() do { asm volatile ("wait ld_c=1, st_c=1" : : : "memory"); } while (0)
/**
* Write memory barrier.
@@ -57,7 +59,7 @@ extern "C" {
* Guarantees that the STORE operations generated before the barrier
* occur before the STORE operations generated after.
*/
-#define rte_wmb() do { asm volatile ("wait all_c=1" : : : "memory"); } while (0)
+#define rte_wmb() do { asm volatile ("wait st_c=1" : : : "memory"); } while (0)
/**
* Read memory barrier.
@@ -83,4 +85,4 @@ extern "C" {
}
#endif
-#endif /* _RTE_ATOMIC_ARM32_H_ */
+#endif /* _RTE_ATOMIC_E2K32_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_atomic_64.h b/lib/librte_eal/common/include/arch/e2k/rte_atomic_64.h
index 40fe224..8d5b5f6 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_atomic_64.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright (C) Cavium, Inc. 2015.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_ATOMIC_ARM64_H_
-#define _RTE_ATOMIC_ARM64_H_
+#ifndef _RTE_ATOMIC_E2K64_H_
+#define _RTE_ATOMIC_E2K64_H_
#ifndef RTE_FORCE_INTRINSICS
# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
@@ -42,7 +43,7 @@ extern "C" {
#endif
#include "generic/rte_atomic.h"
-
+// TODO: use st_c=1 for some barriers
#define dsb() do { asm volatile("wait all_c=1" : : : "memory"); } while(0)
#define dmb() do { asm volatile("wait all_c=1" : : : "memory"); }while(0)
@@ -68,4 +69,4 @@ extern "C" {
}
#endif
-#endif /* _RTE_ATOMIC_ARM64_H_ */
+#endif /* _RTE_ATOMIC_E2K64_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_byteorder.h b/lib/librte_eal/common/include/arch/e2k/rte_byteorder.h
index b61e435..ee45c0f 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_byteorder.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_byteorder.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2015 RehiveTech. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_BYTEORDER_ARM_H_
-#define _RTE_BYTEORDER_ARM_H_
+#ifndef _RTE_BYTEORDER_E2K_H_
+#define _RTE_BYTEORDER_E2K_H_
#ifndef RTE_FORCE_INTRINSICS
# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
@@ -64,8 +65,8 @@ extern "C" {
// rte_arch_bswap16(x)))
//#endif
-/* ARM architecture is bi-endian (both big and little).
- * unlike ARM e2k is little-endian by default */
+/* E2K architecture is bi-endian (both big and little).
+ * unlike E2K e2k is little-endian by default */
#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
#define rte_cpu_to_le_16(x) (x)
@@ -107,4 +108,4 @@ extern "C" {
}
#endif
-#endif /* _RTE_BYTEORDER_ARM_H_ */
+#endif /* _RTE_BYTEORDER_E2K_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_cpuflags.h b/lib/librte_eal/common/include/arch/e2k/rte_cpuflags.h
index b8f6288..1620e84 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_cpuflags.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2015 RehiveTech. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_CPUFLAGS_ARM_H_
-#define _RTE_CPUFLAGS_ARM_H_
+#ifndef _RTE_CPUFLAGS_E2K_H_
+#define _RTE_CPUFLAGS_E2K_H_
#ifdef RTE_ARCH_64
#include <rte_cpuflags_64.h>
@@ -39,4 +40,4 @@
#include <rte_cpuflags_32.h>
#endif
-#endif /* _RTE_CPUFLAGS_ARM_H_ */
+#endif /* _RTE_CPUFLAGS_E2K_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_cpuflags_32.h b/lib/librte_eal/common/include/arch/e2k/rte_cpuflags_32.h
index b18782f..75983da 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_cpuflags_32.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_cpuflags_32.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2015 RehiveTech. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_CPUFLAGS_ARM32_H_
-#define _RTE_CPUFLAGS_ARM32_H_
+#ifndef _RTE_CPUFLAGS_E2K32_H_
+#define _RTE_CPUFLAGS_E2K32_H_
#ifdef __cplusplus
extern "C" {
@@ -43,34 +44,13 @@ extern "C" {
* Enumeration of all CPU features supported
*/
enum rte_cpu_flag_t {
- RTE_CPUFLAG_SWP = 0,
- RTE_CPUFLAG_HALF,
- RTE_CPUFLAG_THUMB,
- RTE_CPUFLAG_A26BIT,
- RTE_CPUFLAG_FAST_MULT,
- RTE_CPUFLAG_FPA,
- RTE_CPUFLAG_VFP,
- RTE_CPUFLAG_EDSP,
- RTE_CPUFLAG_JAVA,
- RTE_CPUFLAG_IWMMXT,
- RTE_CPUFLAG_CRUNCH,
- RTE_CPUFLAG_THUMBEE,
- RTE_CPUFLAG_NEON,
- RTE_CPUFLAG_VFPv3,
- RTE_CPUFLAG_VFPv3D16,
- RTE_CPUFLAG_TLS,
- RTE_CPUFLAG_VFPv4,
- RTE_CPUFLAG_IDIVA,
- RTE_CPUFLAG_IDIVT,
- RTE_CPUFLAG_VFPD32,
- RTE_CPUFLAG_LPAE,
- RTE_CPUFLAG_EVTSTRM,
- RTE_CPUFLAG_AES,
- RTE_CPUFLAG_PMULL,
- RTE_CPUFLAG_SHA1,
- RTE_CPUFLAG_SHA2,
- RTE_CPUFLAG_CRC32,
- RTE_CPUFLAG_V7L,
+ RTE_CPUFLAG_V1 = 0,
+ RTE_CPUFLAG_V2,
+ RTE_CPUFLAG_V3,
+ RTE_CPUFLAG_V4,
+ RTE_CPUFLAG_V5,
+ RTE_CPUFLAG_V6,
+ RTE_CPUFLAG_V7,
/* The last item */
RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
};
@@ -81,4 +61,4 @@ enum rte_cpu_flag_t {
}
#endif
-#endif /* _RTE_CPUFLAGS_ARM32_H_ */
+#endif /* _RTE_CPUFLAGS_E2K32_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_cpuflags_64.h b/lib/librte_eal/common/include/arch/e2k/rte_cpuflags_64.h
index 04f6c17..8c555e6 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_cpuflags_64.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_cpuflags_64.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright (C) Cavium, Inc. 2015.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_CPUFLAGS_ARM64_H_
-#define _RTE_CPUFLAGS_ARM64_H_
+#ifndef _RTE_CPUFLAGS_E2K64_H_
+#define _RTE_CPUFLAGS_E2K64_H_
#ifdef __cplusplus
extern "C" {
@@ -41,18 +42,15 @@ extern "C" {
* Enumeration of all CPU features supported
*/
enum rte_cpu_flag_t {
-/* RTE_CPUFLAG_FP = 0,
- RTE_CPUFLAG_NEON,
- RTE_CPUFLAG_EVTSTRM,
- RTE_CPUFLAG_AES,
- RTE_CPUFLAG_PMULL,
- RTE_CPUFLAG_SHA1,
- RTE_CPUFLAG_SHA2,
- RTE_CPUFLAG_CRC32,
- RTE_CPUFLAG_ATOMICS,
- RTE_CPUFLAG_AARCH64,*/
+ RTE_CPUFLAG_V1 = 0,
+ RTE_CPUFLAG_V2,
+ RTE_CPUFLAG_V3,
+ RTE_CPUFLAG_V4,
+ RTE_CPUFLAG_V5,
+ RTE_CPUFLAG_V6,
+ RTE_CPUFLAG_V7,
/* The last item */
- RTE_CPUFLAG_NUMFLAGS = 0/**< This should always be the last! */
+ RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
};
#include "generic/rte_cpuflags.h"
@@ -61,4 +59,4 @@ enum rte_cpu_flag_t {
}
#endif
-#endif /* _RTE_CPUFLAGS_ARM64_H_ */
+#endif /* _RTE_CPUFLAGS_E2K64_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_cycles.h b/lib/librte_eal/common/include/arch/e2k/rte_cycles.h
index a8009a0..5d938f2 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_cycles.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_cycles.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2015 RehiveTech. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_CYCLES_ARM_H_
-#define _RTE_CYCLES_ARM_H_
+#ifndef _RTE_CYCLES_E2K_H_
+#define _RTE_CYCLES_E2K_H_
#ifdef RTE_ARCH_64
#include <rte_cycles_64.h>
@@ -39,4 +40,4 @@
#include <rte_cycles_32.h>
#endif
-#endif /* _RTE_CYCLES_ARM_H_ */
+#endif /* _RTE_CYCLES_E2K_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_cycles_32.h b/lib/librte_eal/common/include/arch/e2k/rte_cycles_32.h
index ebc012d..14c5164 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_cycles_32.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_cycles_32.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2015 RehiveTech. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,15 +31,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_CYCLES_ARM32_H_
-#define _RTE_CYCLES_ARM32_H_
+#ifndef _RTE_CYCLES_E2K32_H_
+#define _RTE_CYCLES_E2K32_H_
-/* ARM v7 does not have suitable source of clock signals. The only clock counter
- available in the core is 32 bit wide. Therefore it is unsuitable as the
- counter overlaps every few seconds and probably is not accessible by
- userspace programs. Therefore we use clock_gettime(CLOCK_MONOTONIC_RAW) to
- simulate counter running at 1GHz.
-*/
+/* E2K has two sources of clock signals: clkr and sclkr */
#include <time.h>
@@ -54,10 +50,10 @@ extern "C" {
* @return
* The time base for this lcore.
*/
-#ifndef RTE_ARM_EAL_RDTSC_USE_PMU
+#ifdef RTE_E2K_EAL_RDTSC_USE_SYSCALL
/**
- * This call is easily portable to any ARM architecture, however,
+ * This call is easily portable to any architecture, however,
* it may be damn slow and inprecise for some tasks.
*/
static inline uint64_t
@@ -75,33 +71,30 @@ __rte_rdtsc_syscall(void)
}
#define rte_rdtsc __rte_rdtsc_syscall
-#else
+#else /* RTE_E2K_EAL_RDTSC_USE_SYSCALL */
/**
- * This function requires to configure the PMCCNTR and enable
- * userspace access to it:
- *
- * asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(1));
- * asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(29));
- * asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r"(0x8000000f));
+ * Read the time base register.
*
- * which is possible only from the priviledged mode (kernel space).
+ * @return
+ * The time base for this lcore.
*/
static inline uint64_t
-__rte_rdtsc_pmccntr(void)
+__rte_rdtsc_clkr(void)
{
uint64_t final_tsc;
asm volatile("rrd %%clkr, %0" : "=r"(final_tsc));
return (uint64_t)final_tsc;
}
-#define rte_rdtsc __rte_rdtsc_pmccntr
+#define rte_rdtsc __rte_rdtsc_clkr
-#endif /* RTE_ARM_EAL_RDTSC_USE_PMU */
+#endif /* RTE_E2K_EAL_RDTSC_USE_SYSCALL */
static inline uint64_t
rte_rdtsc_precise(void)
{
- rte_mb();
+/* Not needed for in-order variants */
+/* rte_mb(); */
return rte_rdtsc();
}
@@ -112,4 +105,4 @@ rte_get_tsc_cycles(void) { return rte_rdtsc(); }
}
#endif
-#endif /* _RTE_CYCLES_ARM32_H_ */
+#endif /* _RTE_CYCLES_E2K32_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_cycles_64.h b/lib/librte_eal/common/include/arch/e2k/rte_cycles_64.h
index dd448b3..8d791fa 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_cycles_64.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_cycles_64.h
@@ -1,7 +1,8 @@
/*
* BSD LICENSE
*
- * Copyright (C) Cavium, Inc. 2015.
+ * Copyright (C) AO MCST. 2018
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -13,7 +14,7 @@
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
- * * Neither the name of Cavium, Inc nor the names of its
+ * * Neither the name of RehiveTech nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
@@ -28,10 +29,14 @@
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ */
+
+#ifndef _RTE_CYCLES_E2K64_H_
+#define _RTE_CYCLES_E2K64_H_
-#ifndef _RTE_CYCLES_ARM64_H_
-#define _RTE_CYCLES_ARM64_H_
+/* E2K has two sources of clock signals: clkr and sclkr */
+
+#include <time.h>
#ifdef __cplusplus
extern "C" {
@@ -45,51 +50,51 @@ extern "C" {
* @return
* The time base for this lcore.
*/
-#ifndef RTE_ARM_EAL_RDTSC_USE_PMU
+#ifdef RTE_E2K_EAL_RDTSC_USE_SYSCALL
+
/**
- * This call is portable to any ARMv8 architecture, however, typically
- * cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks.
+ * This call is easily portable to any architecture, however,
+ * it may be damn slow and inprecise for some tasks.
*/
static inline uint64_t
-rte_rdtsc(void)
+__rte_rdtsc_syscall(void)
{
- uint64_t tsc;
- asm volatile("rrd %%clkr, %0" : "=r"(tsc));
- return tsc;
+ struct timespec val;
+ uint64_t v;
+
+ while (clock_gettime(CLOCK_MONOTONIC_RAW, &val) != 0)
+ /* no body */;
+
+ v = (uint64_t) val.tv_sec * 1000000000LL;
+ v += (uint64_t) val.tv_nsec;
+ return v;
}
-#else
+#define rte_rdtsc __rte_rdtsc_syscall
+
+#else /* RTE_E2K_EAL_RDTSC_USE_SYSCALL */
+
/**
- * This is an alternative method to enable rte_rdtsc() with high resolution
- * PMU cycles counter.The cycle counter runs at cpu frequency and this scheme
- * uses ARMv8 PMU subsystem to get the cycle counter at userspace, However,
- * access to PMU cycle counter from user space is not enabled by default in
- * arm64 linux kernel.
- * It is possible to enable cycle counter at user space access by configuring
- * the PMU from the privileged mode (kernel space).
- *
- * asm volatile("msr pmintenset_el1, %0" : : "r" ((u64)(0 << 31)));
- * asm volatile("msr pmcntenset_el0, %0" :: "r" BIT(31));
- * asm volatile("msr pmuserenr_el0, %0" : : "r"(BIT(0) | BIT(2)));
- * asm volatile("mrs %0, pmcr_el0" : "=r" (val));
- * val |= (BIT(0) | BIT(2));
- * isb();
- * asm volatile("msr pmcr_el0, %0" : : "r" (val));
+ * Read the time base register.
*
+ * @return
+ * The time base for this lcore.
*/
static inline uint64_t
-rte_rdtsc(void)
+__rte_rdtsc_clkr(void)
{
- uint64_t tsc;
-
- asm volatile("rrd %%clkr, %0" : "=r"(tsc));
- return tsc;
+ uint64_t final_tsc;
+ asm volatile("rrd %%clkr, %0" : "=r"(final_tsc));
+ return (uint64_t)final_tsc;
}
-#endif
+#define rte_rdtsc __rte_rdtsc_clkr
+
+#endif /* RTE_E2K_EAL_RDTSC_USE_SYSCALL */
static inline uint64_t
rte_rdtsc_precise(void)
{
- rte_mb();
+/* Not needed for in-order variants */
+/* rte_mb(); */
return rte_rdtsc();
}
@@ -100,4 +105,4 @@ rte_get_tsc_cycles(void) { return rte_rdtsc(); }
}
#endif
-#endif /* _RTE_CYCLES_ARM64_H_ */
+#endif /* _RTE_CYCLES_E2K64_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_io.h b/lib/librte_eal/common/include/arch/e2k/rte_io.h
index 3b63ec8..4378905 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_io.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_io.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2016 Cavium, Inc. All rights reserved.
* All rights reserved.
*
@@ -31,8 +32,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_IO_ARM_H_
-#define _RTE_IO_ARM_H_
+#ifndef _RTE_IO_E2K_H_
+#define _RTE_IO_E2K_H_
#ifdef __cplusplus
extern "C" {
@@ -41,6 +42,7 @@ extern "C" {
#ifdef RTE_ARCH_64
#include "rte_io_64.h"
#else
+#error E2K32_IO_NOT_IMPLEMENTED
#include "generic/rte_io.h"
#endif
@@ -48,4 +50,4 @@ extern "C" {
}
#endif
-#endif /* _RTE_IO_ARM_H_ */
+#endif /* _RTE_IO_E2K_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_io_64.h b/lib/librte_eal/common/include/arch/e2k/rte_io_64.h
index ba0f64e..c9609f7 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_io_64.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_io_64.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright (C) Cavium, Inc. 2016.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_IO_ARM64_H_
-#define _RTE_IO_ARM64_H_
+#ifndef _RTE_IO_E2K64_H_
+#define _RTE_IO_E2K64_H_
#ifdef __cplusplus
extern "C" {
@@ -44,7 +45,7 @@ extern "C" {
#include "generic/rte_io.h"
#include "rte_atomic_64.h"
// Do check asm/io.h
-// FIXME e3s/kubik needs some serializing; and other don't
+// FIXME TODO e3s/kubik needs some serializing; and other don't
static __rte_always_inline uint8_t
rte_read8_relaxed(const volatile void *addr)
{
@@ -197,4 +198,4 @@ rte_write64(uint64_t value, volatile void *addr)
}
#endif
-#endif /* _RTE_IO_ARM64_H_ */
+#endif /* _RTE_IO_E2K64_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_memcpy.h b/lib/librte_eal/common/include/arch/e2k/rte_memcpy.h
index 1d562c3..337da76 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_memcpy.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_memcpy.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2015 RehiveTech. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_MEMCPY_ARM_H_
-#define _RTE_MEMCPY_ARM_H_
+#ifndef _RTE_MEMCPY_E2K_H_
+#define _RTE_MEMCPY_E2K_H_
#ifdef RTE_ARCH_64
#include <rte_memcpy_64.h>
@@ -39,4 +40,4 @@
#include <rte_memcpy_32.h>
#endif
-#endif /* _RTE_MEMCPY_ARM_H_ */
+#endif /* _RTE_MEMCPY_E2K_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_memcpy_32.h b/lib/librte_eal/common/include/arch/e2k/rte_memcpy_32.h
index b471a3d..7b0ede5 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_memcpy_32.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_memcpy_32.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2015 RehiveTech. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_MEMCPY_ARM32_H_
-#define _RTE_MEMCPY_ARM32_H_
+#ifndef _RTE_MEMCPY_E2K32_H_
+#define _RTE_MEMCPY_E2K32_H_
#include <stdint.h>
#include <string.h>
@@ -90,4 +91,4 @@ rte_memcpy(void *dst, const void *src, size_t n)
}
#endif
-#endif /* _RTE_MEMCPY_ARM32_H_ */
+#endif /* _RTE_MEMCPY_E2K32_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_memcpy_64.h b/lib/librte_eal/common/include/arch/e2k/rte_memcpy_64.h
index b80d8ba..689b3ff 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_memcpy_64.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_memcpy_64.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright (C) Cavium, Inc. 2015.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_MEMCPY_ARM64_H_
-#define _RTE_MEMCPY_ARM64_H_
+#ifndef _RTE_MEMCPY_E2K64_H_
+#define _RTE_MEMCPY_E2K64_H_
#ifdef __cplusplus
extern "C" {
@@ -84,4 +85,4 @@ rte_mov256(uint8_t *dst, const uint8_t *src)
}
#endif
-#endif /* _RTE_MEMCPY_ARM_64_H_ */
+#endif /* _RTE_MEMCPY_E2K_64_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_pause.h b/lib/librte_eal/common/include/arch/e2k/rte_pause.h
index b772ca0..33c2616 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_pause.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_pause.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2017 Cavium, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_PAUSE_ARM_H_
-#define _RTE_PAUSE_ARM_H_
+#ifndef _RTE_PAUSE_E2K_H_
+#define _RTE_PAUSE_E2K_H_
#ifdef __cplusplus
extern "C" {
@@ -47,4 +48,4 @@ extern "C" {
}
#endif
-#endif /* _RTE_PAUSE_ARM_H_ */
+#endif /* _RTE_PAUSE_E2K_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_pause_32.h b/lib/librte_eal/common/include/arch/e2k/rte_pause_32.h
index ec680b5..5c28592 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_pause_32.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_pause_32.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2017 Cavium, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_PAUSE_ARM32_H_
-#define _RTE_PAUSE_ARM32_H_
+#ifndef _RTE_PAUSE_E2K32_H_
+#define _RTE_PAUSE_E2K32_H_
#ifdef __cplusplus
extern "C" {
@@ -42,10 +43,12 @@ extern "C" {
static inline void rte_pause(void)
{
+/* TODO E2K: nop?*/
+ asm volatile ("nop 5");
}
#ifdef __cplusplus
}
#endif
-#endif /* _RTE_PAUSE_ARM32_H_ */
+#endif /* _RTE_PAUSE_E2K32_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_pause_64.h b/lib/librte_eal/common/include/arch/e2k/rte_pause_64.h
index 34bdd4d..568205f 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_pause_64.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_pause_64.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2017 Cavium, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_PAUSE_ARM64_H_
-#define _RTE_PAUSE_ARM64_H_
+#ifndef _RTE_PAUSE_E2K64_H_
+#define _RTE_PAUSE_E2K64_H_
#ifdef __cplusplus
extern "C" {
@@ -43,10 +44,12 @@ extern "C" {
static inline void rte_pause(void)
{
// asm volatile("yield" ::: "memory");
+/* TODO E2K: nop?*/
+ asm volatile ("nop 5");
}
#ifdef __cplusplus
}
#endif
-#endif /* _RTE_PAUSE_ARM64_H_ */
+#endif /* _RTE_PAUSE_E2K64_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_prefetch.h b/lib/librte_eal/common/include/arch/e2k/rte_prefetch.h
index aa37de5..df4ad06 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_prefetch.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_prefetch.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2015 RehiveTech. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_PREFETCH_ARM_H_
-#define _RTE_PREFETCH_ARM_H_
+#ifndef _RTE_PREFETCH_E2K_H_
+#define _RTE_PREFETCH_E2K_H_
#ifdef RTE_ARCH_64
#include <rte_prefetch_64.h>
@@ -39,4 +40,4 @@
#include <rte_prefetch_32.h>
#endif
-#endif /* _RTE_PREFETCH_ARM_H_ */
+#endif /* _RTE_PREFETCH_E2K_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_prefetch_32.h b/lib/librte_eal/common/include/arch/e2k/rte_prefetch_32.h
index f8c25bc..8e8306a 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_prefetch_32.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_prefetch_32.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2015 RehiveTech. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_PREFETCH_ARM32_H_
-#define _RTE_PREFETCH_ARM32_H_
+#ifndef _RTE_PREFETCH_E2K32_H_
+#define _RTE_PREFETCH_E2K32_H_
#ifdef __cplusplus
extern "C" {
@@ -58,6 +59,9 @@ static inline void rte_prefetch2(const volatile void *p)
static inline void rte_prefetch_non_temporal(const volatile void *p)
{
/* non-temporal version not available, fallback to rte_prefetch0 */
+ /* TODO: check C.11.1.3.1 */
+ /* _mm_stream_load_si128 = __builtin_ia32_movntdqa = __builtin_e2k_ld_64s_nta =
+ * ((__di) __builtin_loadmas_64u (pval, 0x60, __LCC_CHAN_ANY)) ?? */
rte_prefetch0(p);
// __builtin_prefetch (p, 1, 0);
}
@@ -66,4 +70,4 @@ static inline void rte_prefetch_non_temporal(const volatile void *p)
}
#endif
-#endif /* _RTE_PREFETCH_ARM32_H_ */
+#endif /* _RTE_PREFETCH_E2K32_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_prefetch_64.h b/lib/librte_eal/common/include/arch/e2k/rte_prefetch_64.h
index 4301fc1..f6d907e 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_prefetch_64.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_prefetch_64.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright (C) Cavium, Inc. 2015.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_PREFETCH_ARM_64_H_
-#define _RTE_PREFETCH_ARM_64_H_
+#ifndef _RTE_PREFETCH_E2K_64_H_
+#define _RTE_PREFETCH_E2K_64_H_
#ifdef __cplusplus
extern "C" {
@@ -58,6 +59,9 @@ static inline void rte_prefetch2(const volatile void *p)
static inline void rte_prefetch_non_temporal(const volatile void *p)
{
/* non-temporal version not available, fallback to rte_prefetch0 */
+ /* TODO: check C.11.1.3.1 */
+ /* _mm_stream_load_si128 = __builtin_ia32_movntdqa = __builtin_e2k_ld_64s_nta =
+ * ((__di) __builtin_loadmas_64u (pval, 0x60, __LCC_CHAN_ANY)) ?? */
rte_prefetch0(p);
// __builtin_prefetch (p, 1, 0);
}
@@ -66,4 +70,4 @@ static inline void rte_prefetch_non_temporal(const volatile void *p)
}
#endif
-#endif /* _RTE_PREFETCH_ARM_64_H_ */
+#endif /* _RTE_PREFETCH_E2K_64_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_rwlock.h b/lib/librte_eal/common/include/arch/e2k/rte_rwlock.h
index 664bec8..fdb7150 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_rwlock.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_rwlock.h
@@ -1,7 +1,12 @@
-/* copied from ppc_64 */
+/*
+ * BSD License
+ *
+ * Copyright (C) AO MCST. 2018
+ * copied from ppc_64
+ */
-#ifndef _RTE_RWLOCK_ARM_H_
-#define _RTE_RWLOCK_ARM_H_
+#ifndef _RTE_RWLOCK_E2K_H_
+#define _RTE_RWLOCK_E2K_H_
#ifdef __cplusplus
extern "C" {
@@ -37,4 +42,4 @@ rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)
}
#endif
-#endif /* _RTE_RWLOCK_ARM_H_ */
+#endif /* _RTE_RWLOCK_E2K_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_spinlock.h b/lib/librte_eal/common/include/arch/e2k/rte_spinlock.h
index 396a42e..b466b19 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_spinlock.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_spinlock.h
@@ -1,6 +1,7 @@
/*
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2015 RehiveTech. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_SPINLOCK_ARM_H_
-#define _RTE_SPINLOCK_ARM_H_
+#ifndef _RTE_SPINLOCK_E2K_H_
+#define _RTE_SPINLOCK_E2K_H_
#ifndef RTE_FORCE_INTRINSICS
# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
@@ -52,6 +53,7 @@ static inline int rte_tm_supported(void)
static inline void
rte_spinlock_lock_tm(rte_spinlock_t *sl)
{
+ /* rasp:: E2K FIXME TODO: native spinlock has bit less code and loops */
rte_spinlock_lock(sl); /* fall-back */
}
@@ -89,4 +91,4 @@ rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)
}
#endif
-#endif /* _RTE_SPINLOCK_ARM_H_ */
+#endif /* _RTE_SPINLOCK_E2K_H_ */
diff --git a/lib/librte_eal/common/include/arch/e2k/rte_vect.h b/lib/librte_eal/common/include/arch/e2k/rte_vect.h
index 92afc3b..56446ae 100644
--- a/lib/librte_eal/common/include/arch/e2k/rte_vect.h
+++ b/lib/librte_eal/common/include/arch/e2k/rte_vect.h
@@ -1,6 +1,7 @@
/*-
* BSD LICENSE
*
+ * Copyright (C) AO MCST. 2018
* Copyright(c) 2015 Cavium, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,8 +31,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef _RTE_VECT_ARM_H_
-#define _RTE_VECT_ARM_H_
+#ifndef _RTE_VECT_E2K_H_
+#define _RTE_VECT_E2K_H_
#include <stdint.h>
#include "generic/rte_vect.h"
--
2.16.4
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