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87 lines
2.1 KiB
C
87 lines
2.1 KiB
C
#ifndef _ASM_X86_BARRIER_H
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#define _ASM_X86_BARRIER_H
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#include <asm/alternative.h>
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#include <asm/nops.h>
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/*
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* Force strict CPU ordering.
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* And yes, this might be required on UP too when we're talking
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* to devices.
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*/
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#ifdef CONFIG_X86_32
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/*
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* Some non-Intel clones support out of order store. wmb() ceases to be a
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* nop for these.
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*/
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#define mb() asm volatile ("lock; addl $0,0(%esp)")/*, "mfence", X86_FEATURE_XMM2) */
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#define rmb() asm volatile("lock; addl $0,0(%esp)")/*, "lfence", X86_FEATURE_XMM2) */
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#define wmb() asm volatile("lock; addl $0,0(%esp)")/*, "sfence", X86_FEATURE_XMM) */
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#else
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#define mb() asm volatile("mfence":::"memory")
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#define rmb() asm volatile("lfence":::"memory")
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#define wmb() asm volatile("sfence" ::: "memory")
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#endif
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#ifdef CONFIG_X86_PPRO_FENCE
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#define dma_rmb() rmb()
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#else
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#define dma_rmb() barrier()
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#endif
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#define dma_wmb() barrier()
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#define __smp_mb() mb()
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#define __smp_rmb() dma_rmb()
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#define __smp_wmb() barrier()
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#define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0)
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#if defined(CONFIG_X86_PPRO_FENCE)
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/*
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* For this option x86 doesn't have a strong TSO memory
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* model and we should fall back to full barriers.
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*/
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#define __smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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__smp_mb(); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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__smp_mb(); \
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___p1; \
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})
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#else /* regular x86 TSO memory ordering */
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#define __smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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___p1; \
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})
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#endif
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/* Atomic operations are already serializing on x86 */
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#define __smp_mb__before_atomic() barrier()
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#define __smp_mb__after_atomic() barrier()
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#include <asm-generic/barrier.h>
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#endif /* _ASM_X86_BARRIER_H */
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