mirror of
https://github.com/KolibriOS/kolibrios.git
synced 2024-12-04 22:32:05 +03:00
321 lines
11 KiB
NASM
321 lines
11 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2020. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;; PCMCIA aka cardbus driver for KolibriOS ;;
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;; Written by hidnplayr@gmail.com ;;
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;; ;;
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;; Many credits go to Paolo Franchetti for his HWTEST program ;;
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;; (https://sites.google.com/site/pfranz73/) from which large ;;
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;; parts of code have been borrowed. ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; This module detects and initialises all Cardbus/pc-card/PCMCIA cards.
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; WARNING: Cards must be inserted before the driver starts, and shouldn't be removed.
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; This module doesn't handle insertions and removals.
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; TODO:
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;
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; Use GetPCIList instead of reading directly from PCI bus to detect bridge.
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; (See #5544 agp.asm for example).
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; Export a function in kernel to re-scan PCI device list (fix 'dirty hack').
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; Fix bugs (currently not working on all PCMCIA bridges).
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format PE DLL native
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entry START
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CURRENT_API = 0x0200
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COMPATIBLE_API = 0x0100
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API_VERSION = (COMPATIBLE_API shl 16) + CURRENT_API
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CARDBUS_IO_BASE = 0x1400
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CARDBUS_IO_SIZE = 0x100
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CARDBUS_IRQ = 0x0A
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__DEBUG__ = 1
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__DEBUG_LEVEL__ = 1
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section '.flat' readable writable executable
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include '../proc32.inc'
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include '../struct.inc'
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include '../macros.inc'
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include '../pci.inc'
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include '../fdo.inc'
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; proc START ;;
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;; ;;
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;; (standard driver proc) ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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proc START c, reason:dword, cmdline:dword
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cmp [reason], DRV_ENTRY
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jne .fail
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DEBUGF 1, "Loading cardbus driver\n"
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invoke RegService, my_service, service_proc
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call detect
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ret
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.fail:
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xor eax, eax
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ret
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endp
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; proc SERVICE_PROC ;;
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;; ;;
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;; (standard driver proc) ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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proc service_proc stdcall, ioctl:dword
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mov edx, [ioctl]
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mov eax, [edx + IOCTL.io_code]
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;------------------------------------------------------
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cmp eax, 0 ;SRV_GETVERSION
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jne .fail
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cmp [edx + IOCTL.out_size], 4
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jb .fail
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mov eax, [edx + IOCTL.output]
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mov [eax], dword API_VERSION
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xor eax, eax
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ret
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.fail:
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or eax, -1
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ret
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endp
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align 4
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proc detect
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locals
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last_bus dd ?
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card_bus dd ?
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bus dd ?
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devfn dd ?
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endl
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DEBUGF 1, "Searching for cardbus bridges...\n"
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xor eax, eax
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mov [bus], eax
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inc eax
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invoke PciApi
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cmp eax, -1
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je .err
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mov [last_bus], eax
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inc eax
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mov [card_bus], eax
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.next_bus:
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and [devfn], 0
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.next_dev:
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invoke PciRead32, [bus], [devfn], PCI_header.vendor_id
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test eax, eax
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jz .next
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cmp eax, -1
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je .next
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invoke PciRead16, [bus], [devfn], PCI_header.subclass ; class & subclass
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cmp ax, 0x0607
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je .found
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.next:
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test [devfn], 7
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jnz .next_fn
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invoke PciRead8, [bus], [devfn], PCI_header.header_type
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test al, al
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js .next_fn
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or [devfn], 7
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.next_fn:
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inc [devfn]
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cmp [devfn], 256
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jb .next_dev
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mov eax, [bus]
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inc eax
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mov [bus], eax
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cmp eax, [last_bus]
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jna .next_bus
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DEBUGF 1, "Search complete\n"
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xor eax, eax
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inc eax
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ret
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.found:
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DEBUGF 1, "Found cardbus bridge: bus=0x%x, dev=0x%x\n", [bus], [devfn]
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invoke PciRead8, [bus], [devfn], PCI_header.header_type
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and al, not 0x80 ; Mask the multifunction device bit
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DEBUGF 1, "Header type=0x%x\n", eax:2
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cmp al, 2
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jne .next
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; Write PCI and cardbus numbers
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invoke PciRead32, [bus], [devfn], PCI_header02.pci_bus_nr ; PCcard latency settings + Card bus number, PCI bus number
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and eax, 0xff000000 ; Keep original latency setting, clear the rest
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mov al, byte[bus]
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mov ah, byte[card_bus]
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mov ebx, [card_bus] ; sub bus nr???
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shl ebx, 16
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or eax, ebx
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DEBUGF 1, "Latency, bus,.. 0x%x\n", eax
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invoke PciWrite32, [bus], [devfn], PCI_header02.pci_bus_nr, eax
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; set ExCA legacy mode base
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invoke PciWrite32, [bus], [devfn], 0x44, 1
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; Enable power
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invoke PciRead8, [bus], [devfn], PCI_header02.cap_list_offs ; get capabilities offset
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movzx eax, al ; (A0 for TI bridges)
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DEBUGF 1, "Capabilities offset=0x%x\n", eax:2
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add al, 4 ; Power management control/status
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invoke PciWrite16, [bus], [devfn], eax, 0x0100 ; Enable PME signaling, power state=D0
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; Enable Bus master, io space, memory space
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invoke PciWrite16, [bus], [devfn], PCI_header02.command, PCI_CMD_PIO or PCI_CMD_MMIO or PCI_CMD_MASTER
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; Write CardBus Socket/ExCA base address
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mov eax, 0x7f000000
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push eax
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invoke PciWrite32, [bus], [devfn], PCI_header02.base_addr, eax ; base is 4 Kbyte aligned
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pop ebx
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invoke MapIoMem, ebx, 4096, PG_SW+PG_NOCACHE
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mov ecx, eax
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; Check if a card is present in the socket
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mov eax, [ecx + 8] ; Socket present state register
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DEBUGF 1, "Socket present state reg: 0x%x\n", eax
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and al, 10110110b ; NotACard | CBCard | 16bitCard | CDetect1 | CDetect2
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cmp al, 00100000b ; Check for inserted cardbus card
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je .CardbusInserted
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; No card found... set PCI command back to 0
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invoke PciWrite16, [bus], [devfn], PCI_header02.command, 0 ; To avoid conflicts with other sockets
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DEBUGF 1, "Cardbus KO\n"
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jmp .next
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.CardbusInserted:
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DEBUGF 1, "Card inserted\n"
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;mov word[ecx + 0x802], 0x00F9 ; Assert reset, output enable, vcc=vpp=3.3V
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mov dword[ecx + 0x10], 0x33 ; Request 3.3V for Vcc and Vpp (Control register)
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;push ecx
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;mov esi, 1
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;invoke Sleep
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;pop ecx
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;mov byte[ecx + 0x803], 0x40 ; stop reset
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mov dword[ecx + 0xC], 0x4000 ; force Card CV test (Force register) ;;; WHY???
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DEBUGF 1, "Resetting card\n"
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; Next power up test can be deferred until before writing to Bridge control PCI reg 0x3E
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.waitpower: ; For TI, you can check that bits 8-11 in PCI reg 80h are all 0
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test dword[ecx + 8], 1 shl 3 ; Test PWRCYCLE bit
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jz .waitpower ; Wait for power to go up
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DEBUGF 1, "Interface is powered up\n"
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; Write MemBase-Limit 0 and 1, then IOBase-Limit 0 and 1
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; mem0 space limit = base => size is 4 kilobytes
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; set to 0 the second interval (mem1 and IO1)
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; IO0: size is 256 bytes
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invoke PciWrite32, [bus], [devfn], PCI_header02.mbar_0, 0x7EFFF000
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invoke PciWrite32, [bus], [devfn], PCI_header02.mlimit_0, 0x7EFFF000
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invoke PciWrite32, [bus], [devfn], PCI_header02.mbar_1, 0
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invoke PciWrite32, [bus], [devfn], PCI_header02.mlimit_1, 0
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invoke PciWrite32, [bus], [devfn], PCI_header02.iobar_0, CARDBUS_IO
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invoke PciWrite32, [bus], [devfn], PCI_header02.iolimit_0, CARDBUS_IO + 0xFC
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invoke PciWrite32, [bus], [devfn], PCI_header02.iobar_1, 0
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invoke PciWrite32, [bus], [devfn], PCI_header02.iolimit_1, 0
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invoke PciWrite8, [bus], [devfn], PCI_header02.interrupt_line, CARDBUS_IRQ ; IRQ line
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invoke PciRead16, [bus], [devfn], PCI_header02.bridge_ctrl ; Bridge control
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or ax, 0x0700 ; Enable write posting, both memory windows prefetchable
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invoke PciWrite16, [bus], [devfn], PCI_header02.bridge_ctrl, eax
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DEBUGF 1, "Write posting enabled\n"
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DEBUGF 1, "Bridge PCI registers:\n"
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rept 17 reg
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{
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invoke PciRead32, [bus], [devfn], 4*(reg-1)
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DEBUGF 1, "0x%x\n", eax
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}
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inc byte[0x80009021] ; LAST PCI bus count in kernel (dirty HACK!)
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mov ecx, 100
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.waitactive:
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push ecx
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invoke PciRead32, [card_bus], 0, PCI_header.vendor_id ; Check if the card is awake yet
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inc eax
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jnz .got_it
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mov esi, 2
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invoke Sleep
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pop ecx
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dec ecx
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jnz .waitactive
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DEBUGF 1, "Timeout!\n"
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; TODO: disable card/bridge again ?
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jmp .next
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.got_it:
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pop eax
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DEBUGF 1, "Card is enabled!\n"
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invoke PciWrite32, [card_bus], 0, PCI_header02.base_addr, CARDBUS_IO ; Supposing it's IO space that is needed
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invoke PciWrite8, [card_bus], 0, PCI_header02.interrupt_line, 0xC ; FIXME
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invoke PciWrite16, [card_bus], 0, PCI_header02.command, PCI_CMD_PIO or PCI_CMD_MMIO
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DEBUGF 1, "done\n"
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jmp .next
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.err:
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DEBUGF 1, "Error\n"
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xor eax, eax
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ret
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endp
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; End of code
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data fixups
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end data
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include '../peimport.inc'
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my_service db 'CARDBUS',0 ; max 16 chars include zero
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include_debug_strings ; All data wich FDO uses will be included here |