mirror of
https://github.com/KolibriOS/kolibrios.git
synced 2024-12-24 23:56:49 +03:00
251 lines
9.6 KiB
C
251 lines
9.6 KiB
C
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#define ACPI_NAME_SIZE 4
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#define ACPI_OEM_ID_SIZE 6
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#define ACPI_OEM_TABLE_ID_SIZE 8
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typedef struct __attribute__((packed))
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{
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u8_t type;
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u8_t len;
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}acpi_madt_hdr_t;
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typedef struct __attribute__((packed))
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{
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acpi_madt_hdr_t header;
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u8_t apic_processor_id;
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u8_t id;
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struct {
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u32_t enabled : 1;
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u32_t : 31;
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} flags;
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}acpi_madt_lapic_t;
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typedef struct __attribute__((packed))
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{
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acpi_madt_hdr_t header;
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u8_t id; /* APIC id */
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u8_t _rsvd_3;
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u32_t address; /* physical address */
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u32_t irq_base; /* global irq number base */
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}acpi_madt_ioapic_t;
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typedef enum {
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conform_polarity = 0,
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active_high = 1,
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reserved_polarity = 2,
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active_low = 3
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}polarity_t ;
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typedef enum {
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conform_trigger = 0,
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edge = 1,
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reserved_trigger = 2,
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level = 3
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}trigger_mode_t;
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typedef struct __attribute__((packed))
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{
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acpi_madt_hdr_t header;
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u8_t src_bus; /* source bus, fixed 0=ISA */
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u8_t src_irq; /* source bus irq */
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u32_t dest; /* global irq number */
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union {
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u16_t flags; /* irq flags */
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struct {
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u16_t polarity : 2;
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u16_t trigger_mode : 2;
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u16_t reserved : 12;
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} x;
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};
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}acpi_madt_irq_t;
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static inline polarity_t irq_get_polarity(acpi_madt_irq_t *irq)
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{ return (polarity_t) irq->x.polarity; }
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static inline trigger_mode_t irq_get_trigger_mode(acpi_madt_irq_t *irq)
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{ return (trigger_mode_t) irq->x.trigger_mode; }
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typedef struct __attribute__((packed))
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{
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acpi_madt_hdr_t header;
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union {
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u16_t flags;
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struct {
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u16_t polarity : 2;
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u16_t trigger_mode : 2;
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u16_t reserved : 12;
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} x;
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};
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u32_t irq;
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}acpi_madt_nmi_t;
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static inline polarity_t nmi_get_polarity(acpi_madt_nmi_t *nmi)
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{ return (polarity_t) nmi->x.polarity; }
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static inline trigger_mode_t nmi_get_trigger_mode(acpi_madt_nmi_t *nmi)
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{ return (trigger_mode_t) nmi->x.trigger_mode; }
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typedef struct __attribute__((packed))
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{
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acpi_madt_hdr_t header;
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u8_t apic_processor_id;
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union {
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u16_t flags;
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struct {
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u16_t polarity : 2;
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u16_t trigger_mode : 2;
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u16_t reserved : 12;
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} x;
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};
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u8_t lint;
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}acpi_lapic_nmi_t;
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static inline polarity_t lapic_nmi_get_polarity(acpi_lapic_nmi_t *nmi)
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{ return (polarity_t) nmi->x.polarity; }
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static inline trigger_mode_t lapic_nmi_get_trigger_mode(acpi_lapic_nmi_t *nmi)
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{ return (trigger_mode_t) nmi->x.trigger_mode; }
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typedef struct __attribute__((packed))
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{
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u32_t sig;
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u32_t len;
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u8_t rev;
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u8_t csum;
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char oem_id[ACPI_OEM_ID_SIZE];
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char oem_tid[ACPI_OEM_TABLE_ID_SIZE];
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u32_t oem_rev;
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u32_t creator_id;
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u32_t creator_rev;
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}acpi_thead_t;
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typedef struct __attribute__((packed))
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{
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acpi_thead_t header;
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u32_t local_apic_addr;
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u32_t apic_flags;
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u8_t data[0];
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} acpi_madt_t;
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typedef struct __attribute__((packed))
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{
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acpi_thead_t header;
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u32_t ptrs[0];
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}acpi_rsdt_t;
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typedef struct __attribute__((packed))
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{
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acpi_thead_t header;
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u64_t ptrs[0];
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}acpi_xsdt_t;
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typedef struct
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{
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u32_t sig[2];
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u8_t csum;
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char oemid[6];
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u8_t rev;
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u32_t rsdt_ptr;
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u32_t rsdt_len;
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u64_t xsdt_ptr;
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u8_t xcsum;
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u8_t _rsvd_33[3];
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}acpi_rsdp_t;
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typedef struct __attribute__((packed))
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{
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u8_t SpaceId; /* Address space where struct or register exists */
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u8_t BitWidth; /* Size in bits of given register */
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u8_t BitOffset; /* Bit offset within the register */
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u8_t AccessWidth; /* Minimum Access size (ACPI 3.0) */
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u64_t Address; /* 64-bit address of struct or register */
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} acpi_address_t;
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typedef struct __attribute__((packed))
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{
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acpi_thead_t Header; /* Common ACPI table header */
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u32_t Facs; /* 32-bit physical address of FACS */
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u32_t Dsdt; /* 32-bit physical address of DSDT */
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u8_t Model; /* System Interrupt Model (ACPI 1.0) - not used in ACPI 2.0+ */
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u8_t PreferredProfile; /* Conveys preferred power management profile to OSPM. */
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u16_t SciInterrupt; /* System vector of SCI interrupt */
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u32_t SmiCommand; /* 32-bit Port address of SMI command port */
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u8_t AcpiEnable; /* Value to write to smi_cmd to enable ACPI */
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u8_t AcpiDisable; /* Value to write to smi_cmd to disable ACPI */
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u8_t S4BiosRequest; /* Value to write to SMI CMD to enter S4BIOS state */
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u8_t PstateControl; /* Processor performance state control*/
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u32_t Pm1aEventBlock; /* 32-bit Port address of Power Mgt 1a Event Reg Blk */
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u32_t Pm1bEventBlock; /* 32-bit Port address of Power Mgt 1b Event Reg Blk */
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u32_t Pm1aControlBlock; /* 32-bit Port address of Power Mgt 1a Control Reg Blk */
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u32_t Pm1bControlBlock; /* 32-bit Port address of Power Mgt 1b Control Reg Blk */
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u32_t Pm2ControlBlock; /* 32-bit Port address of Power Mgt 2 Control Reg Blk */
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u32_t PmTimerBlock; /* 32-bit Port address of Power Mgt Timer Ctrl Reg Blk */
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u32_t Gpe0Block; /* 32-bit Port address of General Purpose Event 0 Reg Blk */
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u32_t Gpe1Block; /* 32-bit Port address of General Purpose Event 1 Reg Blk */
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u8_t Pm1EventLength; /* Byte Length of ports at Pm1xEventBlock */
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u8_t Pm1ControlLength; /* Byte Length of ports at Pm1xControlBlock */
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u8_t Pm2ControlLength; /* Byte Length of ports at Pm2ControlBlock */
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u8_t PmTimerLength; /* Byte Length of ports at PmTimerBlock */
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u8_t Gpe0BlockLength; /* Byte Length of ports at Gpe0Block */
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u8_t Gpe1BlockLength; /* Byte Length of ports at Gpe1Block */
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u8_t Gpe1Base; /* Offset in GPE number space where GPE1 events start */
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u8_t CstControl; /* Support for the _CST object and C States change notification */
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u16_t C2Latency; /* Worst case HW latency to enter/exit C2 state */
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u16_t C3Latency; /* Worst case HW latency to enter/exit C3 state */
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u16_t FlushSize; /* Processor's memory cache line width, in bytes */
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u16_t FlushStride; /* Number of flush strides that need to be read */
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u8_t DutyOffset; /* Processor duty cycle index in processor's P_CNT reg*/
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u8_t DutyWidth; /* Processor duty cycle value bit width in P_CNT register.*/
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u8_t DayAlarm; /* Index to day-of-month alarm in RTC CMOS RAM */
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u8_t MonthAlarm; /* Index to month-of-year alarm in RTC CMOS RAM */
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u8_t Century; /* Index to century in RTC CMOS RAM */
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u16_t BootFlags; /* IA-PC Boot Architecture Flags. See Table 5-10 for description */
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u8_t Reserved; /* Reserved, must be zero */
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u32_t Flags; /* Miscellaneous flag bits (see below for individual flags) */
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acpi_address_t ResetRegister; /* 64-bit address of the Reset register */
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u8_t ResetValue; /* Value to write to the ResetRegister port to reset the system */
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u8_t Reserved4[3]; /* Reserved, must be zero */
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u64_t XFacs; /* 64-bit physical address of FACS */
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u64_t XDsdt; /* 64-bit physical address of DSDT */
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acpi_address_t XPm1aEventBlock; /* 64-bit Extended Power Mgt 1a Event Reg Blk address */
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acpi_address_t XPm1bEventBlock; /* 64-bit Extended Power Mgt 1b Event Reg Blk address */
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acpi_address_t XPm1aControlBlock; /* 64-bit Extended Power Mgt 1a Control Reg Blk address */
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acpi_address_t XPm1bControlBlock; /* 64-bit Extended Power Mgt 1b Control Reg Blk address */
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acpi_address_t XPm2ControlBlock; /* 64-bit Extended Power Mgt 2 Control Reg Blk address */
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acpi_address_t XPmTimerBlock; /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */
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acpi_address_t XGpe0Block; /* 64-bit Extended General Purpose Event 0 Reg Blk address */
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acpi_address_t XGpe1Block; /* 64-bit Extended General Purpose Event 1 Reg Blk address */
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} acpi_fadt_t;
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#define OS_BASE 0x80000000
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#define ACPI_HI_RSDP_WINDOW_START (OS_BASE+0x000E0000)
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#define ACPI_HI_RSDP_WINDOW_END (OS_BASE+0x00100000)
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#define ACPI_RSDP_CHECKSUM_LENGTH 20
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#define ACPI_RSDP_XCHECKSUM_LENGTH 36
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#define ACPI_MADT_SIGN 0x43495041
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#define addr_offset(addr, off) \
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(addr_t)((addr_t)(addr) + (addr_t)(off))
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#define ACPI_ADDR(x) \
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(addr_t)((addr_t)(x)+OS_BASE)
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#define acpi_remap(x) (x)
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