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https://github.com/KolibriOS/kolibrios.git
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737 lines
25 KiB
C++
737 lines
25 KiB
C++
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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;***** Created: 2005-01-11 10:30 ******* Source: ATmega161.xml ***********
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;*************************************************************************
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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;*
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;* Number : AVR000
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;* File Name : "m161def.inc"
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;* Title : Register/Bit Definitions for the ATmega161
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;* Date : 2005-01-11
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;* Version : 2.14
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;* Support E-mail : avr@atmel.com
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;* Target MCU : ATmega161
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;*
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;* DESCRIPTION
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;* When including this file in the assembly program file, all I/O register
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;* names and I/O register bit names appearing in the data book can be used.
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;* In addition, the six registers forming the three data pointers X, Y and
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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;* SRAM is also defined
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;*
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;* The Register names are represented by their hexadecimal address.
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;*
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;* The Register Bit names are represented by their bit number (0-7).
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;*
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;* Please observe the difference in using the bit names with instructions
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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;* (skip if bit in register set/cleared). The following example illustrates
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;* this:
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;*
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;* in r16,PORTB ;read PORTB latch
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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;* out PORTB,r16 ;output to PORTB
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;*
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;* in r16,TIFR ;read the Timer Interrupt Flag Register
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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;* rjmp TOV0_is_set ;jump if set
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;* ... ;otherwise do something else
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;*************************************************************************
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#ifndef _M161DEF_INC_
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#define _M161DEF_INC_
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#pragma partinc 0
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; ***** SPECIFY DEVICE ***************************************************
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.device ATmega161
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#pragma AVRPART ADMIN PART_NAME ATmega161
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.equ SIGNATURE_000 = 0x1e
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.equ SIGNATURE_001 = 0x94
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.equ SIGNATURE_002 = 0x01
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#pragma AVRPART CORE CORE_VERSION V2E
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; ***** I/O REGISTER DEFINITIONS *****************************************
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; NOTE:
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; Definitions marked "MEMORY MAPPED"are extended I/O ports
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; and cannot be used with IN/OUT instructions
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.equ SREG = 0x3f
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.equ SPH = 0x3e
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.equ SPL = 0x3d
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.equ GIMSK = 0x3b
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.equ GIFR = 0x3a
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.equ TIMSK = 0x39
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.equ TIFR = 0x38
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.equ SPMCR = 0x37
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.equ EMCUCR = 0x36
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.equ MCUCR = 0x35
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.equ MCUSR = 0x34
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.equ TCCR0 = 0x33
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.equ TCNT0 = 0x32
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.equ OCR0 = 0x31
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.equ SFIOR = 0x30
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.equ TCCR1A = 0x2f
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.equ TCCR1B = 0x2e
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.equ TCNT1H = 0x2d
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.equ TCNT1L = 0x2c
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.equ OCR1AH = 0x2b
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.equ OCR1AL = 0x2a
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.equ OCR1BH = 0x29
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.equ OCR1BL = 0x28
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.equ TCCR2 = 0x27
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.equ ASSR = 0x26
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.equ ICR1H = 0x25
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.equ ICR1L = 0x24
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.equ TCNT2 = 0x23
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.equ OCR2 = 0x22
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.equ WDTCR = 0x21
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.equ UBRRHI = 0x20
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.equ EEARH = 0x1f
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.equ EEARL = 0x1e
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.equ EEDR = 0x1d
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.equ EECR = 0x1c
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.equ PORTA = 0x1b
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.equ DDRA = 0x1a
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.equ PINA = 0x19
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.equ PORTB = 0x18
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.equ DDRB = 0x17
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.equ PINB = 0x16
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.equ PORTC = 0x15
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.equ DDRC = 0x14
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.equ PINC = 0x13
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.equ PORTD = 0x12
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.equ DDRD = 0x11
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.equ PIND = 0x10
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.equ SPDR = 0x0f
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.equ SPSR = 0x0e
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.equ SPCR = 0x0d
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.equ UDR0 = 0x0c
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.equ UCSR0A = 0x0b
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.equ UCSR0B = 0x0a
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.equ UBRR0 = 0x09
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.equ ACSR = 0x08
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.equ PORTE = 0x07
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.equ DDRE = 0x06
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.equ PINE = 0x05
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.equ UDR1 = 0x03
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.equ UCSR1A = 0x02
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.equ UCSR1B = 0x01
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.equ UBRR1 = 0x00
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; ***** BIT DEFINITIONS **************************************************
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; ***** ANALOG_COMPARATOR ************
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; ACSR - Analog Comparator Control And Status Register
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.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
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.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
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.equ ACIC = 2 ; Analog Comparator Input Capture Enable
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.equ ACIE = 3 ; Analog Comparator Interrupt Enable
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.equ ACI = 4 ; Analog Comparator Interrupt Flag
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.equ ACO = 5 ; Analog Compare Output
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.equ AINBG = 6 ; Analog Comparator Bandgap Select
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.equ ACD = 7 ; Analog Comparator Disable
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; ***** SPI **************************
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; SPDR - SPI Data Register
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.equ SPDR0 = 0 ; SPI Data Register bit 0
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.equ SPDR1 = 1 ; SPI Data Register bit 1
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.equ SPDR2 = 2 ; SPI Data Register bit 2
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.equ SPDR3 = 3 ; SPI Data Register bit 3
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.equ SPDR4 = 4 ; SPI Data Register bit 4
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.equ SPDR5 = 5 ; SPI Data Register bit 5
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.equ SPDR6 = 6 ; SPI Data Register bit 6
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.equ SPDR7 = 7 ; SPI Data Register bit 7
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; SPSR - SPI Status Register
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.equ SPI2X = 0 ; Double SPI Speed Bit
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.equ WCOL = 6 ; Write Collision Flag
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.equ SPIF = 7 ; SPI Interrupt Flag
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; SPCR - SPI Control Register
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.equ SPR0 = 0 ; SPI Clock Rate Select 0
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.equ SPR1 = 1 ; SPI Clock Rate Select 1
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.equ CPHA = 2 ; Clock Phase
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.equ CPOL = 3 ; Clock polarity
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.equ MSTR = 4 ; Master/Slave Select
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.equ DORD = 5 ; Data Order
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.equ SPE = 6 ; SPI Enable
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.equ SPIE = 7 ; SPI Interrupt Enable
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; ***** USART0 ***********************
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; UDR0 - USART I/O Data Register
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.equ UDR00 = 0 ; USART I/O Data Register bit 0
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.equ UDR01 = 1 ; USART I/O Data Register bit 1
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.equ UDR02 = 2 ; USART I/O Data Register bit 2
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.equ UDR03 = 3 ; USART I/O Data Register bit 3
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.equ UDR04 = 4 ; USART I/O Data Register bit 4
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.equ UDR05 = 5 ; USART I/O Data Register bit 5
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.equ UDR06 = 6 ; USART I/O Data Register bit 6
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.equ UDR07 = 7 ; USART I/O Data Register bit 7
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; UCSR0A - USART Control and Status Register A
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.equ MPCM0 = 0 ; Multi-processor Communication Mode
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.equ U2X0 = 1 ; Double the USART transmission speed
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.equ OR0 = 3 ; Data overRun
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.equ FE0 = 4 ; Framing Error
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.equ UDRE0 = 5 ; USART Data Register Empty
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.equ TXC0 = 6 ; USART Transmitt Complete
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.equ RXC0 = 7 ; USART Receive Complete
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; UCSR0B - USART Control and Status Register B
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.equ TXB80 = 0 ; Transmit Data Bit 8
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.equ RXB80 = 1 ; Receive Data Bit 8
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.equ CHR90 = 2 ; 9-Bit Character
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.equ TXEN0 = 3 ; Transmitter Enable
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.equ RXEN0 = 4 ; Receiver Enable
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.equ UDR0IE0 = 5 ; USART Data register Empty Interrupt Enable
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.equ TXCIE0 = 6 ; TX Complete Interrupt Enable
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.equ RXCIE0 = 7 ; RX Complete Interrupt Enable
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; UBRR0 - USART Baud Rate Register Byte
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.equ UBRR00 = 0 ; USART Baud Rate Register bit 0
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.equ UBRR01 = 1 ; USART Baud Rate Register bit 1
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.equ UBRR02 = 2 ; USART Baud Rate Register bit 2
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.equ UBRR03 = 3 ; USART Baud Rate Register bit 3
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.equ UBRR04 = 4 ; USART Baud Rate Register bit 4
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.equ UBRR05 = 5 ; USART Baud Rate Register bit 5
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.equ UBRR06 = 6 ; USART Baud Rate Register bit 6
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.equ UBRR07 = 7 ; USART Baud Rate Register bit 7
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; UBRRHI - High Byte Baud Rate Register
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.equ UBRRHI00 = 0 ; High Byte Baud Rate Register Port 0 Bit 0
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.equ UBRRHI01 = 1 ; High Byte Baud Rate Register Port 0 Bit 1
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.equ UBRRHI02 = 2 ; High Byte Baud Rate Register Port 0 Bit 2
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.equ UBRRHI03 = 3 ; High Byte Baud Rate Register Port 0 Bit 3
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; ***** USART1 ***********************
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; UDR1 - USART I/O Data Register
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.equ UDR10 = 0 ; USART I/O Data Register bit 0
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.equ UDR11 = 1 ; USART I/O Data Register bit 1
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.equ UDR12 = 2 ; USART I/O Data Register bit 2
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.equ UDR13 = 3 ; USART I/O Data Register bit 3
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.equ UDR14 = 4 ; USART I/O Data Register bit 4
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.equ UDR15 = 5 ; USART I/O Data Register bit 5
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.equ UDR16 = 6 ; USART I/O Data Register bit 6
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.equ UDR17 = 7 ; USART I/O Data Register bit 7
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; UCSR1A - USART Control and Status Register A
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.equ MPCM1 = 0 ; Multi-processor Communication Mode
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.equ U2X1 = 1 ; Double the USART transmission speed
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.equ OR1 = 3 ; Data overRun
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.equ FE1 = 4 ; Framing Error
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.equ UDRE1 = 5 ; USART Data Register Empty
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.equ TXC1 = 6 ; USART Transmitt Complete
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.equ RXC1 = 7 ; USART Receive Complete
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; UCSR1B - USART Control and Status Register B
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.equ TXB81 = 0 ; Transmit Data Bit 8
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.equ RXB81 = 1 ; Receive Data Bit 8
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.equ CHR91 = 2 ; 9-Bit Character
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.equ TXEN1 = 3 ; Transmitter Enable
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.equ RXEN1 = 4 ; Receiver Enable
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.equ UDR1IE1 = 5 ; USART Data register Empty Interrupt Enable
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.equ TXCIE1 = 6 ; TX Complete Interrupt Enable
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.equ RXCIE1 = 7 ; RX Complete Interrupt Enable
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; UBRR1 - USART Baud Rate Register Byte
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.equ UBRR10 = 0 ; USART Baud Rate Register bit 0
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.equ UBRR11 = 1 ; USART Baud Rate Register bit 1
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.equ UBRR12 = 2 ; USART Baud Rate Register bit 2
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.equ UBRR13 = 3 ; USART Baud Rate Register bit 3
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.equ UBRR14 = 4 ; USART Baud Rate Register bit 4
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.equ UBRR15 = 5 ; USART Baud Rate Register bit 5
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.equ UBRR16 = 6 ; USART Baud Rate Register bit 6
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.equ UBRR17 = 7 ; USART Baud Rate Register bit 7
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; UBRRHI - high Byte Baud Rate Register
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.equ UBRRHI10 = 4 ; High Byte Baud Rate Register Port 0 Bit 0
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.equ UBRRHI11 = 5 ; High Byte Baud Rate Register Port 0 Bit 1
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.equ UBRRHI12 = 6 ; High Byte Baud Rate Register Port 0 Bit 2
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.equ UBRRHI13 = 7 ; High Byte Baud Rate Register Port 0 Bit 3
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; ***** PORTA ************************
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; PORTA - Port A Data Register
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.equ PORTA0 = 0 ; Port A Data Register bit 0
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.equ PA0 = 0 ; For compatibility
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.equ PORTA1 = 1 ; Port A Data Register bit 1
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.equ PA1 = 1 ; For compatibility
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.equ PORTA2 = 2 ; Port A Data Register bit 2
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.equ PA2 = 2 ; For compatibility
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.equ PORTA3 = 3 ; Port A Data Register bit 3
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.equ PA3 = 3 ; For compatibility
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.equ PORTA4 = 4 ; Port A Data Register bit 4
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.equ PA4 = 4 ; For compatibility
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.equ PORTA5 = 5 ; Port A Data Register bit 5
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.equ PA5 = 5 ; For compatibility
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.equ PORTA6 = 6 ; Port A Data Register bit 6
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.equ PA6 = 6 ; For compatibility
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.equ PORTA7 = 7 ; Port A Data Register bit 7
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.equ PA7 = 7 ; For compatibility
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; DDRA - Port A Data Direction Register
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.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
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.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
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.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
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.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
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.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
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.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
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.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
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.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
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; PINA - Port A Input Pins
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.equ PINA0 = 0 ; Input Pins, Port A bit 0
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.equ PINA1 = 1 ; Input Pins, Port A bit 1
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.equ PINA2 = 2 ; Input Pins, Port A bit 2
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.equ PINA3 = 3 ; Input Pins, Port A bit 3
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.equ PINA4 = 4 ; Input Pins, Port A bit 4
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.equ PINA5 = 5 ; Input Pins, Port A bit 5
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.equ PINA6 = 6 ; Input Pins, Port A bit 6
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.equ PINA7 = 7 ; Input Pins, Port A bit 7
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; ***** PORTB ************************
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; PORTB - Port B Data Register
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.equ PORTB0 = 0 ; Port B Data Register bit 0
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.equ PB0 = 0 ; For compatibility
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.equ PORTB1 = 1 ; Port B Data Register bit 1
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.equ PB1 = 1 ; For compatibility
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.equ PORTB2 = 2 ; Port B Data Register bit 2
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.equ PB2 = 2 ; For compatibility
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.equ PORTB3 = 3 ; Port B Data Register bit 3
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.equ PB3 = 3 ; For compatibility
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.equ PORTB4 = 4 ; Port B Data Register bit 4
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.equ PB4 = 4 ; For compatibility
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.equ PORTB5 = 5 ; Port B Data Register bit 5
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.equ PB5 = 5 ; For compatibility
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.equ PORTB6 = 6 ; Port B Data Register bit 6
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.equ PB6 = 6 ; For compatibility
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.equ PORTB7 = 7 ; Port B Data Register bit 7
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.equ PB7 = 7 ; For compatibility
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; DDRB - Port B Data Direction Register
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.equ DDB0 = 0 ; Port B Data Direction Register bit 0
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.equ DDB1 = 1 ; Port B Data Direction Register bit 1
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.equ DDB2 = 2 ; Port B Data Direction Register bit 2
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.equ DDB3 = 3 ; Port B Data Direction Register bit 3
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.equ DDB4 = 4 ; Port B Data Direction Register bit 4
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.equ DDB5 = 5 ; Port B Data Direction Register bit 5
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.equ DDB6 = 6 ; Port B Data Direction Register bit 6
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.equ DDB7 = 7 ; Port B Data Direction Register bit 7
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; PINB - Port B Input Pins
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.equ PINB0 = 0 ; Port B Input Pins bit 0
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.equ PINB1 = 1 ; Port B Input Pins bit 1
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.equ PINB2 = 2 ; Port B Input Pins bit 2
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.equ PINB3 = 3 ; Port B Input Pins bit 3
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.equ PINB4 = 4 ; Port B Input Pins bit 4
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.equ PINB5 = 5 ; Port B Input Pins bit 5
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.equ PINB6 = 6 ; Port B Input Pins bit 6
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.equ PINB7 = 7 ; Port B Input Pins bit 7
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; ***** PORTC ************************
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; PORTC - Port C Data Register
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.equ PORTC0 = 0 ; Port C Data Register bit 0
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.equ PC0 = 0 ; For compatibility
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.equ PORTC1 = 1 ; Port C Data Register bit 1
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.equ PC1 = 1 ; For compatibility
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.equ PORTC2 = 2 ; Port C Data Register bit 2
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.equ PC2 = 2 ; For compatibility
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.equ PORTC3 = 3 ; Port C Data Register bit 3
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.equ PC3 = 3 ; For compatibility
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.equ PORTC4 = 4 ; Port C Data Register bit 4
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.equ PC4 = 4 ; For compatibility
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.equ PORTC5 = 5 ; Port C Data Register bit 5
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.equ PC5 = 5 ; For compatibility
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.equ PORTC6 = 6 ; Port C Data Register bit 6
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.equ PC6 = 6 ; For compatibility
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.equ PORTC7 = 7 ; Port C Data Register bit 7
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.equ PC7 = 7 ; For compatibility
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; DDRC - Port C Data Direction Register
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.equ DDC0 = 0 ; Port C Data Direction Register bit 0
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.equ DDC1 = 1 ; Port C Data Direction Register bit 1
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.equ DDC2 = 2 ; Port C Data Direction Register bit 2
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.equ DDC3 = 3 ; Port C Data Direction Register bit 3
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.equ DDC4 = 4 ; Port C Data Direction Register bit 4
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.equ DDC5 = 5 ; Port C Data Direction Register bit 5
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.equ DDC6 = 6 ; Port C Data Direction Register bit 6
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.equ DDC7 = 7 ; Port C Data Direction Register bit 7
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; PINC - Port C Input Pins
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.equ PINC0 = 0 ; Port C Input Pins bit 0
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.equ PINC1 = 1 ; Port C Input Pins bit 1
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.equ PINC2 = 2 ; Port C Input Pins bit 2
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.equ PINC3 = 3 ; Port C Input Pins bit 3
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.equ PINC4 = 4 ; Port C Input Pins bit 4
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.equ PINC5 = 5 ; Port C Input Pins bit 5
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.equ PINC6 = 6 ; Port C Input Pins bit 6
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.equ PINC7 = 7 ; Port C Input Pins bit 7
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; ***** PORTD ************************
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; PORTD - Port D Data Register
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.equ PORTD0 = 0 ; Port D Data Register bit 0
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.equ PD0 = 0 ; For compatibility
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.equ PORTD1 = 1 ; Port D Data Register bit 1
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.equ PD1 = 1 ; For compatibility
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.equ PORTD2 = 2 ; Port D Data Register bit 2
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.equ PD2 = 2 ; For compatibility
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.equ PORTD3 = 3 ; Port D Data Register bit 3
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.equ PD3 = 3 ; For compatibility
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.equ PORTD4 = 4 ; Port D Data Register bit 4
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.equ PD4 = 4 ; For compatibility
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.equ PORTD5 = 5 ; Port D Data Register bit 5
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.equ PD5 = 5 ; For compatibility
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.equ PORTD6 = 6 ; Port D Data Register bit 6
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.equ PD6 = 6 ; For compatibility
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.equ PORTD7 = 7 ; Port D Data Register bit 7
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.equ PD7 = 7 ; For compatibility
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; DDRD - Port D Data Direction Register
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.equ DDD0 = 0 ; Port D Data Direction Register bit 0
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.equ DDD1 = 1 ; Port D Data Direction Register bit 1
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.equ DDD2 = 2 ; Port D Data Direction Register bit 2
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.equ DDD3 = 3 ; Port D Data Direction Register bit 3
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.equ DDD4 = 4 ; Port D Data Direction Register bit 4
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.equ DDD5 = 5 ; Port D Data Direction Register bit 5
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.equ DDD6 = 6 ; Port D Data Direction Register bit 6
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.equ DDD7 = 7 ; Port D Data Direction Register bit 7
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; PIND - Port D Input Pins
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.equ PIND0 = 0 ; Port D Input Pins bit 0
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.equ PIND1 = 1 ; Port D Input Pins bit 1
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.equ PIND2 = 2 ; Port D Input Pins bit 2
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.equ PIND3 = 3 ; Port D Input Pins bit 3
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.equ PIND4 = 4 ; Port D Input Pins bit 4
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.equ PIND5 = 5 ; Port D Input Pins bit 5
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.equ PIND6 = 6 ; Port D Input Pins bit 6
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.equ PIND7 = 7 ; Port D Input Pins bit 7
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; ***** PORTE ************************
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; PORTE - Port E Data Register
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.equ PORTE0 = 0 ;
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.equ PE0 = 0 ; For compatibility
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.equ PORTE1 = 1 ;
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.equ PE1 = 1 ; For compatibility
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.equ PORTE2 = 2 ;
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.equ PE2 = 2 ; For compatibility
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; DDRE - Port E Data Direction Register
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.equ DDE0 = 0 ;
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.equ DDE1 = 1 ;
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.equ DDE2 = 2 ;
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|
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; PINE - Port E Input Pins
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.equ PINE0 = 0 ;
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.equ PINE1 = 1 ;
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.equ PINE2 = 2 ;
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|
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|
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; ***** EEPROM ***********************
|
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; EEDR - EEPROM Data Register
|
|
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
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.equ EEDR1 = 1 ; EEPROM Data Register bit 1
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.equ EEDR2 = 2 ; EEPROM Data Register bit 2
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.equ EEDR3 = 3 ; EEPROM Data Register bit 3
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.equ EEDR4 = 4 ; EEPROM Data Register bit 4
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.equ EEDR5 = 5 ; EEPROM Data Register bit 5
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.equ EEDR6 = 6 ; EEPROM Data Register bit 6
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.equ EEDR7 = 7 ; EEPROM Data Register bit 7
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|
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; EECR - EEPROM Control Register
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.equ EERE = 0 ; EEPROM Read Enable
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.equ EEWE = 1 ; EEPROM Write Enable
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.equ EEMWE = 2 ; EEPROM Master Write Enable
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.equ EEWEE = EEMWE ; For compatibility
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.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
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|
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; ***** EXTERNAL_INTERRUPT ***********
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; GIMSK - General Interrupt Mask Register
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.equ INT2 = 5 ; External Interrupt Request 2 Enable
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.equ INT0 = 6 ; External Interrupt Request 0 Enable
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.equ INT1 = 7 ; External Interrupt Request 1 Enable
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; GIFR - General Interrupt Flag Register
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.equ INTF2 = 5 ; External Interrupt Flag 2
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.equ INTF0 = 6 ; External Interrupt Flag 0
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.equ INTF1 = 7 ; External Interrupt Flag 1
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|
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; ***** CPU **************************
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; SREG - Status Register
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.equ SREG_C = 0 ; Carry Flag
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.equ SREG_Z = 1 ; Zero Flag
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.equ SREG_N = 2 ; Negative Flag
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.equ SREG_V = 3 ; Two's Complement Overflow Flag
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.equ SREG_S = 4 ; Sign Bit
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.equ SREG_H = 5 ; Half Carry Flag
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.equ SREG_T = 6 ; Bit Copy Storage
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.equ SREG_I = 7 ; Global Interrupt Enable
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; MCUCR - MCU Control Register
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.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
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.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
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.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 1
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.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
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.equ SM1 = 4 ; Sleep Mode Select
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.equ SE = 5 ; Sleep Enable
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.equ SRW10 = 6 ; External SRAM Wait State Select
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.equ SRE = 7 ; External SRAM Enable
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|
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; MCUSR - MCU Status Register
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.equ PORF = 0 ; Power-on reset flag
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|
.equ EXTRF = 1 ; External Reset Flag
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.equ BORF = 2 ; Brown-out Reset Flag
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.equ WDRF = 3 ; Watchdog Reset Flag
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|
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; EMCUCR - Extended MCU Control Register
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.equ ISC2 = 0 ; Interrupt Sense Control 2
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.equ SRW11 = 1 ; Wait State Select Bit 1 for Upper Sector
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.equ SRW00 = 2 ; Wait State Select Bit 0 for Lower Sector
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.equ SRW01 = 3 ; Wait State Select Bit 1 for Lower Sector
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.equ SRL0 = 4 ; Wait State Sector Limit Bit 0
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|
.equ SRL1 = 5 ; Wait State Sector Limit Bit 1
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.equ SRL2 = 6 ; Wait State Sector Limit Bit 2
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.equ SM0 = 7 ; Sleep mode Select Bit 0
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|
|
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; SPMCR - Store Program Memory Control Register
|
|
.equ SPMEN = 0 ; Store Program Memory Enable
|
|
.equ PGERS = 1 ; Page Erase
|
|
.equ PGWRT = 2 ; Page Write
|
|
.equ BLBSET = 3 ; Boot Lock Bit Set
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|
|
|
|
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; ***** TIMER_COUNTER_0 **************
|
|
; TCCR0 - Timer/Counter Control Register
|
|
.equ CS00 = 0 ; Clock Select 1
|
|
.equ CS01 = 1 ; Clock Select 1
|
|
.equ CS02 = 2 ; Clock Select 2
|
|
.equ WGM01 = 3 ; Waveform Generation Mode 1
|
|
.equ COM00 = 4 ; Compare match Output Mode 0
|
|
.equ COM01 = 5 ; Compare Match Output Mode 1
|
|
.equ WGM00 = 6 ; Waveform Generation Mode 0
|
|
.equ FOC0 = 7 ; Force Output Compare
|
|
|
|
; TCNT0 - Timer/Counter Register
|
|
.equ TCNT0_0 = 0 ;
|
|
.equ TCNT0_1 = 1 ;
|
|
.equ TCNT0_2 = 2 ;
|
|
.equ TCNT0_3 = 3 ;
|
|
.equ TCNT0_4 = 4 ;
|
|
.equ TCNT0_5 = 5 ;
|
|
.equ TCNT0_6 = 6 ;
|
|
.equ TCNT0_7 = 7 ;
|
|
|
|
; OCR0 - Output Compare Register
|
|
.equ OCR0_0 = 0 ;
|
|
.equ OCR0_1 = 1 ;
|
|
.equ OCR0_2 = 2 ;
|
|
.equ OCR0_3 = 3 ;
|
|
.equ OCR0_4 = 4 ;
|
|
.equ OCR0_5 = 5 ;
|
|
.equ OCR0_6 = 6 ;
|
|
.equ OCR0_7 = 7 ;
|
|
|
|
; TIMSK - Timer/Counter Interrupt Mask Register
|
|
.equ OCIE0 = 0 ; Timer/Counter0 Output Compare Match Interrupt register
|
|
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
|
|
|
|
; TIFR - Timer/Counter Interrupt Flag register
|
|
.equ OCF0 = 0 ; Output Compare Flag 0
|
|
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
|
|
|
|
; SFIOR - Special Function IO Register
|
|
.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
|
|
|
|
|
|
; ***** TIMER_COUNTER_2 **************
|
|
; TIMSK - Timer/Counter Interrupt Mask register
|
|
.equ OCIE2 = 2 ; Timer/Counter2 Output Compare Match Interrupt Enable
|
|
.equ TOIE2 = 4 ; Timer/Counter2 Overflow Interrupt Enable
|
|
|
|
; TIFR - Timer/Counter Interrupt Flag Register
|
|
.equ OCF2 = 2 ; Output Compare Flag 2
|
|
.equ TOV2 = 4 ; Timer/Counter2 Overflow Flag
|
|
|
|
; TCCR2 - Timer/Counter2 Control Register
|
|
.equ CS20 = 0 ; Clock Select bit 0
|
|
.equ CS21 = 1 ; Clock Select bit 1
|
|
.equ CS22 = 2 ; Clock Select bit 2
|
|
.equ CTC2 = 3 ; Clear Timer/Counter2 on Compare Match
|
|
.equ COM20 = 4 ; Compare Output Mode bit 0
|
|
.equ COM21 = 5 ; Compare Output Mode bit 1
|
|
.equ PWM2 = 6 ; Pulse Width Modulator Enable
|
|
.equ FOC2 = 7 ; Force Output Compare
|
|
|
|
; TCNT2 - Timer/Counter2
|
|
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
|
|
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
|
|
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
|
|
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
|
|
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
|
|
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
|
|
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
|
|
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
|
|
|
|
; OCR2 - Timer/Counter2 Output Compare Register
|
|
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
|
|
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
|
|
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
|
|
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
|
|
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
|
|
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
|
|
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
|
|
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
|
|
|
|
; ASSR - Asynchronous Status Register
|
|
.equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy
|
|
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy
|
|
.equ TCN2UB = 2 ; Timer/Counter2 Update Busy
|
|
.equ AS2 = 3 ; Asynchronous Timer/counter2
|
|
|
|
; SFIOR - Specil Function IO Register
|
|
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2
|
|
|
|
|
|
; ***** TIMER_COUNTER_1 **************
|
|
; TIMSK - Timer/Counter Interrupt Mask Register
|
|
.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable
|
|
.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable
|
|
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable
|
|
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable
|
|
|
|
; TIFR - Timer/Counter Interrupt Flag register
|
|
.equ ICF1 = 3 ; Input Capture Flag 1
|
|
.equ OCF1B = 5 ; Output Compare Flag 1B
|
|
.equ OCF1A = 6 ; Output Compare Flag 1A
|
|
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag
|
|
|
|
; TCCR1A - Timer/Counter1 Control Register A
|
|
.equ WGM10 = 0 ; Waveform Generation Mode
|
|
.equ WGM11 = 1 ; Waveform Generation Mode
|
|
.equ FOC1B = 2 ; Force Output Compare 1B
|
|
.equ FOC1A = 3 ; Force Output Compare 1A
|
|
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
|
|
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
|
|
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
|
|
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
|
|
|
|
; TCCR1B - Timer/Counter1 Control Register B
|
|
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1
|
|
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1
|
|
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1
|
|
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match
|
|
.equ ICES1 = 6 ; Input Capture 1 Edge Select
|
|
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
|
|
|
|
|
|
; ***** WATCHDOG *********************
|
|
; WDTCR - Watchdog Timer Control Register
|
|
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
|
|
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
|
|
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
|
|
.equ WDE = 3 ; Watch Dog Enable
|
|
.equ WDTOE = 4 ; RW
|
|
.equ WDDE = WDTOE ; For compatibility
|
|
|
|
|
|
|
|
; ***** LOCKSBITS ********************************************************
|
|
.equ LB1 = 0 ; Lock bit
|
|
.equ LB2 = 1 ; Lock bit
|
|
.equ BLB01 = 2 ; Boot Lock bit
|
|
.equ BLB02 = 3 ; Boot Lock bit
|
|
.equ BLB11 = 4 ; Boot lock bit
|
|
.equ BLB12 = 5 ; Boot lock bit
|
|
|
|
|
|
; ***** FUSES ************************************************************
|
|
; LOW fuse bits
|
|
.equ CKSEL0 = 0 ; Select Clock Source
|
|
.equ CKSEL1 = 1 ; Select Clock Source
|
|
.equ CKSEL2 = 2 ; Select Clock Source
|
|
.equ SUT = 3 ; Start-up time
|
|
.equ SPIEN = 4 ; Serial program downloading (SPI) enabled
|
|
.equ BOOTRST = 5 ; Boot Reset Vector Enabled
|
|
|
|
; HIGH fuse bits
|
|
|
|
; EXTENDED fuse bits
|
|
|
|
|
|
|
|
; ***** CPU REGISTER DEFINITIONS *****************************************
|
|
.def XH = r27
|
|
.def XL = r26
|
|
.def YH = r29
|
|
.def YL = r28
|
|
.def ZH = r31
|
|
.def ZL = r30
|
|
|
|
|
|
|
|
; ***** DATA MEMORY DECLARATIONS *****************************************
|
|
.equ FLASHEND = 0x1fff ; Note: Word address
|
|
.equ IOEND = 0x003f
|
|
.equ SRAM_START = 0x0060
|
|
.equ SRAM_SIZE = 1024
|
|
.equ RAMEND = 0x045f
|
|
.equ XRAMEND = 0xfbff
|
|
.equ E2END = 0x01ff
|
|
.equ EEPROMEND = 0x01ff
|
|
.equ EEADRBITS = 9
|
|
#pragma AVRPART MEMORY PROG_FLASH 16384
|
|
#pragma AVRPART MEMORY EEPROM 512
|
|
#pragma AVRPART MEMORY INT_SRAM SIZE 1024
|
|
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
|
|
|
|
|
|
|
|
; ***** BOOTLOADER DECLARATIONS ******************************************
|
|
.equ NRWW_START_ADDR = 0x0
|
|
.equ NRWW_STOP_ADDR = 0x1fff
|
|
.equ PAGESIZE = 64
|
|
.equ FIRSTBOOTSTART = 0x1e00
|
|
|
|
|
|
|
|
; ***** INTERRUPT VECTORS ************************************************
|
|
.equ INT0addr = 0x0002 ; External Interrupt 0
|
|
.equ INT1addr = 0x0004 ; External Interrupt 1
|
|
.equ INT2addr = 0x0006 ; External Interrupt 2
|
|
.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match
|
|
.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow
|
|
.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event
|
|
.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A
|
|
.equ OC1Baddr = 0x0010 ; Timer/Counter1 Compare Match B
|
|
.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow
|
|
.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match
|
|
.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow
|
|
.equ SPIaddr = 0x0018 ; Serial Transfer Complete
|
|
.equ URXC0addr = 0x001a ; UART0, Rx Complete
|
|
.equ URXC1addr = 0x001c ; UART1, Rx Complete
|
|
.equ UDRE0addr = 0x001e ; UART0 Data Register Empty
|
|
.equ UDRE1addr = 0x0020 ; UART1 Data Register Empty
|
|
.equ UTXC0addr = 0x0022 ; UART0, Tx Complete
|
|
.equ UTXC1addr = 0x0024 ; UART1, Tx Complete
|
|
.equ ERDYaddr = 0x0026 ; EEPROM Ready
|
|
.equ ACIaddr = 0x0028 ; Analog Comparator
|
|
|
|
.equ INT_VECTORS_SIZE = 42 ; size in words
|
|
|
|
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
|
|
|
|
#endif /* _M161DEF_INC_ */
|
|
|
|
; ***** END OF FILE ******************************************************
|