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239 lines
8.5 KiB
C
239 lines
8.5 KiB
C
/* alpha.h -- Header file for Alpha opcode table
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Copyright (C) 1996-2015 Free Software Foundation, Inc.
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Contributed by Richard Henderson <rth@tamu.edu>,
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patterned after the PPC opcode table written by Ian Lance Taylor.
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version 3,
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or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING3. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#ifndef OPCODE_ALPHA_H
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#define OPCODE_ALPHA_H
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/* The opcode table is an array of struct alpha_opcode. */
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struct alpha_opcode
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{
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/* The opcode name. */
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const char *name;
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/* The opcode itself. Those bits which will be filled in with
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operands are zeroes. */
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unsigned opcode;
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/* The opcode mask. This is used by the disassembler. This is a
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mask containing ones indicating those bits which must match the
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opcode field, and zeroes indicating those bits which need not
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match (and are presumably filled in by operands). */
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unsigned mask;
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/* One bit flags for the opcode. These are primarily used to
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indicate specific processors and environments support the
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instructions. The defined values are listed below. */
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unsigned flags;
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/* An array of operand codes. Each code is an index into the
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operand table. They appear in the order which the operands must
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appear in assembly code, and are terminated by a zero. */
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unsigned char operands[4];
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};
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/* The table itself is sorted by major opcode number, and is otherwise
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in the order in which the disassembler should consider
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instructions. */
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extern const struct alpha_opcode alpha_opcodes[];
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extern const unsigned alpha_num_opcodes;
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/* Values defined for the flags field of a struct alpha_opcode. */
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/* CPU Availability */
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#define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */
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#define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */
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#define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */
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#define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */
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#define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */
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#define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */
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#define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */
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#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6))
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/* A macro to extract the major opcode from an instruction. */
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#define AXP_OP(i) (((i) >> 26) & 0x3F)
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/* The total number of major opcodes. */
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#define AXP_NOPS 0x40
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/* The operands table is an array of struct alpha_operand. */
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struct alpha_operand
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{
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/* The number of bits in the operand. */
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unsigned int bits : 5;
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/* How far the operand is left shifted in the instruction. */
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unsigned int shift : 5;
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/* The default relocation type for this operand. */
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signed int default_reloc : 16;
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/* One bit syntax flags. */
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unsigned int flags : 16;
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/* Insertion function. This is used by the assembler. To insert an
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operand value into an instruction, check this field.
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If it is NULL, execute
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i |= (op & ((1 << o->bits) - 1)) << o->shift;
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(i is the instruction which we are filling in, o is a pointer to
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this structure, and op is the opcode value; this assumes twos
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complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction and the operand value. It will return the new value
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of the instruction. If the ERRMSG argument is not NULL, then if
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the operand value is illegal, *ERRMSG will be set to a warning
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string (the operand will be inserted in any case). If the
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operand value is legal, *ERRMSG will be unchanged (most operands
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can accept any value). */
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unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
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/* Extraction function. This is used by the disassembler. To
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extract this operand type from an instruction, check this field.
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If it is NULL, compute
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op = ((i) >> o->shift) & ((1 << o->bits) - 1);
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if ((o->flags & AXP_OPERAND_SIGNED) != 0
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&& (op & (1 << (o->bits - 1))) != 0)
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op -= 1 << o->bits;
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(i is the instruction, o is a pointer to this structure, and op
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is the result; this assumes twos complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction value. It will return the value of the operand. If
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the INVALID argument is not NULL, *INVALID will be set to
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non-zero if this operand type can not actually be extracted from
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this operand (i.e., the instruction does not match). If the
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operand is valid, *INVALID will not be changed. */
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int (*extract) (unsigned instruction, int *invalid);
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};
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/* Elements in the table are retrieved by indexing with values from
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the operands field of the alpha_opcodes table. */
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extern const struct alpha_operand alpha_operands[];
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extern const unsigned alpha_num_operands;
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/* Values defined for the flags field of a struct alpha_operand. */
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/* Mask for selecting the type for typecheck purposes */
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#define AXP_OPERAND_TYPECHECK_MASK \
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(AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \
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AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \
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AXP_OPERAND_UNSIGNED)
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/* This operand does not actually exist in the assembler input. This
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is used to support extended mnemonics, for which two operands fields
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are identical. The assembler should call the insert function with
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any op value. The disassembler should call the extract function,
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ignore the return value, and check the value placed in the invalid
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argument. */
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#define AXP_OPERAND_FAKE 01
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/* The operand should be wrapped in parentheses rather than separated
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from the previous by a comma. This is used for the load and store
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instructions which want their operands to look like "Ra,disp(Rb)". */
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#define AXP_OPERAND_PARENS 02
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/* Used in combination with PARENS, this supresses the supression of
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the comma. This is used for "jmp Ra,(Rb),hint". */
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#define AXP_OPERAND_COMMA 04
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/* This operand names an integer register. */
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#define AXP_OPERAND_IR 010
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/* This operand names a floating point register. */
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#define AXP_OPERAND_FPR 020
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/* This operand is a relative branch displacement. The disassembler
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prints these symbolically if possible. */
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#define AXP_OPERAND_RELATIVE 040
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/* This operand takes signed values. */
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#define AXP_OPERAND_SIGNED 0100
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/* This operand takes unsigned values. This exists primarily so that
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a flags value of 0 can be treated as end-of-arguments. */
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#define AXP_OPERAND_UNSIGNED 0200
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/* Supress overflow detection on this field. This is used for hints. */
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#define AXP_OPERAND_NOOVERFLOW 0400
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/* Mask for optional argument default value. */
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#define AXP_OPERAND_OPTIONAL_MASK 07000
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/* This operand defaults to zero. This is used for jump hints. */
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#define AXP_OPERAND_DEFAULT_ZERO 01000
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/* This operand should default to the first (real) operand and is used
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in conjunction with AXP_OPERAND_OPTIONAL. This allows
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"and $0,3,$0" to be written as "and $0,3", etc. I don't like
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it, but it's what DEC does. */
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#define AXP_OPERAND_DEFAULT_FIRST 02000
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/* Similarly, this operand should default to the second (real) operand.
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This allows "negl $0" instead of "negl $0,$0". */
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#define AXP_OPERAND_DEFAULT_SECOND 04000
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/* Register common names */
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#define AXP_REG_V0 0
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#define AXP_REG_T0 1
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#define AXP_REG_T1 2
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#define AXP_REG_T2 3
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#define AXP_REG_T3 4
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#define AXP_REG_T4 5
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#define AXP_REG_T5 6
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#define AXP_REG_T6 7
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#define AXP_REG_T7 8
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#define AXP_REG_S0 9
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#define AXP_REG_S1 10
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#define AXP_REG_S2 11
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#define AXP_REG_S3 12
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#define AXP_REG_S4 13
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#define AXP_REG_S5 14
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#define AXP_REG_FP 15
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#define AXP_REG_A0 16
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#define AXP_REG_A1 17
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#define AXP_REG_A2 18
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#define AXP_REG_A3 19
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#define AXP_REG_A4 20
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#define AXP_REG_A5 21
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#define AXP_REG_T8 22
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#define AXP_REG_T9 23
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#define AXP_REG_T10 24
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#define AXP_REG_T11 25
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#define AXP_REG_RA 26
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#define AXP_REG_PV 27
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#define AXP_REG_T12 27
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#define AXP_REG_AT 28
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#define AXP_REG_GP 29
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#define AXP_REG_SP 30
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#define AXP_REG_ZERO 31
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#endif /* OPCODE_ALPHA_H */
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