mirror of
https://github.com/KolibriOS/kolibrios.git
synced 2024-12-29 09:49:41 +03:00
2d34afd1e0
git-svn-id: svn://kolibrios.org@2330 a494cfbc-eb01-0410-851d-a64ba20cac60
638 lines
17 KiB
C
638 lines
17 KiB
C
/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
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*/
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/*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "drm_crtc_helper.h"
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#include "drm_fb_helper.h"
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#include "intel_drv.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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#include <drm/intel-gtt.h>
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//#include "i915_trace.h"
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//#include "../../../platform/x86/intel_ips.h"
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#include <linux/pci.h>
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//#include <linux/vgaarb.h>
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//#include <linux/acpi.h>
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//#include <linux/pnp.h>
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//#include <linux/vga_switcheroo.h>
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#include <linux/slab.h>
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//#include <acpi/video.h>
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void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
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static inline int pci_read_config_dword(struct pci_dev *dev, int where,
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u32 *val)
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{
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*val = PciRead32(dev->busnr, dev->devfn, where);
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return 1;
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}
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static void i915_write_hws_pga(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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u32 addr;
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addr = dev_priv->status_page_dmah->busaddr;
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if (INTEL_INFO(dev)->gen >= 4)
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addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
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I915_WRITE(HWS_PGA, addr);
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}
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/**
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* Sets up the hardware status page for devices that need a physical address
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* in the register.
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*/
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static int i915_init_phys_hws(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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/* Program Hardware Status Page */
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dev_priv->status_page_dmah =
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drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
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if (!dev_priv->status_page_dmah) {
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DRM_ERROR("Can not allocate hardware status page\n");
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return -ENOMEM;
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}
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i915_write_hws_pga(dev);
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dbgprintf("Enabled hardware status page\n");
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return 0;
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}
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#define MCHBAR_I915 0x44
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#define MCHBAR_I965 0x48
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#define MCHBAR_SIZE (4*4096)
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#define DEVEN_REG 0x54
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#define DEVEN_MCHBAR_EN (1 << 28)
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/* Setup MCHBAR if possible, return true if we should disable it again */
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static void
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intel_setup_mchbar(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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u32 temp;
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bool enabled;
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dev_priv->mchbar_need_disable = false;
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if (IS_I915G(dev) || IS_I915GM(dev)) {
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pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
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enabled = !!(temp & DEVEN_MCHBAR_EN);
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} else {
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pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
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enabled = temp & 1;
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}
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/* If it's already enabled, don't have to do anything */
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if (enabled)
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return;
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dbgprintf("Epic fail\n");
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#if 0
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if (intel_alloc_mchbar_resource(dev))
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return;
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dev_priv->mchbar_need_disable = true;
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/* Space is allocated or reserved, so enable it. */
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if (IS_I915G(dev) || IS_I915GM(dev)) {
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pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
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temp | DEVEN_MCHBAR_EN);
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} else {
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pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
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pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
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}
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#endif
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}
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static int i915_load_gem_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned long prealloc_size, gtt_size, mappable_size;
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int ret;
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prealloc_size = dev_priv->mm.gtt->stolen_size;
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gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
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mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
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dbgprintf("%s prealloc: %x gtt: %x mappable: %x\n",__FUNCTION__,
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prealloc_size, gtt_size, mappable_size);
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/* Basic memrange allocator for stolen space */
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drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
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//0xC00000 >> PAGE_SHIFT
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/* Let GEM Manage all of the aperture.
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*
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* However, leave one page at the end still bound to the scratch page.
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* There are a number of places where the hardware apparently
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* prefetches past the end of the object, and we've seen multiple
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* hangs with the GPU head pointer stuck in a batchbuffer bound
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* at the last page of the aperture. One page should be enough to
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* keep any prefetching inside of the aperture.
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*/
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// i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
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// mutex_lock(&dev->struct_mutex);
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// ret = i915_gem_init_ringbuffer(dev);
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// mutex_unlock(&dev->struct_mutex);
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// if (ret)
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// return ret;
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/* Try to set up FBC with a reasonable compressed buffer size */
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// if (I915_HAS_FBC(dev) && i915_powersave) {
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// int cfb_size;
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/* Leave 1M for line length buffer & misc. */
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/* Try to get a 32M buffer... */
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// if (prealloc_size > (36*1024*1024))
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// cfb_size = 32*1024*1024;
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// else /* fall back to 7/8 of the stolen space */
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// cfb_size = prealloc_size * 7 / 8;
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// i915_setup_compression(dev, cfb_size);
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// }
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/* Allow hardware batchbuffers unless told otherwise. */
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dev_priv->allow_batchbuffer = 1;
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return 0;
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}
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static int i915_load_modeset_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret;
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ret = intel_parse_bios(dev);
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if (ret)
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DRM_INFO("failed to find VBIOS tables\n");
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// intel_register_dsm_handler();
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/* IIR "flip pending" bit means done if this bit is set */
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if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
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dev_priv->flip_pending_is_done = true;
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intel_modeset_init(dev);
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ret = i915_load_gem_init(dev);
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if (ret)
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goto cleanup_vga_switcheroo;
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#if 0
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intel_modeset_gem_init(dev);
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ret = drm_irq_install(dev);
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if (ret)
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goto cleanup_gem;
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/* Always safe in the mode setting case. */
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/* FIXME: do pre/post-mode set stuff in core KMS code */
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dev->vblank_disable_allowed = 1;
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ret = intel_fbdev_init(dev);
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if (ret)
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goto cleanup_irq;
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drm_kms_helper_poll_init(dev);
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/* We're off and running w/KMS */
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dev_priv->mm.suspended = 0;
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#endif
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return 0;
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cleanup_irq:
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// drm_irq_uninstall(dev);
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cleanup_gem:
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// mutex_lock(&dev->struct_mutex);
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// i915_gem_cleanup_ringbuffer(dev);
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// mutex_unlock(&dev->struct_mutex);
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cleanup_vga_switcheroo:
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// vga_switcheroo_unregister_client(dev->pdev);
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cleanup_vga_client:
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// vga_client_register(dev->pdev, NULL, NULL, NULL);
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out:
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return ret;
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}
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static void i915_pineview_get_mem_freq(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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u32 tmp;
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tmp = I915_READ(CLKCFG);
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switch (tmp & CLKCFG_FSB_MASK) {
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case CLKCFG_FSB_533:
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dev_priv->fsb_freq = 533; /* 133*4 */
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break;
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case CLKCFG_FSB_800:
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dev_priv->fsb_freq = 800; /* 200*4 */
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break;
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case CLKCFG_FSB_667:
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dev_priv->fsb_freq = 667; /* 167*4 */
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break;
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case CLKCFG_FSB_400:
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dev_priv->fsb_freq = 400; /* 100*4 */
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break;
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}
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switch (tmp & CLKCFG_MEM_MASK) {
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case CLKCFG_MEM_533:
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dev_priv->mem_freq = 533;
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break;
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case CLKCFG_MEM_667:
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dev_priv->mem_freq = 667;
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break;
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case CLKCFG_MEM_800:
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dev_priv->mem_freq = 800;
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break;
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}
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/* detect pineview DDR3 setting */
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tmp = I915_READ(CSHRDDR3CTL);
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dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
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}
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static void i915_ironlake_get_mem_freq(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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u16 ddrpll, csipll;
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ddrpll = I915_READ16(DDRMPLL1);
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csipll = I915_READ16(CSIPLL0);
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switch (ddrpll & 0xff) {
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case 0xc:
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dev_priv->mem_freq = 800;
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break;
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case 0x10:
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dev_priv->mem_freq = 1066;
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break;
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case 0x14:
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dev_priv->mem_freq = 1333;
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break;
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case 0x18:
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dev_priv->mem_freq = 1600;
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break;
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default:
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DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
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ddrpll & 0xff);
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dev_priv->mem_freq = 0;
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break;
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}
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dev_priv->r_t = dev_priv->mem_freq;
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switch (csipll & 0x3ff) {
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case 0x00c:
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dev_priv->fsb_freq = 3200;
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break;
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case 0x00e:
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dev_priv->fsb_freq = 3733;
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break;
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case 0x010:
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dev_priv->fsb_freq = 4266;
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break;
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case 0x012:
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dev_priv->fsb_freq = 4800;
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break;
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case 0x014:
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dev_priv->fsb_freq = 5333;
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break;
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case 0x016:
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dev_priv->fsb_freq = 5866;
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break;
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case 0x018:
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dev_priv->fsb_freq = 6400;
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break;
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default:
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DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
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csipll & 0x3ff);
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dev_priv->fsb_freq = 0;
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break;
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}
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if (dev_priv->fsb_freq == 3200) {
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dev_priv->c_m = 0;
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} else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
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dev_priv->c_m = 1;
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} else {
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dev_priv->c_m = 2;
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}
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}
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static int i915_get_bridge_dev(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
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if (!dev_priv->bridge_dev) {
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DRM_ERROR("bridge device not found\n");
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return -1;
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}
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return 0;
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}
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/* Global for IPS driver to get at the current i915 device */
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static struct drm_i915_private *i915_mch_dev;
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/*
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* Lock protecting IPS related data structures
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* - i915_mch_dev
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* - dev_priv->max_delay
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* - dev_priv->min_delay
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* - dev_priv->fmax
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* - dev_priv->gpu_busy
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*/
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static DEFINE_SPINLOCK(mchdev_lock);
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/**
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* i915_driver_load - setup chip and create an initial config
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* @dev: DRM device
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* @flags: startup flags
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*
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* The driver load routine has to do several things:
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* - drive output discovery via intel_modeset_init()
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* - initialize the memory manager
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* - allocate initial config memory
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* - setup the DRM framebuffer with the allocated memory
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*/
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int i915_driver_load(struct drm_device *dev, unsigned long flags)
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{
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struct drm_i915_private *dev_priv;
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int ret = 0, mmio_bar;
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uint32_t agp_size;
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ENTER();
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dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
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if (dev_priv == NULL)
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return -ENOMEM;
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dev->dev_private = (void *)dev_priv;
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dev_priv->dev = dev;
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dev_priv->info = (struct intel_device_info *) flags;
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if (i915_get_bridge_dev(dev)) {
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ret = -EIO;
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goto free_priv;
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}
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/* overlay on gen2 is broken and can't address above 1G */
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// if (IS_GEN2(dev))
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// dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
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/* 965GM sometimes incorrectly writes to hardware status page (HWS)
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* using 32bit addressing, overwriting memory if HWS is located
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* above 4GB.
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*
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* The documentation also mentions an issue with undefined
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* behaviour if any general state is accessed within a page above 4GB,
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* which also needs to be handled carefully.
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*/
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// if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
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// dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
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mmio_bar = IS_GEN2(dev) ? 1 : 0;
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dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
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if (!dev_priv->regs) {
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DRM_ERROR("failed to map registers\n");
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ret = -EIO;
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goto put_bridge;
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}
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dev_priv->mm.gtt = intel_gtt_get();
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if (!dev_priv->mm.gtt) {
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DRM_ERROR("Failed to initialize GTT\n");
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ret = -ENODEV;
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goto out_rmmap;
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}
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// agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
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/* agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; */
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// dev_priv->mm.gtt_mapping =
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// io_mapping_create_wc(dev->agp->base, agp_size);
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// if (dev_priv->mm.gtt_mapping == NULL) {
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// ret = -EIO;
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// goto out_rmmap;
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// }
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/* Set up a WC MTRR for non-PAT systems. This is more common than
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* one would think, because the kernel disables PAT on first
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* generation Core chips because WC PAT gets overridden by a UC
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* MTRR if present. Even if a UC MTRR isn't present.
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*/
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// dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
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// agp_size,
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// MTRR_TYPE_WRCOMB, 1);
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// if (dev_priv->mm.gtt_mtrr < 0) {
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// DRM_INFO("MTRR allocation failed. Graphics "
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// "performance may suffer.\n");
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// }
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/* The i915 workqueue is primarily used for batched retirement of
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* requests (and thus managing bo) once the task has been completed
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* by the GPU. i915_gem_retire_requests() is called directly when we
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* need high-priority retirement, such as waiting for an explicit
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* bo.
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*
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* It is also used for periodic low-priority events, such as
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* idle-timers and recording error state.
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*
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* All tasks on the workqueue are expected to acquire the dev mutex
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* so there is no point in running more than one instance of the
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* workqueue at any time: max_active = 1 and NON_REENTRANT.
|
|
*/
|
|
|
|
// dev_priv->wq = alloc_workqueue("i915",
|
|
// WQ_UNBOUND | WQ_NON_REENTRANT,
|
|
// 1);
|
|
// if (dev_priv->wq == NULL) {
|
|
// DRM_ERROR("Failed to create our workqueue.\n");
|
|
// ret = -ENOMEM;
|
|
// goto out_mtrrfree;
|
|
// }
|
|
|
|
/* enable GEM by default */
|
|
dev_priv->has_gem = 1;
|
|
|
|
|
|
// intel_irq_init(dev);
|
|
|
|
/* Try to make sure MCHBAR is enabled before poking at it */
|
|
intel_setup_mchbar(dev);
|
|
intel_setup_gmbus(dev);
|
|
intel_opregion_setup(dev);
|
|
|
|
/* Make sure the bios did its job and set up vital registers */
|
|
intel_setup_bios(dev);
|
|
|
|
i915_gem_load(dev);
|
|
|
|
/* Init HWS */
|
|
if (!I915_NEED_GFX_HWS(dev)) {
|
|
ret = i915_init_phys_hws(dev);
|
|
if (ret)
|
|
goto out_gem_unload;
|
|
}
|
|
|
|
if (IS_PINEVIEW(dev))
|
|
i915_pineview_get_mem_freq(dev);
|
|
else if (IS_GEN5(dev))
|
|
i915_ironlake_get_mem_freq(dev);
|
|
|
|
/* On the 945G/GM, the chipset reports the MSI capability on the
|
|
* integrated graphics even though the support isn't actually there
|
|
* according to the published specs. It doesn't appear to function
|
|
* correctly in testing on 945G.
|
|
* This may be a side effect of MSI having been made available for PEG
|
|
* and the registers being closely associated.
|
|
*
|
|
* According to chipset errata, on the 965GM, MSI interrupts may
|
|
* be lost or delayed, but we use them anyways to avoid
|
|
* stuck interrupts on some machines.
|
|
*/
|
|
// if (!IS_I945G(dev) && !IS_I945GM(dev))
|
|
// pci_enable_msi(dev->pdev);
|
|
|
|
spin_lock_init(&dev_priv->irq_lock);
|
|
spin_lock_init(&dev_priv->error_lock);
|
|
spin_lock_init(&dev_priv->rps_lock);
|
|
|
|
if (IS_MOBILE(dev) || !IS_GEN2(dev))
|
|
dev_priv->num_pipe = 2;
|
|
else
|
|
dev_priv->num_pipe = 1;
|
|
|
|
// ret = drm_vblank_init(dev, dev_priv->num_pipe);
|
|
// if (ret)
|
|
// goto out_gem_unload;
|
|
|
|
/* Start out suspended */
|
|
dev_priv->mm.suspended = 1;
|
|
|
|
intel_detect_pch(dev);
|
|
|
|
ret = i915_load_modeset_init(dev);
|
|
if (ret < 0) {
|
|
DRM_ERROR("failed to init modeset\n");
|
|
goto out_gem_unload;
|
|
}
|
|
|
|
/* Must be done after probing outputs */
|
|
// intel_opregion_init(dev);
|
|
// acpi_video_register();
|
|
|
|
// setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
|
|
// (unsigned long) dev);
|
|
|
|
spin_lock(&mchdev_lock);
|
|
i915_mch_dev = dev_priv;
|
|
dev_priv->mchdev_lock = &mchdev_lock;
|
|
spin_unlock(&mchdev_lock);
|
|
|
|
// ips_ping_for_i915_load();
|
|
|
|
LEAVE();
|
|
|
|
return 0;
|
|
|
|
out_gem_unload:
|
|
// if (dev_priv->mm.inactive_shrinker.shrink)
|
|
// unregister_shrinker(&dev_priv->mm.inactive_shrinker);
|
|
|
|
// if (dev->pdev->msi_enabled)
|
|
// pci_disable_msi(dev->pdev);
|
|
|
|
// intel_teardown_gmbus(dev);
|
|
// intel_teardown_mchbar(dev);
|
|
// destroy_workqueue(dev_priv->wq);
|
|
out_mtrrfree:
|
|
// if (dev_priv->mm.gtt_mtrr >= 0) {
|
|
// mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
|
|
// dev->agp->agp_info.aper_size * 1024 * 1024);
|
|
// dev_priv->mm.gtt_mtrr = -1;
|
|
// }
|
|
// io_mapping_free(dev_priv->mm.gtt_mapping);
|
|
|
|
out_rmmap:
|
|
pci_iounmap(dev->pdev, dev_priv->regs);
|
|
|
|
put_bridge:
|
|
// pci_dev_put(dev_priv->bridge_dev);
|
|
free_priv:
|
|
kfree(dev_priv);
|
|
return ret;
|
|
}
|
|
|