Aren/kolibrios
1
0
Fork 0
mirror of https://github.com/KolibriOS/kolibrios.git synced 2024-12-26 08:36:49 +03:00
Code Issues Packages Projects Releases Wiki Activity

R500 alpha blending (only pow textures)

Browse Source 
git-svn-id: svn://kolibrios.org@885 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge) 2008-10-26 20:09:43 +00:00
parent 4f001bcf95
commit 5a66f7d299
13 changed files with 1933 additions and 654 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
programs/system/drivers/ati2d/accel_3d.inc
View File

@ -805,6 +805,7 @@ static u32_t RADEONGetBlendCntl(int op, u32_t dst_format)
return sblend | dblend;
}
static Bool R300PrepareComposite(int op, int srcX, int srcY,
int dstX, int dstY,
int w, int h)
@ -1064,27 +1065,6 @@ static Bool R300PrepareComposite(int op, int srcX, int srcY,
#define VTX_COUNT 4
static __inline__ u32_t F_TO_DW(float val)
{
union {
float f;
u32_t l;
} tmp;
tmp.f = val;
return tmp.l;
}
#define OUT_RING_F(x) OUT_RING(F_TO_DW(x))
#define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \
do { \
OUT_RING_F(_dstX); \
OUT_RING_F(_dstY); \
OUT_RING_F(_srcX); \
OUT_RING_F(_srcY); \
} while (0)

29
programs/system/drivers/ati2d/ati2d.c
View File

@ -24,7 +24,7 @@ static clip_t clip;
static local_pixmap_t scr_pixmap;
static void Init3DEngine(RHDPtr rhdPtr);
int Init3DEngine(RHDPtr info);
int __stdcall srv_2d(ioctl_t *io);
@ -71,11 +71,8 @@ u32_t __stdcall drvEntry(int action)
return 0;
R5xx2DInit();
rhd.has_tcl = 1;
// Init3DEngine(&rhd);
//init_r500();
Init3DEngine(&rhd);
retval = RegService("HDRAW", srv_2d);
@ -133,6 +130,11 @@ int __stdcall srv_2d(ioctl_t *io)
return FillRect((io_fill_t*)inp);
break;
case PX_LINE:
if(io->inp_size==6)
return Line((io_draw_t*)inp);
break;
case PX_BLIT:
if(io->inp_size==8)
return Blit((io_blit_t*)inp);
@ -143,19 +145,11 @@ int __stdcall srv_2d(ioctl_t *io)
return BlitTransparent((io_blit_t*)inp);
break;
case PX_LINE:
if(io->inp_size==6)
return Line((io_draw_t*)inp);
case PX_BLIT_ALPHA:
if(io->inp_size==8)
return RadeonComposite((io_blit_t*)inp);
break;
/*
case COMPIZ:
if(io->inp_size==6)
return RadeonComposite((blit_t*)inp);
break;
*/
default:
return ERR_PARAM;
};
@ -173,6 +167,7 @@ int __stdcall srv_2d(ioctl_t *io)
#include "clip.inc"
#include "pixmap.inc"
#include "accel_2d.inc"
//#include "accel_3d.inc"
#include "init_3d.inc"
#include "blend.inc"

6
programs/system/drivers/ati2d/ati2d.h
View File

@ -322,7 +322,7 @@ do { \
ring+= 2; \
} while (0)
#define DRM_MEMORYBARRIER() __asm volatile("lock; addl $0,0(%%esp)" : : : "memory");
#define DRM_MEMORYBARRIER() __asm__ volatile("lock; addl $0,0(%%esp)" : : : "memory");
#define COMMIT_RING() do { \
rhd.ring_wp = (ring - rhd.ringBase) & 0x3FFF; \
@ -334,6 +334,10 @@ do { \
/* INREG( RADEON_CP_RB_RPTR ); */ \
} while (0)
#define BEGIN_ACCEL(n) BEGIN_RING(2*(n))
#define FINISH_ACCEL() COMMIT_RING()
#define OUT_ACCEL_REG(reg, val) CP_REG((reg), (val))
typedef struct {

642
programs/system/drivers/ati2d/blend.inc Normal file
View File

@ -0,0 +1,642 @@
struct blendinfo {
Bool dst_alpha;
Bool src_alpha;
u32_t blend_cntl;
};
static struct blendinfo RadeonBlendOp[] = {
/* 0 - Clear */
{0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ZERO},
/* 1 - Src */
{0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO},
/* 2 - Dst */
{0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE},
/* 3 - Over */
{0, 1, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
/* 4 - OverReverse */
{1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE},
/* 5 - In */
{1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO},
/* 6 - InReverse */
{0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_SRC_ALPHA},
/* 7 - Out */
{1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO},
/* 8 - OutReverse */
{0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
/* 9 - Atop */
{1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
/* 10- AtopReverse */
{1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_SRC_ALPHA},
/* 11 - Xor */
{1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA},
/* 12 - Add */
{0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE},
};
static Bool R300TextureSetup(RHDPtr info,local_pixmap_t *srcpix, int w, int h, int unit)
{
u32_t txfilter, txformat0, txformat1, txoffset, txpitch;
// int w = pPict->pDrawable->width;
// int h = pPict->pDrawable->height;
int i, pixel_shift;
txpitch = srcpix->pitch;
txoffset = (u32_t)srcpix->local;
if ((txoffset & 0x1f) != 0)
dbgprintf("Bad texture offset 0x%x\n", (int)txoffset);
if ((txpitch & 0x1f) != 0)
dbgprintf("Bad texture pitch 0x%x\n", (int)txpitch);
/* TXPITCH = pixels (texels) per line - 1 */
pixel_shift = 32 >> 4;
txpitch >>= pixel_shift;
txpitch -= 1;
// if (RADEONPixmapIsColortiled(pPix))
// txoffset |= R300_MACRO_TILE;
// for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++)
// {
// if (R300TexFormats[i].fmt == pPict->format)
// break;
// }
//txformat1 = R300TexFormats[i].card_fmt;
txformat1 = R300_TX_FORMAT_A8R8G8B8;// R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) |
(((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT));
if (IS_R500_3D && ((w - 1) & 0x800))
txpitch |= R500_TXWIDTH_11;
if (IS_R500_3D && ((h - 1) & 0x800))
txpitch |= R500_TXHEIGHT_11;
/* Use TXPITCH instead of TXWIDTH for address computations: we could
* omit this if there is no padding, but there is no apparent advantage
* in doing so.
*/
txformat0 |= R300_TXPITCH_EN;
// info->texW[unit] = w;
// info->texH[unit] = h;
// if (pPict->repeat && !(unit == 0 && need_src_tile_x))
// txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP);
// else
txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL);
// if (pPict->repeat && !(unit == 0 && need_src_tile_y))
// txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP);
// else
txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL);
txfilter |= (unit << R300_TX_ID_SHIFT);
// switch (pPict->filter) {
// case PictFilterNearest:
txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST);
// break;
// case PictFilterBilinear:
// txfilter |= (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR);
// break;
// default:
// RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
// }
{
u32_t *ring;
u32_t ifl = safe_cli();
BEGIN_ACCEL(7);
OUT_ACCEL_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter);
OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0);
OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0);
OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1);
OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch);
OUT_ACCEL_REG(R300_TX_OFFSET_0 + (unit * 4), txoffset);
// if (!pPict->repeat)
OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0);
COMMIT_RING();
safe_sti(ifl);
}
// if (pPict->transform != 0) {
// is_transform[unit] = TRUE;
// transform[unit] = pPict->transform;
// } else {
// is_transform[unit] = FALSE;
// }
return TRUE;
}
static u32_t RADEONGetBlendCntl(int op, u32_t dst_format)
{
u32_t sblend, dblend;
// sblend = RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK;
// dblend = RadeonBlendOp[op].blend_cntl & RADEON_DST_BLEND_MASK;
/* If there's no dst alpha channel, adjust the blend op so that we'll treat
* it as always 1.
*/
// if ( RadeonBlendOp[op].dst_alpha) {
// if (sblend == RADEON_SRC_BLEND_GL_DST_ALPHA)
// sblend = RADEON_SRC_BLEND_GL_ONE;
// else if (sblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA)
// sblend = RADEON_SRC_BLEND_GL_ZERO;
// }
//return sblend | dblend;
return RADEON_SRC_BLEND_GL_SRC_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA;
}
Bool R300PrepareComposite(local_pixmap_t *dstpix, int dstX, int dstY,
local_pixmap_t *srcpix, int srcX, int srcY,
int w, int h, int op)
{
// RINFO_FROM_SCREEN(pDst->drawable.pScreen);
u32_t dst_format, dst_offset, dst_pitch;
u32_t txenable, colorpitch;
u32_t blendcntl;
int pixel_shift;
u32_t *ring;
u32_t ifl;
RHDPtr info = &rhd;
dst_format = R300_COLORFORMAT_ARGB8888;
dst_offset = (u32_t)dstpix->local;
dst_pitch = dstpix->pitch;
pixel_shift = 32 >> 4;
colorpitch = dst_pitch >> pixel_shift;
// if (RADEONPixmapIsColortiled(pDst))
// colorpitch |= R300_COLORTILE;
colorpitch |= dst_format;
if ((dst_offset & 0x0f) != 0)
dbgprintf("Bad destination offset 0x%x\n", (int)dst_offset);
if (((dst_pitch >> pixel_shift) & 0x7) != 0)
dbgprintf("Bad destination pitch 0x%x\n", (int)dst_pitch);
// if (!RADEONSetupSourceTile(pSrcPicture, pSrc, TRUE, FALSE))
// return FALSE;
if (!R300TextureSetup(&rhd, srcpix, w, h, 0))
return FALSE;
txenable = R300_TEX_0_ENABLE;
// RADEON_SWITCH_TO_3D();
/* setup the VAP */
ifl = safe_cli();
BEGIN_RING(32*2);
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_HOST_IDLECLEAN |
RADEON_WAIT_3D_IDLECLEAN);
/* These registers define the number, type, and location of data submitted
* to the PVS unit of GA input (when PVS is disabled)
* DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is
* enabled. This memory provides the imputs to the vertex shader program
* and ordering is not important. When PVS/TCL is disabled, this field maps
* directly to the GA input memory and the order is signifigant. In
* PVS_BYPASS mode the order is as follows:
* 0 Position
* 1 Point Size
* 2 Color 0
* 3 Color 1
* 4 Color 2
* 5 Color 3
* 6 Textures 0
* 7 Textures 1
* 8 Textures 2
* 9 Textures 3 - 7
* 14 Fog
*/
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
(0 << R300_SKIP_DWORDS_0_SHIFT) |
(0 << R300_DST_VEC_LOC_0_SHIFT) |
R300_SIGNED_0 |
(R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
(0 << R300_SKIP_DWORDS_1_SHIFT) |
(6 << R300_DST_VEC_LOC_1_SHIFT) |
R300_LAST_VEC_1 |
R300_SIGNED_1));
/* load the vertex shader
* We pre-load vertex programs in RADEONInit3DEngine():
* - exa no mask
* - exa mask
* - Xv
* Here we select the offset of the vertex program we want to use
*/
OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
((3 << R300_PVS_FIRST_INST_SHIFT) |
(4 << R300_PVS_XYZW_VALID_INST_SHIFT) |
(4 << R300_PVS_LAST_INST_SHIFT)));
OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
(4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
/* Position and one or two sets of 2 texture coordinates */
OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); //VTX_COLOR_0_PRESENT
OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0);
OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
FINISH_ACCEL();
/* setup pixel shader */
/* setup pixel shader */
if (IS_R300_3D)
{
}
else
{
u32_t output_fmt;
u32_t src_color, src_alpha;
u32_t mask_color, mask_alpha;
// if (PICT_FORMAT_RGB(PICT_a8r8g8b8) == 0)
// src_color = (R500_ALU_RGB_R_SWIZ_A_0 |
// R500_ALU_RGB_G_SWIZ_A_0 |
// R500_ALU_RGB_B_SWIZ_A_0);
// else
src_color = (R500_ALU_RGB_R_SWIZ_A_R |
R500_ALU_RGB_G_SWIZ_A_G |
R500_ALU_RGB_B_SWIZ_A_B);
// if (PICT_FORMAT_A(PICT_a8r8g8b8) == 0)
// src_alpha = R500_ALPHA_SWIZ_A_1;
// else
src_alpha = R500_ALPHA_SWIZ_A_A;
mask_color = (R500_ALU_RGB_R_SWIZ_B_1 |
R500_ALU_RGB_G_SWIZ_B_1 |
R500_ALU_RGB_B_SWIZ_B_1);
mask_alpha = R500_ALPHA_SWIZ_B_1;
/* shader output swizzling */
output_fmt = (R300_OUT_FMT_C4_8 |
R300_OUT_FMT_C0_SEL_BLUE |
R300_OUT_FMT_C1_SEL_GREEN |
R300_OUT_FMT_C2_SEL_RED |
R300_OUT_FMT_C3_SEL_ALPHA);
BEGIN_ACCEL(6);
OUT_ACCEL_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
R500_US_CODE_END_ADDR(1)));
OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
R500_US_CODE_RANGE_SIZE(1)));
OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
COMMIT_RING();
BEGIN_ACCEL(13);
OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
/* tex inst for src texture */
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
R500_INST_TEX_SEM_WAIT |
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
R500_INST_ALPHA_WMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP));
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
R500_TEX_SEM_ACQUIRE |
R500_TEX_IGNORE_UNCOVERED));
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
R500_TEX_SRC_S_SWIZ_R |
R500_TEX_SRC_T_SWIZ_G |
R500_TEX_DST_ADDR(0) |
R500_TEX_DST_R_SWIZ_R |
R500_TEX_DST_G_SWIZ_G |
R500_TEX_DST_B_SWIZ_B |
R500_TEX_DST_A_SWIZ_A));
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
R500_DX_S_SWIZ_R |
R500_DX_T_SWIZ_R |
R500_DX_R_SWIZ_R |
R500_DX_Q_SWIZ_R |
R500_DY_ADDR(0) |
R500_DY_S_SWIZ_R |
R500_DY_T_SWIZ_R |
R500_DY_R_SWIZ_R |
R500_DY_Q_SWIZ_R));
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
/* ALU inst */
/* *_OMASK* - output component write mask */
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
R500_INST_TEX_SEM_WAIT |
R500_INST_LAST |
R500_INST_RGB_OMASK_R |
R500_INST_RGB_OMASK_G |
R500_INST_RGB_OMASK_B |
R500_INST_ALPHA_OMASK |
R500_INST_RGB_CLAMP |
R500_INST_ALPHA_CLAMP));
/* ALU inst
* temp addresses for texture inputs
* RGB_ADDR0 is src tex (temp 0)
* RGB_ADDR1 is mask tex (temp 1)
*/
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR1(1) |
R500_RGB_ADDR2(0)));
/* ALU inst
* temp addresses for texture inputs
* ALPHA_ADDR0 is src tex (temp 0)
* ALPHA_ADDR1 is mask tex (temp 1)
*/
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
R500_ALPHA_ADDR1(1) |
R500_ALPHA_ADDR2(0)));
/* R500_ALU_RGB_TARGET - RGB render target */
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
src_color |
R500_ALU_RGB_SEL_B_SRC1 |
mask_color |
R500_ALU_RGB_TARGET(0)));
/* R500_ALPHA_RGB_TARGET - alpha render target */
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
R500_ALPHA_ADDRD(0) |
R500_ALPHA_SEL_A_SRC0 |
src_alpha |
R500_ALPHA_SEL_B_SRC1 |
mask_alpha |
R500_ALPHA_TARGET(0)));
OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
R500_ALU_RGBA_ADDRD(0) |
R500_ALU_RGBA_R_SWIZ_0 |
R500_ALU_RGBA_G_SWIZ_0 |
R500_ALU_RGBA_B_SWIZ_0 |
R500_ALU_RGBA_A_SWIZ_0));
FINISH_ACCEL();
}
BEGIN_ACCEL(3);
OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
blendcntl = RADEONGetBlendCntl(op, PICT_a8r8g8b8);
OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE |
R300_READ_ENABLE);
FINISH_ACCEL();
safe_sti(ifl);
return TRUE;
}
#define VTX_COUNT 4
static __inline__ u32_t F_TO_DW(float val)
{
union {
float f;
u32_t l;
} tmp;
tmp.f = val;
return tmp.l;
}
#define OUT_RING_F(x) OUT_RING(F_TO_DW(x))
#define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \
do { \
OUT_RING_F(_dstX); \
OUT_RING_F(_dstY); \
OUT_RING_F(_srcX); \
OUT_RING_F(_srcY); \
} while (0)
static int RadeonCompositeTile(int srcX, int srcY,
int dstX, int dstY,
int w, int h)
{
// RINFO_FROM_SCREEN(pDst->drawable.pScreen);
int vtx_count;
xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight;
u32_t *ring;
u32_t ifl;
// ACCEL_PREAMBLE();
// ENTER_DRAW(0);
/* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n",
srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
srcTopLeft.x = IntToxFixed(srcX);
srcTopLeft.y = IntToxFixed(srcY);
srcTopRight.x = IntToxFixed(srcX + w);
srcTopRight.y = IntToxFixed(srcY);
srcBottomLeft.x = IntToxFixed(srcX);
srcBottomLeft.y = IntToxFixed(srcY + h);
srcBottomRight.x = IntToxFixed(srcX + w);
srcBottomRight.y = IntToxFixed(srcY + h);
/*
if (is_transform[0]) {
transformPoint(transform[0], &srcTopLeft);
transformPoint(transform[0], &srcTopRight);
transformPoint(transform[0], &srcBottomLeft);
transformPoint(transform[0], &srcBottomRight);
}
if (is_transform[1]) {
transformPoint(transform[1], &maskTopLeft);
transformPoint(transform[1], &maskTopRight);
transformPoint(transform[1], &maskBottomLeft);
transformPoint(transform[1], &maskBottomRight);
}
*/
vtx_count = VTX_COUNT;
ifl = safe_cli();
BEGIN_RING(7 + 4 * vtx_count);
OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count);
OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
4 * vtx_count));
OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
RADEON_CP_VC_CNTL_PRIM_WALK_RING |
(4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
VTX_OUT((float)dstX, (float)dstY,
xFixedToFloat(srcTopLeft.x) / w, // info->texW[0],
xFixedToFloat(srcTopLeft.y) / h); // info->texH[0]);
VTX_OUT((float)dstX, (float)(dstY + h),
xFixedToFloat(srcBottomLeft.x) / w, // info->texW[0],
xFixedToFloat(srcBottomLeft.y) / h); // info->texH[0]);
VTX_OUT((float)(dstX + w), (float)(dstY + h),
xFixedToFloat(srcBottomRight.x) / w, // info->texW[0],
xFixedToFloat(srcBottomRight.y) / h); // info->texH[0]);
VTX_OUT((float)(dstX + w), (float)dstY,
xFixedToFloat(srcTopRight.x) / w, // info->texW[0],
xFixedToFloat(srcTopRight.y) / h); // info->texH[0]);
/* flushing is pipelined, free/finish is not */
OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
COMMIT_RING();
safe_sti(ifl);
// LEAVE_DRAW(0);
}
#undef VTX_OUT
#undef VTX_OUT_MASK
int RadeonComposite( io_blit_t *blit)
{
int tileSrcY, tileMaskY, tileDstY;
int remainingHeight;
local_pixmap_t *srcpixmap;
local_pixmap_t *dstpixmap;
dbgprintf("Blit Alpha src: %x dst: %x\n",blit->srcpix, blit->dstpix);
dstpixmap = (blit->dstpix == (void*)-1) ? &scr_pixmap : blit->dstpix ;
srcpixmap = (blit->srcpix == (void*)-1) ? &scr_pixmap : blit->srcpix ;
{
u32_t *ring;
u32_t ifl = safe_cli();
BEGIN_RING(2 + 6);
CP_REG(R5XX_DP_WRITE_MASK, 0xFF000000);
OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4));
OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
RADEON_GMC_BRUSH_SOLID_COLOR |
RADEON_GMC_DST_32BPP |
RADEON_GMC_SRC_DATATYPE_COLOR |
R5XX_GMC_CLR_CMP_CNTL_DIS |
R5XX_ROP3_P
);
OUT_RING(srcpixmap->pitch_offset);
OUT_RING(blit->key);
OUT_RING( 0 );
OUT_RING((srcpixmap->width<<16)|srcpixmap->height);
COMMIT_RING();
safe_sti(ifl);
};
R300PrepareComposite(dstpixmap, blit->dst_x, blit->dst_y,
srcpixmap, blit->src_x, blit->src_y,
blit->w, blit->h, 3);
// if (!need_src_tile_x && !need_src_tile_y) {
RadeonCompositeTile( blit->src_x, blit->src_y,
blit->dst_x, blit->dst_y,
blit->w, blit->h);
return 0;
// }
/* Tiling logic borrowed from exaFillRegionTiled */
#if 0
modulus(srcY, src_tile_height, tileSrcY);
tileMaskY = maskY;
tileDstY = dstY;
remainingHeight = height;
while (remainingHeight > 0) {
int remainingWidth = width;
int tileSrcX, tileMaskX, tileDstX;
int h = src_tile_height - tileSrcY;
if (h > remainingHeight)
h = remainingHeight;
remainingHeight -= h;
modulus(srcX, src_tile_width, tileSrcX);
tileMaskX = maskX;
tileDstX = dstX;
while (remainingWidth > 0) {
int w = src_tile_width - tileSrcX;
if (w > remainingWidth)
w = remainingWidth;
remainingWidth -= w;
FUNC_NAME(RadeonCompositeTile)(pDst,
tileSrcX, tileSrcY,
tileMaskX, tileMaskY,
tileDstX, tileDstY,
w, h);
tileSrcX = 0;
tileMaskX += w;
tileDstX += w;
}
tileSrcY = 0;
tileMaskY += h;
tileDstY += h;
}
#endif
}

2
programs/system/drivers/ati2d/clip.inc
View File

@ -170,7 +170,7 @@ int blit_clip(clip_t *dst_clip,int *dst_x,int *dst_y,
*src_y += dy0 - *dst_y;
*dst_x = dx0;
*dst_y = dx0;
*dst_y = dy0;
return 0;
};

9
programs/system/drivers/ati2d/init.c
View File

@ -226,6 +226,7 @@ static void radeon_write_mc_fb_agp_location(RHDPtr info, int mask, u32_t fb_loc,
}
}
#if !R300_PIO
static void RADEONUpdateMemMapRegisters(RHDPtr info)
{
@ -444,6 +445,9 @@ static void RADEONUpdateMemMapRegisters(RHDPtr info)
};
};
#endif
static void RADEONInitMemoryMap(RHDPtr info)
{
@ -550,7 +554,12 @@ static void RADEONInitMemoryMap(RHDPtr info)
dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location);
dbgprintf(" FB_LOCATION : 0x%08x\n", (unsigned)info->fbLocation);
#if !R300_PIO
RADEONUpdateMemMapRegisters(info);
#endif
}
static void RADEONGetVRamType(RHDPtr info)

645
programs/system/drivers/ati2d/init_3d.inc Normal file
View File

@ -0,0 +1,645 @@
int Init3DEngine(RHDPtr info)
{
u32_t gb_tile_config, su_reg_dest, vap_cntl;
u32_t *ring;
u32_t ifl;
// info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1;
ifl = safe_cli();
if (IS_R300_3D || IS_R500_3D) {
BEGIN_ACCEL(3);
OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
FINISH_ACCEL();
gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16);
switch(info->num_gb_pipes)
{
case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
default:
case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
}
BEGIN_ACCEL(5);
OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config);
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG);
OUT_ACCEL_REG(R300_GB_SELECT, 0);
OUT_ACCEL_REG(R300_GB_ENABLE, 0);
FINISH_ACCEL();
if (IS_R500_3D) {
su_reg_dest = ((1 << info->num_gb_pipes) - 1);
BEGIN_ACCEL(2);
OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest);
OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0);
FINISH_ACCEL();
}
BEGIN_ACCEL(3);
OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
FINISH_ACCEL();
BEGIN_ACCEL(5);
OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0);
OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) |
(8 << R300_MS_Y0_SHIFT) |
(8 << R300_MS_X1_SHIFT) |
(8 << R300_MS_Y1_SHIFT) |
(8 << R300_MS_X2_SHIFT) |
(8 << R300_MS_Y2_SHIFT) |
(8 << R300_MSBD0_Y_SHIFT) |
(7 << R300_MSBD0_X_SHIFT)));
OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) |
(8 << R300_MS_Y3_SHIFT) |
(8 << R300_MS_X4_SHIFT) |
(8 << R300_MS_Y4_SHIFT) |
(8 << R300_MS_X5_SHIFT) |
(8 << R300_MS_Y5_SHIFT) |
(8 << R300_MSBD1_SHIFT)));
FINISH_ACCEL();
BEGIN_ACCEL(5);
OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
R300_COLOR_ROUND_NEAREST));
OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD |
R300_ALPHA0_SHADING_GOURAUD |
R300_RGB1_SHADING_GOURAUD |
R300_ALPHA1_SHADING_GOURAUD |
R300_RGB2_SHADING_GOURAUD |
R300_ALPHA2_SHADING_GOURAUD |
R300_RGB3_SHADING_GOURAUD |
R300_ALPHA3_SHADING_GOURAUD));
OUT_ACCEL_REG(R300_GA_OFFSET, 0);
FINISH_ACCEL();
BEGIN_ACCEL(5);
OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0);
OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0);
OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG);
OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff);
OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0);
FINISH_ACCEL();
/* setup the VAP */
if (info->has_tcl)
vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) |
(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
(9 << R300_VF_MAX_VTX_NUM_SHIFT));
else
vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
(5 << R300_VF_MAX_VTX_NUM_SHIFT));
if (info->ChipFamily == CHIP_FAMILY_RV515)
vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
else if ((info->ChipFamily == CHIP_FAMILY_RV530) ||
(info->ChipFamily == CHIP_FAMILY_RV560) ||
(info->ChipFamily == CHIP_FAMILY_RV570))
vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
else if ((info->ChipFamily == CHIP_FAMILY_RV410) ||
(info->ChipFamily == CHIP_FAMILY_R420))
vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
else if ((info->ChipFamily == CHIP_FAMILY_R520) ||
(info->ChipFamily == CHIP_FAMILY_R580))
vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
else
vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
if (info->has_tcl)
BEGIN_ACCEL(15)
else
BEGIN_ACCEL(9);
OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0);
OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
if (info->has_tcl)
OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
else
OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl);
OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
(R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
(R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_0_SHIFT) |
(R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
(R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
(R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_1_SHIFT)));
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
(R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
(R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) |
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_2_SHIFT)));
if (info->has_tcl) {
OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
}
FINISH_ACCEL();
/* pre-load the vertex shaders */
if (info->has_tcl) {
/* exa mask/Xv bicubic shader program
dcl_position v0
dcl_texcoord v1
dcl_texcoord1 v2
mov oPos, v0
mov oT0, v1
mov oT1, v2 */
BEGIN_ACCEL(13);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
/* PVS inst 0 */
OUT_ACCEL_REG (R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
R300_PVS_DST_OFFSET(0) |
R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
OUT_ACCEL_REG (R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(0) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
OUT_ACCEL_REG (R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(0) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
OUT_ACCEL_REG (R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(0) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
/* PVS inst 1 */
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
R300_PVS_DST_OFFSET(1) |
R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(6) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(6) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(6) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
/* PVS inst 2 */
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
R300_PVS_DST_OFFSET(2) |
R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(7) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(7) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(7) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
FINISH_ACCEL();
BEGIN_ACCEL(9);
/* exa no mask instruction
dcl_position v0
dcl_texcoord v1
mov oPos, v0
mov oT0, v1 */
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 3);
/* PVS inst 0 */
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
R300_PVS_DST_OFFSET(0) |
R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(0) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(0) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(0) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
/* PVS inst 1 */
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
R300_PVS_DST_OFFSET(1) |
R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(6) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(6) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(6) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
FINISH_ACCEL();
/* Xv shader program */
BEGIN_ACCEL(9);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5);
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
R300_PVS_DST_OFFSET(0) |
R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(0) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(0) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(0) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_DST_OPCODE(R300_VE_ADD) |
R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
R300_PVS_DST_OFFSET(1) |
R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(6) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(6) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
(R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
R300_PVS_SRC_OFFSET(6) |
R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
FINISH_ACCEL();
}
/* pre-load the RS instructions */
BEGIN_ACCEL(4);
if (IS_R300_3D) {
/* rasterizer source table
* R300_RS_TEX_PTR is the offset into the input RS stream
* 0,1 are tex0
* 2,3 are tex1
*/
OUT_ACCEL_REG(R300_RS_IP_0,
(R300_RS_TEX_PTR(0) |
R300_RS_SEL_S(R300_RS_SEL_C0) |
R300_RS_SEL_T(R300_RS_SEL_C1) |
R300_RS_SEL_R(R300_RS_SEL_K0) |
R300_RS_SEL_Q(R300_RS_SEL_K1)));
OUT_ACCEL_REG(R300_RS_IP_1,
(R300_RS_TEX_PTR(2) |
R300_RS_SEL_S(R300_RS_SEL_C0) |
R300_RS_SEL_T(R300_RS_SEL_C1) |
R300_RS_SEL_R(R300_RS_SEL_K0) |
R300_RS_SEL_Q(R300_RS_SEL_K1)));
/* src tex */
/* R300_INST_TEX_ID - select the RS source table entry
* R300_INST_TEX_ADDR - the FS temp register for the texture data
*/
OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
R300_RS_INST_TEX_CN_WRITE |
R300_INST_TEX_ADDR(0)));
/* mask tex */
OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) |
R300_RS_INST_TEX_CN_WRITE |
R300_INST_TEX_ADDR(1)));
} else {
/* rasterizer source table
* R300_RS_TEX_PTR is the offset into the input RS stream
* 0,1 are tex0
* 2,3 are tex1
*/
OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
(1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
(R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) |
(3 << R500_RS_IP_TEX_PTR_T_SHIFT) |
(R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
(R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
/* src tex */
/* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry
* R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data
*/
OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
R500_RS_INST_TEX_CN_WRITE |
(0 << R500_RS_INST_TEX_ADDR_SHIFT)));
/* mask tex */
OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) |
R500_RS_INST_TEX_CN_WRITE |
(1 << R500_RS_INST_TEX_ADDR_SHIFT)));
}
FINISH_ACCEL();
/* pre-load FS tex instructions */
if (IS_R300_3D) {
BEGIN_ACCEL(2);
/* tex inst for src texture */
OUT_ACCEL_REG(R300_US_TEX_INST_0,
(R300_TEX_SRC_ADDR(0) |
R300_TEX_DST_ADDR(0) |
R300_TEX_ID(0) |
R300_TEX_INST(R300_TEX_INST_LD)));
/* tex inst for mask texture */
OUT_ACCEL_REG(R300_US_TEX_INST_1,
(R300_TEX_SRC_ADDR(1) |
R300_TEX_DST_ADDR(1) |
R300_TEX_ID(1) |
R300_TEX_INST(R300_TEX_INST_LD)));
FINISH_ACCEL();
}
if (IS_R300_3D) {
BEGIN_ACCEL(8);
OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
(R300_ALU_START(0) |
R300_ALU_SIZE(0) |
R300_TEX_START(0) |
R300_TEX_SIZE(0)));
OUT_ACCEL_REG(R300_US_CODE_ADDR_1,
(R300_ALU_START(0) |
R300_ALU_SIZE(0) |
R300_TEX_START(0) |
R300_TEX_SIZE(0)));
OUT_ACCEL_REG(R300_US_CODE_ADDR_2,
(R300_ALU_START(0) |
R300_ALU_SIZE(0) |
R300_TEX_START(0) |
R300_TEX_SIZE(0)));
} else {
BEGIN_ACCEL(6);
OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
}
OUT_ACCEL_REG(R300_US_W_FMT, 0);
OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED |
R300_OUT_FMT_C0_SEL_BLUE |
R300_OUT_FMT_C1_SEL_GREEN |
R300_OUT_FMT_C2_SEL_RED |
R300_OUT_FMT_C3_SEL_ALPHA));
OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED |
R300_OUT_FMT_C0_SEL_BLUE |
R300_OUT_FMT_C1_SEL_GREEN |
R300_OUT_FMT_C2_SEL_RED |
R300_OUT_FMT_C3_SEL_ALPHA));
OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED |
R300_OUT_FMT_C0_SEL_BLUE |
R300_OUT_FMT_C1_SEL_GREEN |
R300_OUT_FMT_C2_SEL_RED |
R300_OUT_FMT_C3_SEL_ALPHA));
FINISH_ACCEL();
BEGIN_ACCEL(3);
OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0);
OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0);
OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0);
FINISH_ACCEL();
BEGIN_ACCEL(13);
OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0);
OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0);
OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0);
OUT_ACCEL_REG(R300_RB3D_ZTOP, 0);
OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0);
OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0);
OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN |
R300_GREEN_MASK_EN |
R300_RED_MASK_EN |
R300_ALPHA_MASK_EN));
OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
OUT_ACCEL_REG(R300_RB3D_CCTL, 0);
OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0);
OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
FINISH_ACCEL();
BEGIN_ACCEL(7);
OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5);
OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) |
(0 << R300_SCISSOR_Y_SHIFT)));
OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) |
(8191 << R300_SCISSOR_Y_SHIFT)));
if (IS_R300_3D) {
/* clip has offset 1440 */
OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) |
(1088 << R300_CLIP_Y_SHIFT)));
OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2920) << R300_CLIP_X_SHIFT) |
((1080 + 2920) << R300_CLIP_Y_SHIFT)));
} else {
OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) |
(0 << R300_CLIP_Y_SHIFT)));
OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
(4080 << R300_CLIP_Y_SHIFT)));
}
OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA);
OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff);
FINISH_ACCEL();
} else if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
(info->ChipFamily == CHIP_FAMILY_RV280) ||
(info->ChipFamily == CHIP_FAMILY_RS300) ||
(info->ChipFamily == CHIP_FAMILY_R200)) {
BEGIN_ACCEL(7);
if (info->ChipFamily == CHIP_FAMILY_RS300) {
OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
} else {
OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0);
}
OUT_ACCEL_REG(R200_PP_CNTL_X, 0);
OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0);
OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0);
OUT_ACCEL_REG(R200_RE_CNTL, 0x0);
OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0);
OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE |
R200_VAP_VF_MAX_VTX_NUM);
FINISH_ACCEL();
BEGIN_ACCEL(5);
OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
RADEON_BFACE_SOLID |
RADEON_FFACE_SOLID |
RADEON_VTX_PIX_CENTER_OGL |
RADEON_ROUND_MODE_ROUND |
RADEON_ROUND_PREC_4TH_PIX));
FINISH_ACCEL();
} else {
BEGIN_ACCEL(2);
if ((info->ChipFamily == CHIP_FAMILY_RADEON) ||
(info->ChipFamily == CHIP_FAMILY_RV200))
OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0);
else
OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
OUT_ACCEL_REG(RADEON_SE_COORD_FMT,
RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
RADEON_VTX_ST0_NONPARAMETRIC |
RADEON_VTX_ST1_NONPARAMETRIC |
RADEON_TEX1_W_ROUTING_USE_W0);
FINISH_ACCEL();
BEGIN_ACCEL(5);
OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0);
OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff);
OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0);
OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff);
OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD |
RADEON_BFACE_SOLID |
RADEON_FFACE_SOLID |
RADEON_VTX_PIX_CENTER_OGL |
RADEON_ROUND_MODE_ROUND |
RADEON_ROUND_PREC_4TH_PIX));
FINISH_ACCEL();
}
safe_sti(ifl);
}

6
programs/system/drivers/ati2d/init_cp.c
View File

@ -303,7 +303,7 @@ void init_ring_buffer(RHDPtr info)
OUTREG(RADEON_CP_RB_WPTR,rhd.ring_rp);
tmp = (((u32_t)&rhd.host_rp) & 4095) + GetPgAddr(&rhd.host_rp);
tmp = (((u32_t)&rhd.host_rp) & 4095) + GetPgAddr((void*)&rhd.host_rp);
OUTREG(RADEON_CP_RB_RPTR_ADDR, tmp); // ring buffer read pointer
@ -318,7 +318,7 @@ void init_ring_buffer(RHDPtr info)
* with PCI GART as well as (whatever kind of) AGP GART
*/
tmp = (((u32_t)&rhd.scratch0) & 4095) + GetPgAddr(&rhd.scratch0);
tmp = (((u32_t)&rhd.scratch0) & 4095) + GetPgAddr((void*)&rhd.scratch0);
OUTREG(RADEON_SCRATCH_ADDR, tmp);
OUTREG(RADEON_SCRATCH_UMSK, 0x0);
@ -482,7 +482,6 @@ static int radeon_cp_start(RHDPtr info)
safe_sti(ifl);
radeon_do_wait_for_idle();
dbgprintf("run cp RPTR= %d\n", INREG(RADEON_CP_RB_RPTR) );
};
@ -498,7 +497,6 @@ Bool init_cp(RHDPtr info)
init_pipes(&rhd);
rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR);
dbgprintf("ring wp= %x\n",rhd.ring_wp);
OUTREG(RADEON_CP_RB_WPTR, rhd.ring_rp);
radeon_cp_start(&rhd);

5
programs/system/drivers/ati2d/makefile
View File

@ -9,11 +9,14 @@ HFILES:= ati2d.h \
pci.h \
accel_2d.h \
r5xx_regs.h \
microcode.h
radeon_microcode.h
SRC_DEP:= init.c \
pci.c \
ati_mem.c \
init_cp.c \
init_3d.inc \
blend.inc \
r500.inc \
pixmap.inc \
accel_2d.inc \

519
programs/system/drivers/ati2d/microcode.h
View File

@ -1,519 +0,0 @@
static const u32_t R300_cp_microcode[][2]={
{ 0x4200e000, 0000000000 },
{ 0x4000e000, 0000000000 },
{ 0x000000ae, 0x00000008 },
{ 0x000000b2, 0x00000008 },
{ 0x67554b4a, 0000000000 },
{ 0x4a4a4475, 0000000000 },
{ 0x55527d83, 0000000000 },
{ 0x4a8c8b65, 0000000000 },
{ 0x4aef4af6, 0000000000 },
{ 0x4ae14a4a, 0000000000 },
{ 0xe4979797, 0000000000 },
{ 0xdb4aebdd, 0000000000 },
{ 0x9ccc4a4a, 0000000000 },
{ 0xd1989898, 0000000000 },
{ 0x4a0f9ad6, 0000000000 },
{ 0x000ca000, 0x00000004 },
{ 0x000d0012, 0x00000038 },
{ 0x0000e8b4, 0x00000004 },
{ 0x000d0014, 0x00000038 },
{ 0x0000e8b6, 0x00000004 },
{ 0x000d0016, 0x00000038 },
{ 0x0000e854, 0x00000004 },
{ 0x000d0018, 0x00000038 },
{ 0x0000e855, 0x00000004 },
{ 0x000d001a, 0x00000038 },
{ 0x0000e856, 0x00000004 },
{ 0x000d001c, 0x00000038 },
{ 0x0000e857, 0x00000004 },
{ 0x000d001e, 0x00000038 },
{ 0x0000e824, 0x00000004 },
{ 0x000d0020, 0x00000038 },
{ 0x0000e825, 0x00000004 },
{ 0x000d0022, 0x00000038 },
{ 0x0000e830, 0x00000004 },
{ 0x000d0024, 0x00000038 },
{ 0x0000f0c0, 0x00000004 },
{ 0x000d0026, 0x00000038 },
{ 0x0000f0c1, 0x00000004 },
{ 0x000d0028, 0x00000038 },
{ 0x0000f041, 0x00000004 },
{ 0x000d002a, 0x00000038 },
{ 0x0000f184, 0x00000004 },
{ 0x000d002c, 0x00000038 },
{ 0x0000f185, 0x00000004 },
{ 0x000d002e, 0x00000038 },
{ 0x0000f186, 0x00000004 },
{ 0x000d0030, 0x00000038 },
{ 0x0000f187, 0x00000004 },
{ 0x000d0032, 0x00000038 },
{ 0x0000f180, 0x00000004 },
{ 0x000d0034, 0x00000038 },
{ 0x0000f393, 0x00000004 },
{ 0x000d0036, 0x00000038 },
{ 0x0000f38a, 0x00000004 },
{ 0x000d0038, 0x00000038 },
{ 0x0000f38e, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00000043, 0x00000018 },
{ 0x00cce800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x0000003a, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x2000451d, 0x00000004 },
{ 0x0000e580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x08004580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x00000047, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x00032000, 0x00000004 },
{ 0x00022051, 0x00000028 },
{ 0x00000051, 0x00000024 },
{ 0x0800450f, 0x00000004 },
{ 0x0000a04b, 0x00000008 },
{ 0x0000e565, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x00000052, 0x00000008 },
{ 0x03cca5b4, 0x00000004 },
{ 0x05432000, 0x00000004 },
{ 0x00022000, 0x00000004 },
{ 0x4ccce05e, 0x00000030 },
{ 0x08274565, 0x00000004 },
{ 0x0000005e, 0x00000030 },
{ 0x08004564, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x00000055, 0x00000008 },
{ 0x00802061, 0x00000010 },
{ 0x00202000, 0x00000004 },
{ 0x001b00ff, 0x00000004 },
{ 0x01000064, 0x00000010 },
{ 0x001f2000, 0x00000004 },
{ 0x001c00ff, 0x00000004 },
{ 0000000000, 0x0000000c },
{ 0x00000080, 0x00000030 },
{ 0x00000055, 0x00000008 },
{ 0x0000e576, 0x00000004 },
{ 0x000ca000, 0x00000004 },
{ 0x00012000, 0x00000004 },
{ 0x00082000, 0x00000004 },
{ 0x1800650e, 0x00000004 },
{ 0x00092000, 0x00000004 },
{ 0x000a2000, 0x00000004 },
{ 0x000f0000, 0x00000004 },
{ 0x00400000, 0x00000004 },
{ 0x00000074, 0x00000018 },
{ 0x0000e563, 0x00000004 },
{ 0x00c0e5f9, 0x000000c2 },
{ 0x00000069, 0x00000008 },
{ 0x0000a069, 0x00000008 },
{ 0x0000e576, 0x00000004 },
{ 0x0000e577, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x0000e50f, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00000077, 0x00000018 },
{ 0x00c0e5f9, 0x000000c2 },
{ 0x00000077, 0x00000008 },
{ 0x0014e50e, 0x00000004 },
{ 0x0040e50f, 0x00000004 },
{ 0x00c0007a, 0x00000008 },
{ 0x0000e570, 0x00000004 },
{ 0x0000e571, 0x00000004 },
{ 0x0000e572, 0x0000000c },
{ 0x0000a000, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x0000e568, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00000084, 0x00000018 },
{ 0x000b0000, 0x00000004 },
{ 0x18c0e562, 0x00000004 },
{ 0x00000086, 0x00000008 },
{ 0x00c00085, 0x00000008 },
{ 0x000700e3, 0x00000004 },
{ 0x00000092, 0x00000038 },
{ 0x000ca094, 0x00000030 },
{ 0x080045bb, 0x00000004 },
{ 0x000c2095, 0x00000030 },
{ 0x0800e5bc, 0000000000 },
{ 0x0000e5bb, 0x00000004 },
{ 0x0000e5bc, 0000000000 },
{ 0x00120000, 0x0000000c },
{ 0x00120000, 0x00000004 },
{ 0x001b0002, 0x0000000c },
{ 0x0000a000, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e800, 0000000000 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e82e, 0000000000 },
{ 0x02cca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000ce1cc, 0x00000004 },
{ 0x050de1cd, 0x00000004 },
{ 0x00400000, 0x00000004 },
{ 0x000000a4, 0x00000018 },
{ 0x00c0a000, 0x00000004 },
{ 0x000000a1, 0x00000008 },
{ 0x000000a6, 0x00000020 },
{ 0x4200e000, 0000000000 },
{ 0x000000ad, 0x00000038 },
{ 0x000ca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00160000, 0x00000004 },
{ 0x700ce000, 0x00000004 },
{ 0x001400a9, 0x00000008 },
{ 0x4000e000, 0000000000 },
{ 0x02400000, 0x00000004 },
{ 0x400ee000, 0x00000004 },
{ 0x02400000, 0x00000004 },
{ 0x4000e000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x0240e51b, 0x00000004 },
{ 0x0080e50a, 0x00000005 },
{ 0x0080e50b, 0x00000005 },
{ 0x00220000, 0x00000004 },
{ 0x000700e3, 0x00000004 },
{ 0x000000c0, 0x00000038 },
{ 0x000c2095, 0x00000030 },
{ 0x0880e5bd, 0x00000005 },
{ 0x000c2094, 0x00000030 },
{ 0x0800e5bb, 0x00000005 },
{ 0x000c2095, 0x00000030 },
{ 0x0880e5bc, 0x00000005 },
{ 0x000000c3, 0x00000008 },
{ 0x0080e5bd, 0x00000005 },
{ 0x0000e5bb, 0x00000005 },
{ 0x0080e5bc, 0x00000005 },
{ 0x00210000, 0x00000004 },
{ 0x02800000, 0x00000004 },
{ 0x00c000c7, 0x00000018 },
{ 0x4180e000, 0x00000040 },
{ 0x000000c9, 0x00000024 },
{ 0x01000000, 0x0000000c },
{ 0x0100e51d, 0x0000000c },
{ 0x000045bb, 0x00000004 },
{ 0x000080c3, 0x00000008 },
{ 0x0000f3ce, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c053cf, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x0000f3d2, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c053d3, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x0000f39d, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c0539e, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x03c00830, 0x00000004 },
{ 0x4200e000, 0000000000 },
{ 0x0000a000, 0x00000004 },
{ 0x200045e0, 0x00000004 },
{ 0x0000e5e1, 0000000000 },
{ 0x00000001, 0000000000 },
{ 0x000700e0, 0x00000004 },
{ 0x0800e394, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x0000e8c4, 0x00000004 },
{ 0x0000e8c5, 0x00000004 },
{ 0x0000e8c6, 0x00000004 },
{ 0x0000e928, 0x00000004 },
{ 0x0000e929, 0x00000004 },
{ 0x0000e92a, 0x00000004 },
{ 0x000000e4, 0x00000008 },
{ 0x0000e928, 0x00000004 },
{ 0x0000e929, 0x00000004 },
{ 0x0000e92a, 0x00000004 },
{ 0x000000eb, 0x00000008 },
{ 0x02c02000, 0x00000004 },
{ 0x00060000, 0x00000004 },
{ 0x000000f3, 0x00000034 },
{ 0x000000f0, 0x00000008 },
{ 0x00008000, 0x00000004 },
{ 0xc000e000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x001d0018, 0x00000004 },
{ 0x001a0001, 0x00000004 },
{ 0x000000fb, 0x00000034 },
{ 0x0000004a, 0x00000008 },
{ 0x0500a04a, 0x00000008 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
};
static const u32_t R520_cp_microcode[][2]={
{ 0x4200e000, 0000000000 },
{ 0x4000e000, 0000000000 },
{ 0x00000099, 0x00000008 },
{ 0x0000009d, 0x00000008 },
{ 0x4a554b4a, 0000000000 },
{ 0x4a4a4467, 0000000000 },
{ 0x55526f75, 0000000000 },
{ 0x4a7e7d65, 0000000000 },
{ 0xe0dae6f6, 0000000000 },
{ 0x4ac54a4a, 0000000000 },
{ 0xc8828282, 0000000000 },
{ 0xbf4acfc1, 0000000000 },
{ 0x87b04ad5, 0000000000 },
{ 0xb5838383, 0000000000 },
{ 0x4a0f85ba, 0000000000 },
{ 0x000ca000, 0x00000004 },
{ 0x000d0012, 0x00000038 },
{ 0x0000e8b4, 0x00000004 },
{ 0x000d0014, 0x00000038 },
{ 0x0000e8b6, 0x00000004 },
{ 0x000d0016, 0x00000038 },
{ 0x0000e854, 0x00000004 },
{ 0x000d0018, 0x00000038 },
{ 0x0000e855, 0x00000004 },
{ 0x000d001a, 0x00000038 },
{ 0x0000e856, 0x00000004 },
{ 0x000d001c, 0x00000038 },
{ 0x0000e857, 0x00000004 },
{ 0x000d001e, 0x00000038 },
{ 0x0000e824, 0x00000004 },
{ 0x000d0020, 0x00000038 },
{ 0x0000e825, 0x00000004 },
{ 0x000d0022, 0x00000038 },
{ 0x0000e830, 0x00000004 },
{ 0x000d0024, 0x00000038 },
{ 0x0000f0c0, 0x00000004 },
{ 0x000d0026, 0x00000038 },
{ 0x0000f0c1, 0x00000004 },
{ 0x000d0028, 0x00000038 },
{ 0x0000e000, 0x00000004 },
{ 0x000d002a, 0x00000038 },
{ 0x0000e000, 0x00000004 },
{ 0x000d002c, 0x00000038 },
{ 0x0000e000, 0x00000004 },
{ 0x000d002e, 0x00000038 },
{ 0x0000e000, 0x00000004 },
{ 0x000d0030, 0x00000038 },
{ 0x0000e000, 0x00000004 },
{ 0x000d0032, 0x00000038 },
{ 0x0000f180, 0x00000004 },
{ 0x000d0034, 0x00000038 },
{ 0x0000f393, 0x00000004 },
{ 0x000d0036, 0x00000038 },
{ 0x0000f38a, 0x00000004 },
{ 0x000d0038, 0x00000038 },
{ 0x0000f38e, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00000043, 0x00000018 },
{ 0x00cce800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x08004800, 0x00000004 },
{ 0x0000003a, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x2000451d, 0x00000004 },
{ 0x0000e580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x08004580, 0x00000004 },
{ 0x000ce581, 0x00000004 },
{ 0x00000047, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x00032000, 0x00000004 },
{ 0x00022051, 0x00000028 },
{ 0x00000051, 0x00000024 },
{ 0x0800450f, 0x00000004 },
{ 0x0000a04b, 0x00000008 },
{ 0x0000e565, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x00000052, 0x00000008 },
{ 0x03cca5b4, 0x00000004 },
{ 0x05432000, 0x00000004 },
{ 0x00022000, 0x00000004 },
{ 0x4ccce05e, 0x00000030 },
{ 0x08274565, 0x00000004 },
{ 0x0000005e, 0x00000030 },
{ 0x08004564, 0x00000004 },
{ 0x0000e566, 0x00000004 },
{ 0x00000055, 0x00000008 },
{ 0x00802061, 0x00000010 },
{ 0x00202000, 0x00000004 },
{ 0x001b00ff, 0x00000004 },
{ 0x01000064, 0x00000010 },
{ 0x001f2000, 0x00000004 },
{ 0x001c00ff, 0x00000004 },
{ 0000000000, 0x0000000c },
{ 0x00000072, 0x00000030 },
{ 0x00000055, 0x00000008 },
{ 0x0000e576, 0x00000004 },
{ 0x0000e577, 0x00000004 },
{ 0x0000e50e, 0x00000004 },
{ 0x0000e50f, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00000069, 0x00000018 },
{ 0x00c0e5f9, 0x000000c2 },
{ 0x00000069, 0x00000008 },
{ 0x0014e50e, 0x00000004 },
{ 0x0040e50f, 0x00000004 },
{ 0x00c0006c, 0x00000008 },
{ 0x0000e570, 0x00000004 },
{ 0x0000e571, 0x00000004 },
{ 0x0000e572, 0x0000000c },
{ 0x0000a000, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x0000e568, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00000076, 0x00000018 },
{ 0x000b0000, 0x00000004 },
{ 0x18c0e562, 0x00000004 },
{ 0x00000078, 0x00000008 },
{ 0x00c00077, 0x00000008 },
{ 0x000700c7, 0x00000004 },
{ 0x00000080, 0x00000038 },
{ 0x0000e5bb, 0x00000004 },
{ 0x0000e5bc, 0000000000 },
{ 0x0000a000, 0x00000004 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e800, 0000000000 },
{ 0x0000e821, 0x00000004 },
{ 0x0000e82e, 0000000000 },
{ 0x02cca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000ce1cc, 0x00000004 },
{ 0x050de1cd, 0x00000004 },
{ 0x00400000, 0x00000004 },
{ 0x0000008f, 0x00000018 },
{ 0x00c0a000, 0x00000004 },
{ 0x0000008c, 0x00000008 },
{ 0x00000091, 0x00000020 },
{ 0x4200e000, 0000000000 },
{ 0x00000098, 0x00000038 },
{ 0x000ca000, 0x00000004 },
{ 0x00140000, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00160000, 0x00000004 },
{ 0x700ce000, 0x00000004 },
{ 0x00140094, 0x00000008 },
{ 0x4000e000, 0000000000 },
{ 0x02400000, 0x00000004 },
{ 0x400ee000, 0x00000004 },
{ 0x02400000, 0x00000004 },
{ 0x4000e000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x0240e51b, 0x00000004 },
{ 0x0080e50a, 0x00000005 },
{ 0x0080e50b, 0x00000005 },
{ 0x00220000, 0x00000004 },
{ 0x000700c7, 0x00000004 },
{ 0x000000a4, 0x00000038 },
{ 0x0080e5bd, 0x00000005 },
{ 0x0000e5bb, 0x00000005 },
{ 0x0080e5bc, 0x00000005 },
{ 0x00210000, 0x00000004 },
{ 0x02800000, 0x00000004 },
{ 0x00c000ab, 0x00000018 },
{ 0x4180e000, 0x00000040 },
{ 0x000000ad, 0x00000024 },
{ 0x01000000, 0x0000000c },
{ 0x0100e51d, 0x0000000c },
{ 0x000045bb, 0x00000004 },
{ 0x000080a7, 0x00000008 },
{ 0x0000f3ce, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c053cf, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x0000f3d2, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c053d3, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x0000f39d, 0x00000004 },
{ 0x0140a000, 0x00000004 },
{ 0x00cc2000, 0x00000004 },
{ 0x08c0539e, 0x00000040 },
{ 0x00008000, 0000000000 },
{ 0x03c00830, 0x00000004 },
{ 0x4200e000, 0000000000 },
{ 0x0000a000, 0x00000004 },
{ 0x200045e0, 0x00000004 },
{ 0x0000e5e1, 0000000000 },
{ 0x00000001, 0000000000 },
{ 0x000700c4, 0x00000004 },
{ 0x0800e394, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x0000e8c4, 0x00000004 },
{ 0x0000e8c5, 0x00000004 },
{ 0x0000e8c6, 0x00000004 },
{ 0x0000e928, 0x00000004 },
{ 0x0000e929, 0x00000004 },
{ 0x0000e92a, 0x00000004 },
{ 0x000000c8, 0x00000008 },
{ 0x0000e928, 0x00000004 },
{ 0x0000e929, 0x00000004 },
{ 0x0000e92a, 0x00000004 },
{ 0x000000cf, 0x00000008 },
{ 0xdeadbeef, 0000000000 },
{ 0x00000116, 0000000000 },
{ 0x000700d3, 0x00000004 },
{ 0x080050e7, 0x00000004 },
{ 0x000700d4, 0x00000004 },
{ 0x0800401c, 0x00000004 },
{ 0x0000e01d, 0000000000 },
{ 0x02c02000, 0x00000004 },
{ 0x00060000, 0x00000004 },
{ 0x000000de, 0x00000034 },
{ 0x000000db, 0x00000008 },
{ 0x00008000, 0x00000004 },
{ 0xc000e000, 0000000000 },
{ 0x0000e1cc, 0x00000004 },
{ 0x0500e1cd, 0x00000004 },
{ 0x000ca000, 0x00000004 },
{ 0x000000e5, 0x00000034 },
{ 0x000000e1, 0x00000008 },
{ 0x0000a000, 0000000000 },
{ 0x0019e1cc, 0x00000004 },
{ 0x001b0001, 0x00000004 },
{ 0x0500a000, 0x00000004 },
{ 0x080041cd, 0x00000004 },
{ 0x000ca000, 0x00000004 },
{ 0x000000fb, 0x00000034 },
{ 0x0000004a, 0x00000008 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0x000c2000, 0x00000004 },
{ 0x001d0018, 0x00000004 },
{ 0x001a0001, 0x00000004 },
{ 0x000000fb, 0x00000034 },
{ 0x0000004a, 0x00000008 },
{ 0x0500a04a, 0x00000008 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
{ 0000000000, 0000000000 },
};

4
programs/system/drivers/ati2d/pixmap.inc
View File

@ -54,7 +54,7 @@ int CreatePixmap(pixmap_t *io)
pixmap->pitch = pitch;
pixmap->mapped = mapped;
pixmap->pitch_offset = ((pitch/64)<<22)| (((u32_t)local+rhd.fbLocation)>>10);
pixmap->local = local;
pixmap->local = local+rhd.fbLocation;
dbgprintf("pixmap.pitch_offset: %x\n", pixmap->pitch_offset);
dbgprintf("width: %d height: %d\n",pixmap->width,pixmap->height );
@ -86,7 +86,7 @@ int DestroyPixmap( pixmap_t *io )
UnmapPages(pixmap->mapped, size);
UserFree(pixmap->mapped);
rhd_mem_free(&rhd,RHD_MEM_FB,pixmap->local);
rhd_mem_free(&rhd,RHD_MEM_FB,pixmap->local-rhd.fbLocation);
free(pixmap);
io->format = 0;

49
programs/system/drivers/ati2d/r500.inc
View File

@ -3,52 +3,6 @@
#include "r5xx_regs.h"
#define RADEON_BUS_CNTL 0x0030
# define RADEON_BUS_MASTER_DIS (1 << 6)
#define RADEON_SCRATCH_UMSK 0x0770
#define RADEON_SCRATCH_ADDR 0x0774
#define RADEON_CP_ME_RAM_ADDR 0x07d4
#define RADEON_CP_ME_RAM_RADDR 0x07d8
#define RADEON_CP_ME_RAM_DATAH 0x07dc
#define RADEON_CP_ME_RAM_DATAL 0x07e0
#define RADEON_AIC_CNTL 0x01d0
#define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
#define RADEON_CP_RB_BASE 0x0700
#define RADEON_CP_RB_CNTL 0x0704
# define RADEON_BUF_SWAP_32BIT (2 << 16)
# define RADEON_RB_NO_UPDATE (1 << 27)
#define RADEON_CP_RB_RPTR_ADDR 0x070c
#define RADEON_CP_RB_RPTR 0x0710
#define RADEON_CP_RB_WPTR 0x0714
#define RADEON_CP_RB_WPTR_DELAY 0x0718
# define RADEON_PRE_WRITE_TIMER_SHIFT 0
# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
#define RADEON_CP_IB_BASE 0x0738
#define RADEON_CP_CSQ_CNTL 0x0740
# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
#define RADEON_ISYNC_CNTL 0x1724
# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
#define R5XX_LOOP_COUNT 2000000
@ -210,7 +164,6 @@ void R5xx2DInit()
dbgprintf("gui_control %x \n", rhd.gui_control);
rhd.surface_cntl = 0;
// rhd.dst_pitch_offset = ((screenpitch / 64) << 22) | (rhd.fbLocation >> 10);
rhd.dst_pitch_offset = (((rhd.displayWidth * 4 / 64)<< 22) |
(rhd.fbLocation >> 10));
@ -221,7 +174,7 @@ void R5xx2DInit()
scr_pixmap.width = rhd.displayWidth;
scr_pixmap.height = rhd.displayHeight;
scr_pixmap.format = PICT_a8r8g8b8;
scr_pixmap.pitch = screenpitch;
scr_pixmap.pitch = rhd.displayWidth * 4 ;//screenpitch;
scr_pixmap.local = (void*)rhd.fbLocation;
scr_pixmap.pitch_offset = rhd.dst_pitch_offset;
scr_pixmap.mapped = (void*)0;

569
programs/system/drivers/ati2d/vs_prog.inc Normal file
View File

@ -0,0 +1,569 @@
typedef unsigned int u32_t;
typedef enum
{
VS_OUT_POS = 0,
VS_OUT_PSIZE,
VS_OUT_COL0,
VS_OUT_COL1,
VS_OUT_COL2,
VS_OUT_COL3,
VS_OUT_TEX0,
VS_OUT_TEX1,
VS_OUT_TEX2,
VS_OUT_TEX3,
VS_OUT_TEX4,
VS_OUT_TEX5,
VS_OUT_TEX6,
VS_OUT_TEX7,
VS_OUT_FOG,
VS_OUT_MAX = 0xFFFFFFFF
}v_out_t;
#if 0
vs_1_1
dcl_position v0
dcl_color v1
dcl_color1 v2
dcl_fog v3
dcl_psize v4
dcl_texcoord v5
dcl_texcoord1 v6
mov oPos, v0
mov oD0, v1
mov oD1, v2
mov oFog, v3.x
mov oPts, v4.x
mov oT0, v5
mov oT1, v6
#endif
const u32_t vs11[] =
{
0xfffe0101, 0x0000001f, 0x80000000, 0x900f0000, 0x0000001f, 0x8000000a,
0x900f0001, 0x0000001f, 0x8001000a, 0x900f0002, 0x0000001f, 0x8000000b,
0x900f0003, 0x0000001f, 0x80000004, 0x900f0004, 0x0000001f, 0x80000005,
0x900f0005, 0x0000001f, 0x80010005, 0x900f0006, 0x00000001, 0xc00f0000,
0x90e40000, 0x00000001, 0xd00f0000, 0x90e40001, 0x00000001, 0xd00f0001,
0x90e40002, 0x00000001, 0xc00f0001, 0x90000003, 0x00000001, 0xc00f0002,
0x90000004, 0x00000001, 0xe00f0000, 0x90e40005, 0x00000001, 0xe00f0001,
0x90e40006, 0x0000ffff
};
char *sz_vs_command[] =
{
"nop",
"mov",
"add",
"sub",
"mad",
"mul",
"rcp",
"rsq",
"dp3",
"dp4",
"min",
"max",
"slt",
"sge",
"exp",
"log",
"lit",
"dst",
"lrp",
"frc",
"m4x4",
"m4x3",
"m3x4",
"m3x3",
"m3x2",
};
/*
char *sz_ps_command[] =
{
texcoord
texkill
tex
texbem
texbeml
texreg2ar
texreg2gb
texm3x2pad
texm3x3tex
texm3x3pad
texm3x3tex
texm3x3diff
texm3x3spec
texm3x3vspec
expp
logp
cnd
def
texreg2rgb
texdp3tex
texm3x2depth
texdp3
texm3x3
texdepth
cmp
bem
}
*/
char *szusage[]=
{
"position",
"blendweight",
"blendindices",
"normal",
"psize",
"texcoord",
"tangent",
"binormal",
"tessfactor",
"positiont",
"color",
"fog",
"depth",
"sample"
};
char *sztype[]=
{
"r",
"v",
"c"
"a",
"t",
"rasout",
"attrout",
"texcrdout",
"output",
"constint",
"colorout",
"depthout",
"sampler",
"const2",
"const3",
"const4",
"constbool",
"loop",
"tempfloat16",
"misctype",
"label",
"predicate"
};
typedef struct
{
u32_t minor: 8;
u32_t major: 8;
u32_t type :16;
}version_t;
typedef struct
{
u32_t type:5;
u32_t rsv :11;
u32_t ind :4;
u32_t rsv2:11;
u32_t sign:1;
}usage_t;
typedef struct
{
u32_t ind :11;
u32_t typeh :2;
u32_t rsv :3;
u32_t wr :4;
u32_t mod :4;
u32_t scale :4;
u32_t typel :3;
u32_t sign :1;
}dst_t;
typedef struct
{
u32_t ind :11;
u32_t rsv :5;
u32_t swzl :8;
u32_t mod :4;
u32_t typel :3;
u32_t sign :1;
}src_t;
int parse_vs();
int parse_mov();
int parse_dcl();
int parse_vs(const u32_t *stream);
static void assign_outputs();
int translate_vs(const u32_t *stream);
u32_t vs_out_written;
u32_t inp_mask;
u32_t vs_outputs[16];
int main()
{
version_t *ver;
ver = (version_t*)vs11;
if(ver->type == 0xFFFE)
{
printf("vs_%d_%d\n\n",ver->major,ver->minor);
if( parse_vs(vs11+1) )
translate_vs(vs11+1);
};
return 0;
};
static char txt_swzl[4] = {'x','y','z','w'};
static char *txt_mod[2] = { "","_sat"};
int parse_vs(const u32_t *stream)
{
dst_t *dst;
src_t *src;
u32_t swzl;
u32_t wr;
char szswzl[5];
char szwm[5];
int i,j;
while(1)
{
op_type_t instr = *stream++ & 0xFFFF;
switch( instr )
{
case D3DSIO_MOV:
dst = (dst_t*)stream++;
src = (src_t*)stream++;
swzl = src->swzl;
wr = dst->wr;
for(i=0,j=0; i < 4; i++)
{
szswzl[i] = txt_swzl[swzl&3];
swzl>>=2;
if(wr & (1<<i))
szwm[j++] = txt_swzl[i];
};
szswzl[4] = 0;
szwm[j] = 0;
switch(dst->typel)
{
case 4: // Rasterizer Register File
if(dst->ind == 0)
vs_out_written |= (1 << VS_OUT_POS);
else if (dst->ind == 1)
vs_out_written |= (1 << VS_OUT_FOG);
else if (dst->ind == 2)
vs_out_written |= (1 << VS_OUT_PSIZE);
else
printf("invalid raster register %d",dst->ind);
break;
case 5: // Attribute Output Register File
if(dst->ind == 0)
vs_out_written |= (1 << VS_OUT_COL0);
else if (dst->ind == 1)
vs_out_written |= (1 << VS_OUT_COL1);
else
printf("invalid attribute register %d",dst->ind);
break;
case 6: // Texture Coordinate Output Register File
if(dst->ind < 8)
vs_out_written |= (1 << (VS_OUT_TEX0+dst->ind));
else
printf("invalid texture register %d",dst->ind);
};
printf("%s%s %s%d.%s,\t %s%d.%s\n",sz_vs_command[instr],txt_mod[dst->mod],
sztype[dst->typel],dst->ind,szwm,
sztype[src->typel],src->ind,szswzl);
break;
case D3DSIO_DCL:
parse_dcl(stream);
stream+=2;
break;
case 0xFFFF:
return 1;
default:
return 0;
};
};
};
int parse_dcl(const u32_t *stream)
{
usage_t *usage;
dst_t *dst;
int dsttype;
char szwm[5];
int i;
u32_t wr;
usage = (usage_t*)stream++;
dst = (dst_t*)stream++;
dsttype = (dst->typeh << 4) | dst->typel;
wr = dst->wr;
for(i=0; wr; i++, wr>>=1)
{
if(wr & 1)
szwm[i] = txt_swzl[i];
};
szwm[i] = 0;
printf("dcl_%s%d \t\t %s%d.%s\n",szusage[usage->type],usage->ind,
sztype[dsttype],dst->ind, szwm);
return 2;
}
int translate_dcl(const u32_t *stream);
int translate_mov(const u32_t *stream);
int translate_vs(const u32_t *stream)
{
assign_outputs();
while(1)
{
op_type_t instr = *stream++ & 0xFFFF;
switch( instr )
{
case D3DSIO_MOV:
translate_mov(stream);
stream+=2;
break;
case D3DSIO_DCL:
translate_dcl(stream);
stream+=2;
break;
case 0xFFFF:
return 1;
default:
return 0;
};
};
};
int translate_dcl(const u32_t *stream)
{
return 1;
};
u32_t inst[4];
#include "r300_vertprog.h"
/**
* Swizzle indexes.
* Do not change!
*/
/*@{*/
#define SWIZZLE_X 0
#define SWIZZLE_Y 1
#define SWIZZLE_Z 2
#define SWIZZLE_W 3
#define SWIZZLE_ZERO 4 /**< For SWZ instruction only */
#define SWIZZLE_ONE 5 /**< For SWZ instruction only */
#define SWIZZLE_NIL 7 /**< used during shader code gen (undefined value) */
/*@}*/
#define __CONST(x, y) \
(PVS_SRC_OPERAND(t_src_index(vp, &src[x]), \
t_swizzle(y), \
t_swizzle(y), \
t_swizzle(y), \
t_swizzle(y), \
t_src_class(src[x].File), \
VSF_FLAG_NONE) | (src[x].RelAddr << 4))
static unsigned long t_swizzle(u32_t swizzle)
{
/* this is in fact a NOP as the Mesa SWIZZLE_* are all identical to VSF_IN_COMPONENT_* */
return swizzle;
}
static unsigned long t_dst_mask(u32_t mask)
{
/* WRITEMASK_* is equivalent to VSF_FLAG_* */
return mask & VSF_FLAG_ALL;
}
static unsigned long t_dst_class(int file)
{
switch (file) {
case 0: //D3DSPR_TEMP
return PVS_DST_REG_TEMPORARY;
case 3: //D3DSPR_ADDR
return PVS_DST_REG_A0;
case 4: //D3DSPR_RASTOUT
case 5:
case 6: //D3DSPR_TEXCRDOUT
return PVS_DST_REG_OUT;
/*
case PROGRAM_INPUT:
case PROGRAM_LOCAL_PARAM:
case PROGRAM_ENV_PARAM:
case PROGRAM_NAMED_PARAM:
case PROGRAM_STATE_VAR:
case PROGRAM_WRITE_ONLY:
case PROGRAM_ADDRESS:
*/
default:
printf("problem in %s", __FUNCTION__);
return -1;
}
}
static unsigned long t_dst_index(dst_t *dst)
{
switch(dst->typel)
{
case 4:
if(dst->ind == 0)
return vs_outputs[VS_OUT_POS];
else if (dst->ind == 1)
return vs_outputs[VS_OUT_FOG];
else if (dst->ind == 2)
return vs_outputs[VS_OUT_PSIZE];
break;
case 5:
if(dst->ind == 0)
return vs_outputs[VS_OUT_COL0];
else if (dst->ind == 1)
return vs_outputs[VS_OUT_COL1];
case 6:
return vs_outputs[VS_OUT_TEX0+dst->ind];
default:
return dst->ind;
}
}
static void assign_outputs()
{
int i;
int cur_reg = 0;
for (i = 0; i < 16; i++)
vs_outputs[i] = -1;
// assert(vs_out_written & (1 << VS_OUT_POS));
if (vs_out_written & (1 << VS_OUT_POS)) {
vs_outputs[VS_OUT_POS] = cur_reg++;
}
if (vs_out_written & (1 << VS_OUT_PSIZE)) {
vs_outputs[VS_OUT_PSIZE] = cur_reg++;
}
if (vs_out_written & (1 << VS_OUT_COL0)) {
vs_outputs[VS_OUT_COL0] = cur_reg++;
}
if (vs_out_written & (1 << VS_OUT_COL1)) {
vs_outputs[VS_OUT_COL1] = vs_outputs[VS_OUT_COL0] + 1; // ???
cur_reg = vs_outputs[VS_OUT_COL1] + 1;
}
#if 0
if (vp->key.OutputsWritten & (1 << VERT_RESULT_FOGC)) { //fog must be in
vp->outputs[VERT_RESULT_FOGC] = cur_reg++; //one of the color regs
}
#endif
for (i = VS_OUT_TEX0; i <= VS_OUT_TEX7; i++) {
if (vs_out_written & (1 << i)) {
vs_outputs[i] = cur_reg++;
}
}
}
int translate_mov(const u32_t *stream)
{
dst_t *dst = (dst_t*)stream++;
src_t *src = (src_t*)stream++;
int swzl = src->swzl;
int wr = dst->wr;
inst[0] = PVS_OP_DST_OPERAND(VE_ADD,
0,
0,
t_dst_index(dst),
(dst->wr),
t_dst_class(dst->typel));
//inst[1] = t_src(vp, &src[0]);
// inst[2] = __CONST(0, SWIZZLE_ZERO);
//inst[3] = __CONST(0, SWIZZLE_ZERO);
printf("inst_0 %x\n", inst[0]);
return 1;
}
/*
static GLuint *r300TranslateOpcodeMOV(struct r300_vertex_program *vp,
struct prog_instruction *vpi,
GLuint * inst,
struct prog_src_register src[3])
{
//ADD RESULT 1.X Y Z W PARAM 0{} {X Y Z W} PARAM 0{} {ZERO ZERO ZERO ZERO}
inst[0] = PVS_OP_DST_OPERAND(VE_ADD,
GL_FALSE,
GL_FALSE,
t_dst_index(vp, &vpi->DstReg),
t_dst_mask(vpi->DstReg.WriteMask),
t_dst_class(vpi->DstReg.File));
inst[1] = t_src(vp, &src[0]);
inst[2] = __CONST(0, SWIZZLE_ZERO);
inst[3] = __CONST(0, SWIZZLE_ZERO);
return inst;
}
*/