2011-12-26 23:41:30 +04:00
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/*
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* Copyright 2006 Dave Airlie <airlied@linux.ie>
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* Copyright © 2006-2009 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Jesse Barnes <jesse.barnes@intel.com>
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*/
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#include <linux/i2c.h>
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#include <linux/slab.h>
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2012-11-13 01:22:52 +04:00
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#include <linux/delay.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_edid.h>
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2011-12-26 23:41:30 +04:00
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#include "intel_drv.h"
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2012-11-13 01:22:52 +04:00
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#include <drm/i915_drm.h>
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2011-12-26 23:41:30 +04:00
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#include "i915_drv.h"
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2013-02-13 12:23:54 +04:00
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static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
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{
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return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
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}
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2012-11-13 01:22:52 +04:00
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static void
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assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
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{
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2013-02-13 12:23:54 +04:00
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struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
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2012-11-13 01:22:52 +04:00
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t enabled_bits;
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2013-04-25 00:04:21 +04:00
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enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
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2011-12-26 23:41:30 +04:00
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2013-07-02 20:03:52 +04:00
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WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
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2012-11-13 01:22:52 +04:00
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"HDMI port enabled, expecting disabled\n");
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}
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struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
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2011-12-26 23:41:30 +04:00
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{
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2013-02-13 12:23:54 +04:00
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struct intel_digital_port *intel_dig_port =
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container_of(encoder, struct intel_digital_port, base.base);
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return &intel_dig_port->hdmi;
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2011-12-26 23:41:30 +04:00
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}
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static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
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{
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2013-02-13 12:23:54 +04:00
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return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
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2011-12-26 23:41:30 +04:00
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}
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void intel_dip_infoframe_csum(struct dip_infoframe *frame)
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{
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uint8_t *data = (uint8_t *)frame;
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uint8_t sum = 0;
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unsigned i;
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frame->checksum = 0;
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frame->ecc = 0;
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2012-02-03 10:54:20 +04:00
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for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
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2011-12-26 23:41:30 +04:00
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sum += data[i];
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frame->checksum = 0x100 - sum;
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}
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2012-11-13 01:22:52 +04:00
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static u32 g4x_infoframe_index(struct dip_infoframe *frame)
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2011-12-26 23:41:30 +04:00
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{
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switch (frame->type) {
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case DIP_TYPE_AVI:
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2012-11-13 01:22:52 +04:00
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return VIDEO_DIP_SELECT_AVI;
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2011-12-26 23:41:30 +04:00
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case DIP_TYPE_SPD:
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2012-11-13 01:22:52 +04:00
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return VIDEO_DIP_SELECT_SPD;
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2011-12-26 23:41:30 +04:00
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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2012-11-13 01:22:52 +04:00
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return 0;
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2011-12-26 23:41:30 +04:00
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}
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}
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2012-11-13 01:22:52 +04:00
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static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
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2011-12-26 23:41:30 +04:00
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{
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2012-11-13 01:22:52 +04:00
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switch (frame->type) {
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case DIP_TYPE_AVI:
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return VIDEO_DIP_ENABLE_AVI;
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case DIP_TYPE_SPD:
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return VIDEO_DIP_ENABLE_SPD;
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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return 0;
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}
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}
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2011-12-26 23:41:30 +04:00
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2012-11-13 01:22:52 +04:00
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static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
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{
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2011-12-26 23:41:30 +04:00
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switch (frame->type) {
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case DIP_TYPE_AVI:
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2012-11-13 01:22:52 +04:00
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return VIDEO_DIP_ENABLE_AVI_HSW;
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2011-12-26 23:41:30 +04:00
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case DIP_TYPE_SPD:
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2012-11-13 01:22:52 +04:00
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return VIDEO_DIP_ENABLE_SPD_HSW;
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2011-12-26 23:41:30 +04:00
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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2012-11-13 01:22:52 +04:00
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return 0;
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2011-12-26 23:41:30 +04:00
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}
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2012-11-13 01:22:52 +04:00
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}
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2011-12-26 23:41:30 +04:00
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2013-07-02 20:03:52 +04:00
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static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame,
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enum transcoder cpu_transcoder)
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2012-11-13 01:22:52 +04:00
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{
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switch (frame->type) {
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case DIP_TYPE_AVI:
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2013-07-02 20:03:52 +04:00
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return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
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2012-11-13 01:22:52 +04:00
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case DIP_TYPE_SPD:
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2013-07-02 20:03:52 +04:00
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return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
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2012-11-13 01:22:52 +04:00
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default:
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DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
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return 0;
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}
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2011-12-26 23:41:30 +04:00
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}
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2012-11-13 01:22:52 +04:00
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static void g4x_write_infoframe(struct drm_encoder *encoder,
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2011-12-26 23:41:30 +04:00
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struct dip_infoframe *frame)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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2012-11-13 01:22:52 +04:00
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u32 val = I915_READ(VIDEO_DIP_CTL);
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2011-12-26 23:41:30 +04:00
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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2012-11-13 01:22:52 +04:00
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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2011-12-26 23:41:30 +04:00
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2012-11-13 01:22:52 +04:00
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(frame);
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2011-12-26 23:41:30 +04:00
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2012-11-13 01:22:52 +04:00
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val &= ~g4x_infoframe_enable(frame);
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2011-12-26 23:41:30 +04:00
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2012-11-13 01:22:52 +04:00
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I915_WRITE(VIDEO_DIP_CTL, val);
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2011-12-26 23:41:30 +04:00
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2012-11-13 01:22:52 +04:00
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mmiowb();
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2011-12-26 23:41:30 +04:00
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for (i = 0; i < len; i += 4) {
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I915_WRITE(VIDEO_DIP_DATA, *data);
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data++;
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}
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2012-11-13 01:22:52 +04:00
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/* Write every possible data byte to force correct ECC calculation. */
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for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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I915_WRITE(VIDEO_DIP_DATA, 0);
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mmiowb();
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2011-12-26 23:41:30 +04:00
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2012-11-13 01:22:52 +04:00
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val |= g4x_infoframe_enable(frame);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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2011-12-26 23:41:30 +04:00
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2012-11-13 01:22:52 +04:00
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I915_WRITE(VIDEO_DIP_CTL, val);
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POSTING_READ(VIDEO_DIP_CTL);
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2011-12-26 23:41:30 +04:00
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}
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2012-11-13 01:22:52 +04:00
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static void ibx_write_infoframe(struct drm_encoder *encoder,
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2011-12-26 23:41:30 +04:00
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struct dip_infoframe *frame)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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2012-11-13 01:22:52 +04:00
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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2011-12-26 23:41:30 +04:00
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int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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2012-11-13 01:22:52 +04:00
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u32 val = I915_READ(reg);
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(frame);
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val &= ~g4x_infoframe_enable(frame);
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I915_WRITE(reg, val);
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mmiowb();
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for (i = 0; i < len; i += 4) {
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
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data++;
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}
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/* Write every possible data byte to force correct ECC calculation. */
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for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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mmiowb();
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val |= g4x_infoframe_enable(frame);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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2011-12-26 23:41:30 +04:00
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2012-11-13 01:22:52 +04:00
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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}
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static void cpt_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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u32 val = I915_READ(reg);
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2011-12-26 23:41:30 +04:00
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2012-11-13 01:22:52 +04:00
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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2011-12-26 23:41:30 +04:00
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2012-02-03 10:54:20 +04:00
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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2012-11-13 01:22:52 +04:00
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val |= g4x_infoframe_index(frame);
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/* The DIP control register spec says that we need to update the AVI
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* infoframe without clearing its enable bit */
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if (frame->type != DIP_TYPE_AVI)
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val &= ~g4x_infoframe_enable(frame);
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2011-12-26 23:41:30 +04:00
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2012-11-13 01:22:52 +04:00
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I915_WRITE(reg, val);
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2011-12-26 23:41:30 +04:00
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2012-11-13 01:22:52 +04:00
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mmiowb();
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2011-12-26 23:41:30 +04:00
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for (i = 0; i < len; i += 4) {
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
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data++;
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}
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2012-11-13 01:22:52 +04:00
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/* Write every possible data byte to force correct ECC calculation. */
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for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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mmiowb();
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2011-12-26 23:41:30 +04:00
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2012-11-13 01:22:52 +04:00
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val |= g4x_infoframe_enable(frame);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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2011-12-26 23:41:30 +04:00
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2012-11-13 01:22:52 +04:00
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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2011-12-26 23:41:30 +04:00
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}
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2012-11-13 01:22:52 +04:00
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static void vlv_write_infoframe(struct drm_encoder *encoder,
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struct dip_infoframe *frame)
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{
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uint32_t *data = (uint32_t *)frame;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
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unsigned i, len = DIP_HEADER_SIZE + frame->len;
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u32 val = I915_READ(reg);
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WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
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val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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val |= g4x_infoframe_index(frame);
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val &= ~g4x_infoframe_enable(frame);
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I915_WRITE(reg, val);
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mmiowb();
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for (i = 0; i < len; i += 4) {
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I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
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data++;
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}
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/* Write every possible data byte to force correct ECC calculation. */
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for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
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I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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mmiowb();
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val |= g4x_infoframe_enable(frame);
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val &= ~VIDEO_DIP_FREQ_MASK;
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val |= VIDEO_DIP_FREQ_VSYNC;
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I915_WRITE(reg, val);
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POSTING_READ(reg);
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}
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|
|
|
|
|
|
static void hsw_write_infoframe(struct drm_encoder *encoder,
|
2011-12-26 23:41:30 +04:00
|
|
|
struct dip_infoframe *frame)
|
|
|
|
{
|
2012-11-13 01:22:52 +04:00
|
|
|
uint32_t *data = (uint32_t *)frame;
|
|
|
|
struct drm_device *dev = encoder->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
2013-07-02 20:03:52 +04:00
|
|
|
u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
|
|
|
|
u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->config.cpu_transcoder);
|
2012-11-13 01:22:52 +04:00
|
|
|
unsigned int i, len = DIP_HEADER_SIZE + frame->len;
|
|
|
|
u32 val = I915_READ(ctl_reg);
|
2011-12-26 23:41:30 +04:00
|
|
|
|
2012-11-13 01:22:52 +04:00
|
|
|
if (data_reg == 0)
|
2011-12-26 23:41:30 +04:00
|
|
|
return;
|
|
|
|
|
2012-11-13 01:22:52 +04:00
|
|
|
val &= ~hsw_infoframe_enable(frame);
|
|
|
|
I915_WRITE(ctl_reg, val);
|
|
|
|
|
|
|
|
mmiowb();
|
|
|
|
for (i = 0; i < len; i += 4) {
|
|
|
|
I915_WRITE(data_reg + i, *data);
|
|
|
|
data++;
|
|
|
|
}
|
|
|
|
/* Write every possible data byte to force correct ECC calculation. */
|
|
|
|
for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
|
|
|
|
I915_WRITE(data_reg + i, 0);
|
|
|
|
mmiowb();
|
|
|
|
|
|
|
|
val |= hsw_infoframe_enable(frame);
|
|
|
|
I915_WRITE(ctl_reg, val);
|
|
|
|
POSTING_READ(ctl_reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_set_infoframe(struct drm_encoder *encoder,
|
|
|
|
struct dip_infoframe *frame)
|
|
|
|
{
|
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
|
|
|
|
2011-12-26 23:41:30 +04:00
|
|
|
intel_dip_infoframe_csum(frame);
|
|
|
|
intel_hdmi->write_infoframe(encoder, frame);
|
|
|
|
}
|
|
|
|
|
2012-11-13 01:22:52 +04:00
|
|
|
static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
|
|
|
|
struct drm_display_mode *adjusted_mode)
|
2011-12-26 23:41:30 +04:00
|
|
|
{
|
2013-04-25 00:04:21 +04:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
2013-07-02 20:03:52 +04:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
2011-12-26 23:41:30 +04:00
|
|
|
struct dip_infoframe avi_if = {
|
|
|
|
.type = DIP_TYPE_AVI,
|
|
|
|
.ver = DIP_VERSION_AVI,
|
|
|
|
.len = DIP_LEN_AVI,
|
|
|
|
};
|
|
|
|
|
2012-11-13 01:22:52 +04:00
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
|
|
|
|
avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
|
|
|
|
|
2013-04-25 00:04:21 +04:00
|
|
|
if (intel_hdmi->rgb_quant_range_selectable) {
|
2013-07-02 20:03:52 +04:00
|
|
|
if (intel_crtc->config.limited_color_range)
|
2013-04-25 00:04:21 +04:00
|
|
|
avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
|
|
|
|
else
|
|
|
|
avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
|
2013-02-13 12:23:54 +04:00
|
|
|
|
2011-12-26 23:41:30 +04:00
|
|
|
intel_set_infoframe(encoder, &avi_if);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct dip_infoframe spd_if;
|
|
|
|
|
|
|
|
memset(&spd_if, 0, sizeof(spd_if));
|
|
|
|
spd_if.type = DIP_TYPE_SPD;
|
|
|
|
spd_if.ver = DIP_VERSION_SPD;
|
|
|
|
spd_if.len = DIP_LEN_SPD;
|
|
|
|
strcpy(spd_if.body.spd.vn, "Intel");
|
|
|
|
strcpy(spd_if.body.spd.pd, "Integrated gfx");
|
|
|
|
spd_if.body.spd.sdi = DIP_SPD_PC;
|
|
|
|
|
|
|
|
intel_set_infoframe(encoder, &spd_if);
|
|
|
|
}
|
|
|
|
|
2012-11-13 01:22:52 +04:00
|
|
|
static void g4x_set_infoframes(struct drm_encoder *encoder,
|
|
|
|
struct drm_display_mode *adjusted_mode)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
|
2013-04-25 00:04:21 +04:00
|
|
|
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
|
|
|
|
struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
|
2012-11-13 01:22:52 +04:00
|
|
|
u32 reg = VIDEO_DIP_CTL;
|
|
|
|
u32 val = I915_READ(reg);
|
|
|
|
u32 port;
|
|
|
|
|
|
|
|
assert_hdmi_port_disabled(intel_hdmi);
|
|
|
|
|
|
|
|
/* If the registers were not initialized yet, they might be zeroes,
|
|
|
|
* which means we're selecting the AVI DIP and we're setting its
|
|
|
|
* frequency to once. This seems to really confuse the HW and make
|
|
|
|
* things stop working (the register spec says the AVI always needs to
|
|
|
|
* be sent every VSync). So here we avoid writing to the register more
|
|
|
|
* than we need and also explicitly select the AVI DIP and explicitly
|
|
|
|
* set its frequency to every VSync. Avoiding to write it twice seems to
|
|
|
|
* be enough to solve the problem, but being defensive shouldn't hurt us
|
|
|
|
* either. */
|
|
|
|
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
|
|
|
|
|
|
|
|
if (!intel_hdmi->has_hdmi_sink) {
|
|
|
|
if (!(val & VIDEO_DIP_ENABLE))
|
|
|
|
return;
|
|
|
|
val &= ~VIDEO_DIP_ENABLE;
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
POSTING_READ(reg);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-04-25 00:04:21 +04:00
|
|
|
switch (intel_dig_port->port) {
|
|
|
|
case PORT_B:
|
2012-11-13 01:22:52 +04:00
|
|
|
port = VIDEO_DIP_PORT_B;
|
|
|
|
break;
|
2013-04-25 00:04:21 +04:00
|
|
|
case PORT_C:
|
2012-11-13 01:22:52 +04:00
|
|
|
port = VIDEO_DIP_PORT_C;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (port != (val & VIDEO_DIP_PORT_MASK)) {
|
|
|
|
if (val & VIDEO_DIP_ENABLE) {
|
|
|
|
val &= ~VIDEO_DIP_ENABLE;
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
POSTING_READ(reg);
|
|
|
|
}
|
|
|
|
val &= ~VIDEO_DIP_PORT_MASK;
|
|
|
|
val |= port;
|
|
|
|
}
|
|
|
|
|
|
|
|
val |= VIDEO_DIP_ENABLE;
|
|
|
|
val &= ~VIDEO_DIP_ENABLE_VENDOR;
|
|
|
|
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
POSTING_READ(reg);
|
|
|
|
|
|
|
|
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
|
|
|
|
intel_hdmi_set_spd_infoframe(encoder);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ibx_set_infoframes(struct drm_encoder *encoder,
|
|
|
|
struct drm_display_mode *adjusted_mode)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
2013-04-25 00:04:21 +04:00
|
|
|
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
|
|
|
|
struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
|
2012-11-13 01:22:52 +04:00
|
|
|
u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
|
|
|
|
u32 val = I915_READ(reg);
|
|
|
|
u32 port;
|
|
|
|
|
|
|
|
assert_hdmi_port_disabled(intel_hdmi);
|
|
|
|
|
|
|
|
/* See the big comment in g4x_set_infoframes() */
|
|
|
|
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
|
|
|
|
|
|
|
|
if (!intel_hdmi->has_hdmi_sink) {
|
|
|
|
if (!(val & VIDEO_DIP_ENABLE))
|
|
|
|
return;
|
|
|
|
val &= ~VIDEO_DIP_ENABLE;
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
POSTING_READ(reg);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2013-04-25 00:04:21 +04:00
|
|
|
switch (intel_dig_port->port) {
|
|
|
|
case PORT_B:
|
2012-11-13 01:22:52 +04:00
|
|
|
port = VIDEO_DIP_PORT_B;
|
|
|
|
break;
|
2013-04-25 00:04:21 +04:00
|
|
|
case PORT_C:
|
2012-11-13 01:22:52 +04:00
|
|
|
port = VIDEO_DIP_PORT_C;
|
|
|
|
break;
|
2013-04-25 00:04:21 +04:00
|
|
|
case PORT_D:
|
2012-11-13 01:22:52 +04:00
|
|
|
port = VIDEO_DIP_PORT_D;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (port != (val & VIDEO_DIP_PORT_MASK)) {
|
|
|
|
if (val & VIDEO_DIP_ENABLE) {
|
|
|
|
val &= ~VIDEO_DIP_ENABLE;
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
POSTING_READ(reg);
|
|
|
|
}
|
|
|
|
val &= ~VIDEO_DIP_PORT_MASK;
|
|
|
|
val |= port;
|
|
|
|
}
|
|
|
|
|
|
|
|
val |= VIDEO_DIP_ENABLE;
|
|
|
|
val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
|
|
|
VIDEO_DIP_ENABLE_GCP);
|
|
|
|
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
POSTING_READ(reg);
|
|
|
|
|
|
|
|
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
|
|
|
|
intel_hdmi_set_spd_infoframe(encoder);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void cpt_set_infoframes(struct drm_encoder *encoder,
|
|
|
|
struct drm_display_mode *adjusted_mode)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
|
|
|
u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
|
|
|
|
u32 val = I915_READ(reg);
|
|
|
|
|
|
|
|
assert_hdmi_port_disabled(intel_hdmi);
|
|
|
|
|
|
|
|
/* See the big comment in g4x_set_infoframes() */
|
|
|
|
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
|
|
|
|
|
|
|
|
if (!intel_hdmi->has_hdmi_sink) {
|
|
|
|
if (!(val & VIDEO_DIP_ENABLE))
|
|
|
|
return;
|
|
|
|
val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
POSTING_READ(reg);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set both together, unset both together: see the spec. */
|
|
|
|
val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
|
|
|
|
val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
|
|
|
VIDEO_DIP_ENABLE_GCP);
|
|
|
|
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
POSTING_READ(reg);
|
|
|
|
|
|
|
|
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
|
|
|
|
intel_hdmi_set_spd_infoframe(encoder);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vlv_set_infoframes(struct drm_encoder *encoder,
|
|
|
|
struct drm_display_mode *adjusted_mode)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
|
|
|
u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
|
|
|
|
u32 val = I915_READ(reg);
|
|
|
|
|
|
|
|
assert_hdmi_port_disabled(intel_hdmi);
|
|
|
|
|
|
|
|
/* See the big comment in g4x_set_infoframes() */
|
|
|
|
val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
|
|
|
|
|
|
|
|
if (!intel_hdmi->has_hdmi_sink) {
|
|
|
|
if (!(val & VIDEO_DIP_ENABLE))
|
|
|
|
return;
|
|
|
|
val &= ~VIDEO_DIP_ENABLE;
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
POSTING_READ(reg);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
val |= VIDEO_DIP_ENABLE;
|
|
|
|
val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
|
|
|
|
VIDEO_DIP_ENABLE_GCP);
|
|
|
|
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
POSTING_READ(reg);
|
|
|
|
|
|
|
|
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
|
|
|
|
intel_hdmi_set_spd_infoframe(encoder);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hsw_set_infoframes(struct drm_encoder *encoder,
|
|
|
|
struct drm_display_mode *adjusted_mode)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = encoder->dev->dev_private;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
2013-07-02 20:03:52 +04:00
|
|
|
u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
|
2012-11-13 01:22:52 +04:00
|
|
|
u32 val = I915_READ(reg);
|
|
|
|
|
|
|
|
assert_hdmi_port_disabled(intel_hdmi);
|
|
|
|
|
|
|
|
if (!intel_hdmi->has_hdmi_sink) {
|
|
|
|
I915_WRITE(reg, 0);
|
|
|
|
POSTING_READ(reg);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
|
|
|
|
VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
|
|
|
|
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
POSTING_READ(reg);
|
|
|
|
|
|
|
|
intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
|
|
|
|
intel_hdmi_set_spd_infoframe(encoder);
|
|
|
|
}
|
|
|
|
|
2011-12-26 23:41:30 +04:00
|
|
|
static void intel_hdmi_mode_set(struct drm_encoder *encoder,
|
|
|
|
struct drm_display_mode *mode,
|
|
|
|
struct drm_display_mode *adjusted_mode)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = encoder->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-11-13 01:22:52 +04:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
|
2011-12-26 23:41:30 +04:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
|
2013-07-02 20:03:52 +04:00
|
|
|
u32 hdmi_val;
|
2011-12-26 23:41:30 +04:00
|
|
|
|
2013-07-02 20:03:52 +04:00
|
|
|
hdmi_val = SDVO_ENCODING_HDMI;
|
|
|
|
if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
|
|
|
|
hdmi_val |= intel_hdmi->color_range;
|
2011-12-26 23:41:30 +04:00
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
|
2013-07-02 20:03:52 +04:00
|
|
|
hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
|
2011-12-26 23:41:30 +04:00
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
|
2013-07-02 20:03:52 +04:00
|
|
|
hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
|
2011-12-26 23:41:30 +04:00
|
|
|
|
2013-07-02 20:03:52 +04:00
|
|
|
if (intel_crtc->config.pipe_bpp > 24)
|
|
|
|
hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
|
2011-12-26 23:41:30 +04:00
|
|
|
else
|
2013-07-02 20:03:52 +04:00
|
|
|
hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
|
2011-12-26 23:41:30 +04:00
|
|
|
|
|
|
|
/* Required on CPT */
|
|
|
|
if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
|
2013-07-02 20:03:52 +04:00
|
|
|
hdmi_val |= HDMI_MODE_SELECT_HDMI;
|
2011-12-26 23:41:30 +04:00
|
|
|
|
|
|
|
if (intel_hdmi->has_audio) {
|
2012-02-03 10:54:20 +04:00
|
|
|
DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
|
|
|
|
pipe_name(intel_crtc->pipe));
|
2013-07-02 20:03:52 +04:00
|
|
|
hdmi_val |= SDVO_AUDIO_ENABLE;
|
|
|
|
hdmi_val |= HDMI_MODE_SELECT_HDMI;
|
2012-02-03 10:54:20 +04:00
|
|
|
intel_write_eld(encoder, adjusted_mode);
|
2011-12-26 23:41:30 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
if (HAS_PCH_CPT(dev))
|
2013-07-02 20:03:52 +04:00
|
|
|
hdmi_val |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
|
|
|
|
else
|
|
|
|
hdmi_val |= SDVO_PIPE_SEL(intel_crtc->pipe);
|
2011-12-26 23:41:30 +04:00
|
|
|
|
2013-07-02 20:03:52 +04:00
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2011-12-26 23:41:30 +04:00
|
|
|
|
2012-11-13 01:22:52 +04:00
|
|
|
intel_hdmi->set_infoframes(encoder, adjusted_mode);
|
2011-12-26 23:41:30 +04:00
|
|
|
}
|
|
|
|
|
2012-11-13 01:22:52 +04:00
|
|
|
static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
|
|
|
|
enum pipe *pipe)
|
2011-12-26 23:41:30 +04:00
|
|
|
{
|
2012-11-13 01:22:52 +04:00
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2011-12-26 23:41:30 +04:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-11-13 01:22:52 +04:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
|
|
u32 tmp;
|
|
|
|
|
2013-07-02 20:03:52 +04:00
|
|
|
tmp = I915_READ(intel_hdmi->hdmi_reg);
|
2012-11-13 01:22:52 +04:00
|
|
|
|
|
|
|
if (!(tmp & SDVO_ENABLE))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (HAS_PCH_CPT(dev))
|
|
|
|
*pipe = PORT_TO_PIPE_CPT(tmp);
|
|
|
|
else
|
|
|
|
*pipe = PORT_TO_PIPE(tmp);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_enable_hdmi(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-07-02 20:03:52 +04:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
|
2012-11-13 01:22:52 +04:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
2011-12-26 23:41:30 +04:00
|
|
|
u32 temp;
|
2012-02-03 10:54:20 +04:00
|
|
|
u32 enable_bits = SDVO_ENABLE;
|
|
|
|
|
|
|
|
if (intel_hdmi->has_audio)
|
|
|
|
enable_bits |= SDVO_AUDIO_ENABLE;
|
2011-12-26 23:41:30 +04:00
|
|
|
|
2013-07-02 20:03:52 +04:00
|
|
|
temp = I915_READ(intel_hdmi->hdmi_reg);
|
2011-12-26 23:41:30 +04:00
|
|
|
|
2012-11-13 01:22:52 +04:00
|
|
|
/* HW workaround for IBX, we need to move the port to transcoder A
|
2013-07-02 20:03:52 +04:00
|
|
|
* before disabling it, so restore the transcoder select bit here. */
|
|
|
|
if (HAS_PCH_IBX(dev))
|
|
|
|
enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
|
2012-11-13 01:22:52 +04:00
|
|
|
|
2011-12-26 23:41:30 +04:00
|
|
|
/* HW workaround, need to toggle enable bit off and on for 12bpc, but
|
|
|
|
* we do this anyway which shows more stable in testing.
|
|
|
|
*/
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
2013-07-02 20:03:52 +04:00
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2011-12-26 23:41:30 +04:00
|
|
|
}
|
|
|
|
|
2012-11-13 01:22:52 +04:00
|
|
|
temp |= enable_bits;
|
|
|
|
|
2013-07-02 20:03:52 +04:00
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2012-11-13 01:22:52 +04:00
|
|
|
|
|
|
|
/* HW workaround, need to write this twice for issue that may result
|
|
|
|
* in first write getting masked.
|
|
|
|
*/
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
2013-07-02 20:03:52 +04:00
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2012-11-13 01:22:52 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_disable_hdmi(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
|
|
u32 temp;
|
|
|
|
u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
|
|
|
|
|
2013-07-02 20:03:52 +04:00
|
|
|
temp = I915_READ(intel_hdmi->hdmi_reg);
|
2012-11-13 01:22:52 +04:00
|
|
|
|
|
|
|
/* HW workaround for IBX, we need to move the port to transcoder A
|
|
|
|
* before disabling it. */
|
|
|
|
if (HAS_PCH_IBX(dev)) {
|
|
|
|
struct drm_crtc *crtc = encoder->base.crtc;
|
|
|
|
int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
|
|
|
|
|
|
|
|
if (temp & SDVO_PIPE_B_SELECT) {
|
|
|
|
temp &= ~SDVO_PIPE_B_SELECT;
|
2013-07-02 20:03:52 +04:00
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2012-11-13 01:22:52 +04:00
|
|
|
|
|
|
|
/* Again we need to write this twice. */
|
2013-07-02 20:03:52 +04:00
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2012-11-13 01:22:52 +04:00
|
|
|
|
|
|
|
/* Transcoder selection bits only update
|
|
|
|
* effectively on vblank. */
|
|
|
|
if (crtc)
|
|
|
|
intel_wait_for_vblank(dev, pipe);
|
|
|
|
else
|
|
|
|
msleep(50);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* HW workaround, need to toggle enable bit off and on for 12bpc, but
|
|
|
|
* we do this anyway which shows more stable in testing.
|
|
|
|
*/
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
2013-07-02 20:03:52 +04:00
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2011-12-26 23:41:30 +04:00
|
|
|
}
|
|
|
|
|
2012-11-13 01:22:52 +04:00
|
|
|
temp &= ~enable_bits;
|
|
|
|
|
2013-07-02 20:03:52 +04:00
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2011-12-26 23:41:30 +04:00
|
|
|
|
|
|
|
/* HW workaround, need to write this twice for issue that may result
|
|
|
|
* in first write getting masked.
|
|
|
|
*/
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
2013-07-02 20:03:52 +04:00
|
|
|
I915_WRITE(intel_hdmi->hdmi_reg, temp);
|
|
|
|
POSTING_READ(intel_hdmi->hdmi_reg);
|
2011-12-26 23:41:30 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int intel_hdmi_mode_valid(struct drm_connector *connector,
|
|
|
|
struct drm_display_mode *mode)
|
|
|
|
{
|
|
|
|
if (mode->clock > 165000)
|
|
|
|
return MODE_CLOCK_HIGH;
|
|
|
|
if (mode->clock < 20000)
|
|
|
|
return MODE_CLOCK_LOW;
|
|
|
|
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
|
|
|
return MODE_NO_DBLESCAN;
|
|
|
|
|
|
|
|
return MODE_OK;
|
|
|
|
}
|
|
|
|
|
2013-07-02 20:03:52 +04:00
|
|
|
bool intel_hdmi_compute_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_config *pipe_config)
|
2011-12-26 23:41:30 +04:00
|
|
|
{
|
2013-07-02 20:03:52 +04:00
|
|
|
struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
|
2012-11-13 01:22:52 +04:00
|
|
|
|
2013-04-25 00:04:21 +04:00
|
|
|
if (intel_hdmi->color_range_auto) {
|
|
|
|
/* See CEA-861-E - 5.1 Default Encoding Parameters */
|
|
|
|
if (intel_hdmi->has_hdmi_sink &&
|
|
|
|
drm_match_cea_mode(adjusted_mode) > 1)
|
2013-07-02 20:03:52 +04:00
|
|
|
intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
|
2013-04-25 00:04:21 +04:00
|
|
|
else
|
|
|
|
intel_hdmi->color_range = 0;
|
2012-11-13 01:22:52 +04:00
|
|
|
}
|
|
|
|
|
2013-04-25 00:04:21 +04:00
|
|
|
if (intel_hdmi->color_range)
|
2013-07-02 20:03:52 +04:00
|
|
|
pipe_config->limited_color_range = true;
|
|
|
|
|
|
|
|
if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
|
|
|
|
pipe_config->has_pch_encoder = true;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* HDMI is either 12 or 8, so if the display lets 10bpc sneak
|
|
|
|
* through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
|
|
|
|
* outputs.
|
|
|
|
*/
|
|
|
|
if (pipe_config->pipe_bpp > 8*3 && HAS_PCH_SPLIT(dev)) {
|
|
|
|
DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
|
|
|
|
pipe_config->pipe_bpp = 12*3;
|
|
|
|
} else {
|
|
|
|
DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
|
|
|
|
pipe_config->pipe_bpp = 8*3;
|
|
|
|
}
|
2013-04-25 00:04:21 +04:00
|
|
|
|
|
|
|
return true;
|
2012-11-13 01:22:52 +04:00
|
|
|
}
|
|
|
|
|
2011-12-26 23:41:30 +04:00
|
|
|
static enum drm_connector_status
|
|
|
|
intel_hdmi_detect(struct drm_connector *connector, bool force)
|
|
|
|
{
|
2013-04-25 00:04:21 +04:00
|
|
|
struct drm_device *dev = connector->dev;
|
2011-12-26 23:41:30 +04:00
|
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
2013-02-13 12:23:54 +04:00
|
|
|
struct intel_digital_port *intel_dig_port =
|
|
|
|
hdmi_to_dig_port(intel_hdmi);
|
|
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
2013-04-25 00:04:21 +04:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-12-26 23:41:30 +04:00
|
|
|
struct edid *edid;
|
|
|
|
enum drm_connector_status status = connector_status_disconnected;
|
|
|
|
|
|
|
|
intel_hdmi->has_hdmi_sink = false;
|
|
|
|
intel_hdmi->has_audio = false;
|
2013-04-25 00:04:21 +04:00
|
|
|
intel_hdmi->rgb_quant_range_selectable = false;
|
2011-12-26 23:41:30 +04:00
|
|
|
edid = drm_get_edid(connector,
|
2012-11-13 01:22:52 +04:00
|
|
|
intel_gmbus_get_adapter(dev_priv,
|
|
|
|
intel_hdmi->ddc_bus));
|
2011-12-26 23:41:30 +04:00
|
|
|
|
|
|
|
if (edid) {
|
|
|
|
if (edid->input & DRM_EDID_INPUT_DIGITAL) {
|
|
|
|
status = connector_status_connected;
|
2012-11-13 01:22:52 +04:00
|
|
|
if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
|
|
|
|
intel_hdmi->has_hdmi_sink =
|
|
|
|
drm_detect_hdmi_monitor(edid);
|
2011-12-26 23:41:30 +04:00
|
|
|
intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
|
2013-04-25 00:04:21 +04:00
|
|
|
intel_hdmi->rgb_quant_range_selectable =
|
|
|
|
drm_rgb_quant_range_selectable(edid);
|
2011-12-26 23:41:30 +04:00
|
|
|
}
|
|
|
|
kfree(edid);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (status == connector_status_connected) {
|
2012-11-13 01:22:52 +04:00
|
|
|
if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
|
|
|
|
intel_hdmi->has_audio =
|
|
|
|
(intel_hdmi->force_audio == HDMI_AUDIO_ON);
|
2013-02-13 12:23:54 +04:00
|
|
|
intel_encoder->type = INTEL_OUTPUT_HDMI;
|
2011-12-26 23:41:30 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int intel_hdmi_get_modes(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
|
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
|
|
|
|
|
|
|
/* We should parse the EDID data and find out if it's an HDMI sink so
|
|
|
|
* we can send audio to it.
|
|
|
|
*/
|
|
|
|
|
|
|
|
return intel_ddc_get_modes(connector,
|
2012-11-13 01:22:52 +04:00
|
|
|
intel_gmbus_get_adapter(dev_priv,
|
|
|
|
intel_hdmi->ddc_bus));
|
2011-12-26 23:41:30 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool
|
|
|
|
intel_hdmi_detect_audio(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
|
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
|
|
|
struct edid *edid;
|
|
|
|
bool has_audio = false;
|
|
|
|
|
|
|
|
edid = drm_get_edid(connector,
|
2012-11-13 01:22:52 +04:00
|
|
|
intel_gmbus_get_adapter(dev_priv,
|
|
|
|
intel_hdmi->ddc_bus));
|
2011-12-26 23:41:30 +04:00
|
|
|
if (edid) {
|
|
|
|
if (edid->input & DRM_EDID_INPUT_DIGITAL)
|
|
|
|
has_audio = drm_detect_monitor_audio(edid);
|
|
|
|
kfree(edid);
|
|
|
|
}
|
|
|
|
|
|
|
|
return has_audio;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
intel_hdmi_set_property(struct drm_connector *connector,
|
|
|
|
struct drm_property *property,
|
|
|
|
uint64_t val)
|
|
|
|
{
|
|
|
|
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
|
2013-02-13 12:23:54 +04:00
|
|
|
struct intel_digital_port *intel_dig_port =
|
|
|
|
hdmi_to_dig_port(intel_hdmi);
|
2011-12-26 23:41:30 +04:00
|
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
|
|
|
int ret;
|
|
|
|
|
2013-02-13 12:23:54 +04:00
|
|
|
ret = drm_object_property_set_value(&connector->base, property, val);
|
2011-12-26 23:41:30 +04:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-04-25 00:04:21 +04:00
|
|
|
|
2011-12-26 23:41:30 +04:00
|
|
|
if (property == dev_priv->force_audio_property) {
|
2012-11-13 01:22:52 +04:00
|
|
|
enum hdmi_force_audio i = val;
|
2011-12-26 23:41:30 +04:00
|
|
|
bool has_audio;
|
|
|
|
|
|
|
|
if (i == intel_hdmi->force_audio)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
intel_hdmi->force_audio = i;
|
|
|
|
|
2012-11-13 01:22:52 +04:00
|
|
|
if (i == HDMI_AUDIO_AUTO)
|
2011-12-26 23:41:30 +04:00
|
|
|
has_audio = intel_hdmi_detect_audio(connector);
|
|
|
|
else
|
2012-11-13 01:22:52 +04:00
|
|
|
has_audio = (i == HDMI_AUDIO_ON);
|
2011-12-26 23:41:30 +04:00
|
|
|
|
2012-11-13 01:22:52 +04:00
|
|
|
if (i == HDMI_AUDIO_OFF_DVI)
|
|
|
|
intel_hdmi->has_hdmi_sink = 0;
|
2011-12-26 23:41:30 +04:00
|
|
|
|
|
|
|
intel_hdmi->has_audio = has_audio;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (property == dev_priv->broadcast_rgb_property) {
|
2013-07-02 20:03:52 +04:00
|
|
|
bool old_auto = intel_hdmi->color_range_auto;
|
|
|
|
uint32_t old_range = intel_hdmi->color_range;
|
|
|
|
|
2013-04-25 00:04:21 +04:00
|
|
|
switch (val) {
|
|
|
|
case INTEL_BROADCAST_RGB_AUTO:
|
|
|
|
intel_hdmi->color_range_auto = true;
|
|
|
|
break;
|
|
|
|
case INTEL_BROADCAST_RGB_FULL:
|
|
|
|
intel_hdmi->color_range_auto = false;
|
|
|
|
intel_hdmi->color_range = 0;
|
|
|
|
break;
|
|
|
|
case INTEL_BROADCAST_RGB_LIMITED:
|
|
|
|
intel_hdmi->color_range_auto = false;
|
2013-07-02 20:03:52 +04:00
|
|
|
intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
|
2013-04-25 00:04:21 +04:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2013-07-02 20:03:52 +04:00
|
|
|
|
|
|
|
if (old_auto == intel_hdmi->color_range_auto &&
|
|
|
|
old_range == intel_hdmi->color_range)
|
|
|
|
return 0;
|
|
|
|
|
2011-12-26 23:41:30 +04:00
|
|
|
goto done;
|
|
|
|
}
|
2012-11-13 01:22:52 +04:00
|
|
|
|
2011-12-26 23:41:30 +04:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
done:
|
2013-04-25 00:04:21 +04:00
|
|
|
if (intel_dig_port->base.base.crtc)
|
|
|
|
intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
|
2011-12-26 23:41:30 +04:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_hdmi_destroy(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
drm_sysfs_connector_remove(connector);
|
|
|
|
drm_connector_cleanup(connector);
|
|
|
|
kfree(connector);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
|
|
|
|
.mode_set = intel_hdmi_mode_set,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
|
2012-11-13 01:22:52 +04:00
|
|
|
.dpms = intel_connector_dpms,
|
2011-12-26 23:41:30 +04:00
|
|
|
.detect = intel_hdmi_detect,
|
|
|
|
.fill_modes = drm_helper_probe_single_connector_modes,
|
|
|
|
.set_property = intel_hdmi_set_property,
|
|
|
|
.destroy = intel_hdmi_destroy,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
|
|
|
|
.get_modes = intel_hdmi_get_modes,
|
|
|
|
.mode_valid = intel_hdmi_mode_valid,
|
|
|
|
.best_encoder = intel_best_encoder,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
|
|
|
|
.destroy = intel_encoder_destroy,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void
|
|
|
|
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
intel_attach_force_audio_property(connector);
|
|
|
|
intel_attach_broadcast_rgb_property(connector);
|
2013-04-25 00:04:21 +04:00
|
|
|
intel_hdmi->color_range_auto = true;
|
2011-12-26 23:41:30 +04:00
|
|
|
}
|
|
|
|
|
2013-02-13 12:23:54 +04:00
|
|
|
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
|
|
|
|
struct intel_connector *intel_connector)
|
2011-12-26 23:41:30 +04:00
|
|
|
{
|
2013-02-13 12:23:54 +04:00
|
|
|
struct drm_connector *connector = &intel_connector->base;
|
|
|
|
struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
|
|
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
|
|
|
struct drm_device *dev = intel_encoder->base.dev;
|
2011-12-26 23:41:30 +04:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-02-13 12:23:54 +04:00
|
|
|
enum port port = intel_dig_port->port;
|
2011-12-26 23:41:30 +04:00
|
|
|
|
|
|
|
drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
|
|
|
|
DRM_MODE_CONNECTOR_HDMIA);
|
|
|
|
drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
|
|
|
|
|
2012-11-13 01:22:52 +04:00
|
|
|
connector->interlace_allowed = 1;
|
2011-12-26 23:41:30 +04:00
|
|
|
connector->doublescan_allowed = 0;
|
|
|
|
|
2012-11-13 01:22:52 +04:00
|
|
|
switch (port) {
|
|
|
|
case PORT_B:
|
2011-12-26 23:41:30 +04:00
|
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
|
2013-07-02 20:03:52 +04:00
|
|
|
intel_encoder->hpd_pin = HPD_PORT_B;
|
2012-11-13 01:22:52 +04:00
|
|
|
break;
|
|
|
|
case PORT_C:
|
2011-12-26 23:41:30 +04:00
|
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
|
2013-07-02 20:03:52 +04:00
|
|
|
intel_encoder->hpd_pin = HPD_PORT_C;
|
2012-11-13 01:22:52 +04:00
|
|
|
break;
|
|
|
|
case PORT_D:
|
2011-12-26 23:41:30 +04:00
|
|
|
intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
|
2013-07-02 20:03:52 +04:00
|
|
|
intel_encoder->hpd_pin = HPD_PORT_D;
|
2012-11-13 01:22:52 +04:00
|
|
|
break;
|
|
|
|
case PORT_A:
|
2013-07-02 20:03:52 +04:00
|
|
|
intel_encoder->hpd_pin = HPD_PORT_A;
|
2012-11-13 01:22:52 +04:00
|
|
|
/* Internal port only for eDP. */
|
|
|
|
default:
|
|
|
|
BUG();
|
2011-12-26 23:41:30 +04:00
|
|
|
}
|
|
|
|
|
2013-07-02 20:03:52 +04:00
|
|
|
if (IS_VALLEYVIEW(dev)) {
|
2012-11-13 01:22:52 +04:00
|
|
|
intel_hdmi->write_infoframe = vlv_write_infoframe;
|
|
|
|
intel_hdmi->set_infoframes = vlv_set_infoframes;
|
2013-07-02 20:03:52 +04:00
|
|
|
} else if (!HAS_PCH_SPLIT(dev)) {
|
|
|
|
intel_hdmi->write_infoframe = g4x_write_infoframe;
|
|
|
|
intel_hdmi->set_infoframes = g4x_set_infoframes;
|
|
|
|
} else if (HAS_DDI(dev)) {
|
2012-11-13 01:22:52 +04:00
|
|
|
intel_hdmi->write_infoframe = hsw_write_infoframe;
|
|
|
|
intel_hdmi->set_infoframes = hsw_set_infoframes;
|
|
|
|
} else if (HAS_PCH_IBX(dev)) {
|
|
|
|
intel_hdmi->write_infoframe = ibx_write_infoframe;
|
|
|
|
intel_hdmi->set_infoframes = ibx_set_infoframes;
|
|
|
|
} else {
|
|
|
|
intel_hdmi->write_infoframe = cpt_write_infoframe;
|
|
|
|
intel_hdmi->set_infoframes = cpt_set_infoframes;
|
|
|
|
}
|
|
|
|
|
2013-04-25 00:04:21 +04:00
|
|
|
if (HAS_DDI(dev))
|
2013-02-13 12:23:54 +04:00
|
|
|
intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
|
|
|
|
else
|
2012-11-13 01:22:52 +04:00
|
|
|
intel_connector->get_hw_state = intel_connector_get_hw_state;
|
2011-12-26 23:41:30 +04:00
|
|
|
|
|
|
|
intel_hdmi_add_properties(intel_hdmi, connector);
|
|
|
|
|
|
|
|
intel_connector_attach_encoder(intel_connector, intel_encoder);
|
|
|
|
drm_sysfs_connector_add(connector);
|
|
|
|
|
|
|
|
/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
|
|
|
|
* 0xd. Failure to do so will result in spurious interrupts being
|
|
|
|
* generated on the port when a cable is not attached.
|
|
|
|
*/
|
|
|
|
if (IS_G4X(dev) && !IS_GM45(dev)) {
|
|
|
|
u32 temp = I915_READ(PEG_BAND_GAP_DATA);
|
|
|
|
I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
|
|
|
|
}
|
|
|
|
}
|
2013-02-13 12:23:54 +04:00
|
|
|
|
2013-07-02 20:03:52 +04:00
|
|
|
void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
|
2013-02-13 12:23:54 +04:00
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port;
|
|
|
|
struct intel_encoder *intel_encoder;
|
|
|
|
struct drm_encoder *encoder;
|
|
|
|
struct intel_connector *intel_connector;
|
|
|
|
|
|
|
|
intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
|
|
|
|
if (!intel_dig_port)
|
|
|
|
return;
|
|
|
|
|
|
|
|
intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
|
|
|
|
if (!intel_connector) {
|
|
|
|
kfree(intel_dig_port);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
intel_encoder = &intel_dig_port->base;
|
|
|
|
encoder = &intel_encoder->base;
|
|
|
|
|
|
|
|
drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
|
|
|
|
DRM_MODE_ENCODER_TMDS);
|
|
|
|
drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
|
|
|
|
|
2013-07-02 20:03:52 +04:00
|
|
|
intel_encoder->compute_config = intel_hdmi_compute_config;
|
2013-02-13 12:23:54 +04:00
|
|
|
intel_encoder->enable = intel_enable_hdmi;
|
|
|
|
intel_encoder->disable = intel_disable_hdmi;
|
|
|
|
intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
|
|
|
|
|
|
|
|
intel_encoder->type = INTEL_OUTPUT_HDMI;
|
|
|
|
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
|
|
|
|
intel_encoder->cloneable = false;
|
|
|
|
|
|
|
|
intel_dig_port->port = port;
|
2013-07-02 20:03:52 +04:00
|
|
|
intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
|
2013-02-13 12:23:54 +04:00
|
|
|
intel_dig_port->dp.output_reg = 0;
|
|
|
|
|
|
|
|
intel_hdmi_init_connector(intel_dig_port, intel_connector);
|
|
|
|
}
|