X512 fa557843f2 riscv: use atomic CSR bit set/clear operations, refactor ... Fix race conditions that cause broken timer interrupts. Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>		2022-12-11 18:43:15 +00:00
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arch_commpage_defs.h	kernel/arch/riscv64: fix crash on userland thread exit	2021-10-11 17:38:20 +00:00
arch_config.h	kernel: riscv64 patches	2021-06-07 07:14:23 +00:00
arch_cpu_defs.h	riscv: use atomic CSR bit set/clear operations, refactor	2022-12-11 18:43:15 +00:00
arch_elf.h	rumtime_loader: fix TLS for riscv64	2022-03-27 16:15:41 +00:00
arch_real_time_data.h	kernel/arch/timer: implement for riscv64	2021-08-06 15:47:48 +00:00
asm_defs.h