cbd4081064
not take the VCO limits into account; both could (and would during testing) create invalid frequencies. * Also reverted the order in which the PLL divisors are traversed to match the order of what is used in the X driver to create comparable output (our error computation is based on float, though, and should therefore create more accurate values). * The i965 introduced a special register for the surface; the former display base register is now only used for the view offset. Instead of setting the base manually here and there, there is now a set_frame_buffer_base() function. * The DPMS code will now also turn off/on the PLL clock generator. * The code needs some more cleanup, and while the driver now produces the correct timing on my i965 system, I'm now greeted by a black screen after startup. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22289 a95241bf-73f2-0310-859d-f6bbb57e9c96 |
||
|---|---|---|
| .. | ||
| atimach64 | ||
| cirrus | ||
| common | ||
| et6x00 | ||
| intel_extreme | ||
| matrox | ||
| neomagic | ||
| nvidia | ||
| radeon | ||
| s3savage | ||
| skeleton | ||
| tdfx | ||
| vesa | ||
| via | ||
| vmware | ||
| AGP.h | ||
| video_overlay.h | ||