2613175e19
* add boot item support to radeon hd driver * add edid storage to shared info * add pull of active monitor VESA EDID to radeon hd driver (until AtomBios complete) * EDID pulled in driver now passed to create_display_modes * move registers to external stock xorg radeon hd register headers (lic. allows it) git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41411 a95241bf-73f2-0310-859d-f6bbb57e9c96
133 lines
4.7 KiB
C
133 lines
4.7 KiB
C
/*
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* RadeonHD R6xx, R7xx Register documentation
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*
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* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
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* Copyright (C) 2008-2009 Matthias Hopf
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _R600_REG_H_
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#define _R600_REG_H_
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/*
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* Register definitions
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*/
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#include "r600_reg_auto_r6xx.h"
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#include "r600_reg_r6xx.h"
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#include "r600_reg_r7xx.h"
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/* SET_*_REG offsets + ends */
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enum {
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SET_CONFIG_REG_offset = 0x00008000,
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SET_CONFIG_REG_end = 0x0000ac00,
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SET_CONTEXT_REG_offset = 0x00028000,
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SET_CONTEXT_REG_end = 0x00029000,
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SET_ALU_CONST_offset = 0x00030000,
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SET_ALU_CONST_end = 0x00032000,
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SET_RESOURCE_offset = 0x00038000,
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SET_RESOURCE_end = 0x0003c000,
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SET_SAMPLER_offset = 0x0003c000,
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SET_SAMPLER_end = 0x0003cff0,
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SET_CTL_CONST_offset = 0x0003cff0,
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SET_CTL_CONST_end = 0x0003e200,
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SET_LOOP_CONST_offset = 0x0003e200,
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SET_LOOP_CONST_end = 0x0003e380,
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SET_BOOL_CONST_offset = 0x0003e380,
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SET_BOOL_CONST_end = 0x0003e38c
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};
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/* packet3 IT_SURFACE_BASE_UPDATE bits */
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enum {
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DEPTH_BASE = (1 << 0),
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COLOR0_BASE = (1 << 1),
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COLOR1_BASE = (1 << 2),
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COLOR2_BASE = (1 << 3),
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COLOR3_BASE = (1 << 4),
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COLOR4_BASE = (1 << 5),
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COLOR5_BASE = (1 << 6),
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COLOR6_BASE = (1 << 7),
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COLOR7_BASE = (1 << 8),
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STRMOUT_BASE0 = (1 << 9),
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STRMOUT_BASE1 = (1 << 10),
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STRMOUT_BASE2 = (1 << 11),
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STRMOUT_BASE3 = (1 << 12),
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COHER_BASE0 = (1 << 13),
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COHER_BASE1 = (1 << 14)
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};
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/* packet3 IT_WAIT_REG_MEM operation encoding */
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enum {
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WAIT_ALWAYS = (0<<0),
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WAIT_LT = (1<<0),
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WAIT_LE = (2<<0),
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WAIT_EQ = (3<<0),
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WAIT_NE = (4<<0),
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WAIT_GE = (5<<0),
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WAIT_GT = (6<<0),
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WAIT_REG = (0<<4),
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WAIT_MEM = (1<<4)
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};
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/* Packet3 commands */
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enum {
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IT_NOP = 0x10,
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IT_INDIRECT_BUFFER_END = 0x17,
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IT_SET_PREDICATION = 0x20,
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IT_REG_RMW = 0x21,
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IT_COND_EXEC = 0x22,
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IT_PRED_EXEC = 0x23,
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IT_START_3D_CMDBUF = 0x24,
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IT_DRAW_INDEX_2 = 0x27,
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IT_CONTEXT_CONTROL = 0x28,
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IT_DRAW_INDEX_IMMD_BE = 0x29,
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IT_INDEX_TYPE = 0x2A,
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IT_DRAW_INDEX = 0x2B,
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IT_DRAW_INDEX_AUTO = 0x2D,
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IT_DRAW_INDEX_IMMD = 0x2E,
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IT_NUM_INSTANCES = 0x2F,
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IT_STRMOUT_BUFFER_UPDATE = 0x34,
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IT_INDIRECT_BUFFER_MP = 0x38,
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IT_MEM_SEMAPHORE = 0x39,
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IT_MPEG_INDEX = 0x3A,
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IT_WAIT_REG_MEM = 0x3C,
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IT_MEM_WRITE = 0x3D,
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IT_INDIRECT_BUFFER = 0x32,
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IT_CP_INTERRUPT = 0x40,
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IT_SURFACE_SYNC = 0x43,
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IT_ME_INITIALIZE = 0x44,
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IT_COND_WRITE = 0x45,
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IT_EVENT_WRITE = 0x46,
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IT_EVENT_WRITE_EOP = 0x47,
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IT_ONE_REG_WRITE = 0x57,
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IT_SET_CONFIG_REG = 0x68,
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IT_SET_CONTEXT_REG = 0x69,
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IT_SET_ALU_CONST = 0x6A,
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IT_SET_BOOL_CONST = 0x6B,
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IT_SET_LOOP_CONST = 0x6C,
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IT_SET_RESOURCE = 0x6D,
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IT_SET_SAMPLER = 0x6E,
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IT_SET_CTL_CONST = 0x6F,
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IT_SURFACE_BASE_UPDATE = 0x73
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};
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#endif
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