694eca3bb6
* First attempts at DisplayPort link training clock equalization. * Add DP define to detect equalization state * Working towards resolving #8626
232 lines
9.4 KiB
C
232 lines
9.4 KiB
C
/*
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* Copyright 2012 Haiku, Inc. All rights reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Alexander von Gluck, kallisti5@unixzen.com
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*/
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#ifndef _DP_RAW_H
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#define _DP_RAW_H
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/* ****************************************************** */
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/* *** AUX Channel Communications *** */
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// Native AUX Communications
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#define AUX_NATIVE_WRITE (8 << 0)
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#define AUX_NATIVE_READ (9 << 0)
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#define AUX_NATIVE_REPLY_ACK (0 << 4)
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#define AUX_NATIVE_REPLY_NACK (1 << 4)
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#define AUX_NATIVE_REPLY_DEFER (2 << 4)
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#define AUX_NATIVE_REPLY_MASK (3 << 4)
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// AUX i2c Communications
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#define AUX_I2C_WRITE (0 << 0)
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#define AUX_I2C_READ (1 << 0)
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#define AUX_I2C_STATUS (2 << 0)
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#define AUX_I2C_MOT (4 << 0)
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#define AUX_I2C_REPLY_ACK (0 << 6)
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#define AUX_I2C_REPLY_NACK (1 << 6)
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#define AUX_I2C_REPLY_DEFER (2 << 6)
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#define AUX_I2C_REPLY_MASK (3 << 6)
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/* ****************************************************** */
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/* *** DPCD (DisplayPort Configuration Data) *** */
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/* *** Read / Written over DisplayPort AUX link *** */
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/* *** DPCD Receiver Compatibility Field (0x0000) *** */
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/* *** VESA DisplayPort Standard, rev 1.1, p112 *** */
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// DPCD Version (0x0)
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#define DP_DPCD_REV 0x0000 // Reg
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#define DP_DPCD_REV_MINOR_MASK (15 << 0) // Int
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#define DP_DPCD_REV_MAJOR_MASK (15 << 4) // Int
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#define DP_DPCD_REV_10 0x0010 // Value
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#define DP_DPCD_REV_11 0x0011 // Value
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// DP Maximum Link Rate (0x1)
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#define DP_MAX_LINK_RATE 0x0001 // Reg
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// Use DP_LINK_RATE_* for speed.
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// DP Maximum Lane Count (0x2)
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#define DP_MAX_LANE_COUNT 0x0002 // Reg
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#define DP_MAX_LANE_COUNT_MASK (31 << 0) // Count
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#define DP_MAX_LANE_COUNT_1 (1 << 0) // Value
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#define DP_MAX_LANE_COUNT_2 (2 << 0) // Value
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#define DP_MAX_LANE_COUNT_4 (4 << 0) // Value
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#define DP_ENHANCED_FRAME_CAP_EN (1 << 7) // Bool, Rev 1.1
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// DP Maximum Downspread (0x3)
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#define DP_MAX_DOWNSPREAD 0x0003 // Reg
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#define DP_MAX_DOWNSPREAD_EN (1 << 0) // Bool
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#define DP_MAX_DOWNSPREAD_REQ_NO_HANDSHAKE (1 << 6) // Bool
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// DP Number of Receiver Ports (0x4)
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#define DP_NORP 0x0004 // Reg
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#define DP_NORP_MASK (1 << 0) // Count
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// DP Downstream Port Present (0x5)
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#define DP_DOWNSTREAMPORT 0x0005 // Reg
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#define DP_DOWNSTREAMPORT_EN (1 << 0) // Bool
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#define DP_DOWNSTREAMPORT_TYPE_MASK (3 << 1) // Mask
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#define DP_DOWNSTREAMPORT_TYPE_DP (0 << 1) // Value
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#define DP_DOWNSTREAMPORT_TYPE_ANALOG (1 << 1) // Value
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#define DP_DOWNSTREAMPORT_TYPE_DIGITAL (2 << 1) // Value
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#define DP_DOWNSTREAMPORT_TYPE_OTHER (3 << 1) // Value
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#define DP_DOWNSTREAMPORT_FORMAT_EN (1 << 3) // Bool
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// DP Main Link Channel Coding (0x6)
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#define DP_CURR_MAIN_CHAN_CODE 0x0006 // Reg
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#define DP_CURR_MAIN_CHAN_CODE_ANSIX3_EN (1 << 0) // Bool
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// DP Downstream Port Count (0x7) (Only 1.1+)
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#define DP_DOWNSTREAMPORT_COUNT 0x0007 // Reg
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#define DP_DOWNSTREAMPORT_COUNT_MASK (15 << 0) // Count
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#define DP_DOWNSTREAMPORT_COUNT_OUI_EN (1 << 7) // Bool
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// DP Port Capability 0
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#define DP_PORT0_CAPABILITY0 0x0008 // Reg
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#define DP_PORT1_CAPABILITY0 0x000A // Reg
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#define DP_PORT_CAPABILITY0_EDID_EN (1 << 1) // Bool
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#define DP_PORT_CAPABILITY0_SECOND_EN (1 << 2) // Bool
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// DP Port Capability 1
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#define DP_PORT0_CAPABILITY1 0x0009 // Reg
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#define DP_PORT1_CAPABILITY1 0x000B // Reg
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#define DP_PORT_CAPABILITY1_BUF_SIZE_MASK (255 << 0) // Size
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// (value + 1) * 32 bytes per lane
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/* *** DPCD Link Configuration Field (0x0100) *** */
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/* *** VESA DisplayPort Standard, rev 1.1, p117 *** */
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// DP Set Link Rate Per Lane (0x0100)
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#define DP_LINK_RATE 0x0100 // Reg
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#define DP_LINK_RATE_162 0x0006 // 1.62Ghz
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#define DP_LINK_RATE_270 0x000A // 2.70Ghz
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#define DP_LINK_RATE_540 0x0014 // 5.40Ghz
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// DP Set Lane Count (0x0101)
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#define DP_LANE_COUNT 0x0101 // Reg
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#define DP_LANE_COUNT_MASK (31 << 0) // Count
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#define DP_ENHANCED_FRAME_EN (1 << 7) // Bool, Rev 1.1
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// DP Training Pattern (0x0102)
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#define DP_TRAIN 0x0102 // Reg
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#define DP_TRAIN_PATTERN_MASK (3 << 0) // Mask
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#define DP_TRAIN_PATTERN_DISABLED (0 << 0) // Value
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#define DP_TRAIN_PATTERN_1 (1 << 0) // Value
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#define DP_TRAIN_PATTERN_2 (2 << 0) // Value
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#define DP_TRAIN_PATTERN_3 (3 << 0) // Value
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#define DP_TRAIN_QUAL_MASK (3 << 2) // Mask
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#define DP_TRAIN_QUAL_NONE (0 << 2) // Value
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#define DP_TRAIN_QUAL_D102 (1 << 2) // Value
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#define DP_TRAIN_QUAL_SYMB_ERR (2 << 2) // Value
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#define DP_TRAIN_QUAL_PRBS7 (3 << 2) // Value
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#define DP_TRAIN_CLOCK_RECOVER_EN (1 << 4) // Bool
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#define DP_TRAIN_SCRAMBLE_DI (1 << 5) // Bool (rev)
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#define DP_TRAIN_SYMBL_ERR_SEL_MASK (3 << 6) // Mask
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#define DP_TRAIN_SYMBL_ERR_SEL_BOTH (0 << 6) // Value
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#define DP_TRAIN_SYMBL_ERR_SEL_DISPARITY (1 << 6) // Value
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#define DP_TRAIN_SYMBL_ERR_SEL_SYMBOL (2 << 6) // Value
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// DP Training Lane n (0x0103 - 0x0106)
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#define DP_TRAIN_LANE0 0x0103 // Reg
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#define DP_TRAIN_LANE1 0x0104 // Reg
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#define DP_TRAIN_LANE2 0x0105 // Reg
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#define DP_TRAIN_LANE3 0x0106 // Reg
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#define DP_TRAIN_VCC_SWING_SHIFT (0 << 0) // Shift
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#define DP_TRAIN_VCC_SWING_MASK (3 << 0) // Mask
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#define DP_TRAIN_VCC_SWING_400 (0 << 0) // Value
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#define DP_TRAIN_VCC_SWING_600 (1 << 0) // Value
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#define DP_TRAIN_VCC_SWING_800 (2 << 0) // Value
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#define DP_TRAIN_VCC_SWING_1200 (3 << 0) // Value
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#define DP_TRAIN_MAX_SWING_EN (1 << 2) // Bool
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#define DP_TRAIN_PRE_EMPHASIS_SHIFT (3 << 0) // Shift
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#define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) // Mask
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#define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) // Value
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#define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) // Value
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#define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) // Value
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#define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) // Value
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#define DP_TRAIN_MAX_EMPHASIS_EN (1 << 5) // Bool
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// DP Down-spread Control (0x0107)
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#define DP_DOWNSPREAD_CTRL 0x0107 // Reg
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#define DP_DOWNSPREAD_CTRL_FREQ_MASK (1 << 0) // Int
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#define DP_DOWNSPREAD_CTRL_AMP_EN (1 << 4) // Int
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// DP Main Link Channel Coding (0x0108)
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#define DP_MAIN_CHAN_CODE 0x0108 // Reg
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#define DP_MAIN_CHAN_CODE_ANSIX3_EN (1 << 0) // Bool
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/* *** DPCD Link / Sink Status Field (0x0200) *** */
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/* *** VESA DisplayPort Standard, rev 1.1, p120 *** */
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// DP Sink Count (0x0200)
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#define DP_SINK_COUNT 0x0200 // Reg
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#define DP_SINK_COUNT_MASK (63 << 0) // Mask
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#define DP_SINK_COUNT_CP_READY (1 << 6) // Bool
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// DP Service IRQ Vector (0x0201)
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#define DP_SINK_IRQ_VECTOR 0x0201 // Reg
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#define DP_SINK_IRQ_TEST_REQ (1 << 1) // Bool
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#define DP_SINK_IRQ_CP_IRQ (1 << 2) // Bool
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#define DP_SINK_IRQ_VENDOR (1 << 6) // Bool
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// DP Lane Status A B
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#define DP_LANE_STATUS_0_1 0x0202 // Reg
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#define DP_LANE_STATUS_2_3 0x0203 // Reg
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#define DP_LINK_STATUS_SIZE 6 // Size
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#define DP_LANE_STATUS_CR_DONE_A (1 << 0) // Bool
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#define DP_LANE_STATUS_CHEQ_DONE_A (1 << 1) // Bool
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#define DP_LANE_STATUS_SYMB_LOCK_A (1 << 2) // Bool
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#define DP_LANE_STATUS_CR_DONE_B (1 << 4) // Bool
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#define DP_LANE_STATUS_CHEQ_DONE_B (1 << 5) // Bool
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#define DP_LANE_STATUS_SYMB_LOCK_B (1 << 6) // Bool
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#define DP_LANE_STATUS_EQUALIZED_A DP_LANE_STATUS_CR_DONE_A \
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|| DP_LANE_STATUS_CHEQ_DONE_A \
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|| DP_LANE_STATUS_SYMB_LOCK_A
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#define DP_LANE_STATUS_EQUALIZED_B DP_LANE_STATUS_CR_DONE_B \
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|| DP_LANE_STATUS_CHEQ_DONE_B \
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|| DP_LANE_STATUS_SYMB_LOCK_B
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// DP Lane Align Status (0x0204)
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#define DP_LANE_ALIGN 0x0204 // Reg
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#define DP_LANE_ALIGN_DONE (1 << 0) // Bool
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#define DP_LANE_ALIGN_PORT_STATUS_CHANGE (1 << 6) // Bool
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#define DP_LANE_ALIGN_LINK_STATUS_UPDATE (1 << 7) // Bool
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// DP Sink Status (0x0205)
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#define DP_SINK_STATUS 0x0205 // Reg
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#define DP_SINK_STATUS_IN_SYNC_0 (1 << 0) // Bool
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#define DP_SINK_STATUS_IN_SYNC_1 (1 << 1) // Bool
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// DP Adjust Request A B
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#define DP_ADJ_REQUEST_0_1 0x0206 // Reg
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#define DP_ADJ_REQUEST_2_3 0x0207 // Reg
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#define DP_ADJ_VCC_SWING_LANEA_SHIFT 0 // Shift
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#define DP_ADJ_VCC_SWING_LANEA_MASK (3 << 0) // Mask
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#define DP_ADJ_PRE_EMPHASIS_LANEA_SHIFT 2 // Shift
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#define DP_ADJ_PRE_EMPHASIS_LANEA_MASK (3 << 2) // Mask
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#define DP_ADJ_VCC_SWING_LANEB_SHIFT 4 // Shift
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#define DP_ADJ_VCC_SRING_LANEB_MASK (3 << 4) // Mask
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#define DP_ADJ_PRE_EMPHASIS_LANEB_SHIFT 6 // Shift
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#define DP_ADJ_PRE_EMPHASIS_LANEB_MASK (3 << 6) // Mask
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// TODO: 0x0210 - 0x0217
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/* *** DPCD Automated Self-testing Field (0x0218) *** */
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/* *** VESA DisplayPort Standard, rev 1.1, p123 *** */
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// TODO: Optional Field
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/* *** DPCD Source Device Specific Field (0x0300) *** */
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/* *** VESA DisplayPort Standard, rev 1.1, p127 *** */
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// TODO
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/* *** DPCD Sink Device Specific Field (0x0400) *** */
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/* *** VESA DisplayPort Standard, rev 1.1, p127 *** */
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// TODO
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/* *** DPCD Branch Device Specific Field (0x0500) *** */
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/* *** VESA DisplayPort Standard, rev 1.1, p127 *** */
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// TODO
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/* *** DPCD Sink Control Field (0x0600) *** */
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/* *** VESA DisplayPort Standard, rev 1.1, p128 *** */
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#define DP_SET_POWER 0x0600 // Reg
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#define DP_SET_POWER_D0 (1 << 0) // Value
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#define DP_SET_POWER_D3 (1 << 1) // Value
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/* *** DPCD Reserved (0x0700+) *** */
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/* ****************************************************** */
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#endif /* _DP_RAW_H */
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