58 lines
1.3 KiB
C
58 lines
1.3 KiB
C
/*
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* Copyright 2014, Paweł Dziepak, pdziepak@quarnos.org.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Alexander von Gluck IV <kallisti5@unixzen.com>
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*/
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#ifndef _KERNEL_ARCH_ARM_ATOMIC_H
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#define _KERNEL_ARCH_ARM_ATOMIC_H
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#if __ARM_ARCH__ <= 5
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#define isb() __asm__ __volatile__("" : : : "memory")
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#define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb() __asm__ __volatile__("" : : : "memory")
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#elif __ARM_ARCH__ == 6
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#define isb() __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 4" \
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: : "r" (0) : "memory")
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#define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 5" \
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: : "r" (0) : "memory")
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#else /* ARMv7+ */
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#define isb() __asm__ __volatile__("isb" : : : "memory")
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#define dsb() __asm__ __volatile__("dsb" : : : "memory")
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#define dmb() __asm__ __volatile__("dmb" : : : "memory")
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#endif
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static inline void
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memory_read_barrier_inline(void)
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{
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dmb();
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}
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static inline void
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memory_write_barrier_inline(void)
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{
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dmb();
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}
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static inline void
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memory_full_barrier_inline(void)
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{
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dmb();
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}
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#define memory_read_barrier memory_read_barrier_inline
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#define memory_write_barrier memory_write_barrier_inline
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#define memory_full_barrier memory_full_barrier_inline
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#endif // _KERNEL_ARCH_ARM_ATOMIC_H
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