476346ac62
Change-Id: Ib643545271700e6ff4a4037d0e797355194927e7 Reviewed-on: https://review.haiku-os.org/c/haiku/+/5149 Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org> Reviewed-by: David Karoly <karolyd577@gmail.com> Reviewed-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>
555 lines
11 KiB
C++
555 lines
11 KiB
C++
/*
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* Copyright 2022 Haiku, Inc. All rights reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Oliver Ruiz Dorantes, oliver.ruiz.dorantes@gmail.com
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*/
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#ifndef __DEV_UART_LINFLEX_H
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#define __DEV_UART_LINFLEX_H
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#include <sys/types.h>
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#include <ByteOrder.h>
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#include <SupportDefs.h>
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#include <arch/generic/debug_uart.h>
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#define UART_KIND_LINFLEX "linflex"
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namespace LINFlexRegisters {
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typedef union { /* LINFLEX LIN Control 1 (Base+0x0000) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32 :16;
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vuint32 CCD:1;
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vuint32 CFD:1;
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vuint32 LASE:1;
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vuint32 AWUM:1;
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vuint32 MBL:4;
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vuint32 BF:1;
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vuint32 SFTM:1;
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vuint32 LBKM:1;
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vuint32 MME:1;
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vuint32 SBDT:1;
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vuint32 RBLM:1;
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vuint32 SLEEP:1;
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vuint32 INIT:1;
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#endif
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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vuint32 INIT:1;
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vuint32 SLEEP:1;
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vuint32 RBLM:1;
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vuint32 SBDT:1;
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vuint32 MME:1;
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vuint32 LBKM:1;
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vuint32 SFTM:1;
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vuint32 BF:1;
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vuint32 MBL:4;
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vuint32 AWUM:1;
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vuint32 LASE:1;
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vuint32 CFD:1;
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vuint32 CCD:1;
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vuint32 :16;
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#endif
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} B;
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} LINCR1_register;
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typedef union { /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32 :16;
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vuint32 SZIE:1;
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vuint32 OCIE:1;
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vuint32 BEIE:1;
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vuint32 CEIE:1;
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vuint32 HEIE:1;
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vuint32:2;
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vuint32 FEIE:1;
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vuint32 BOIE:1;
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vuint32 LSIE:1;
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vuint32 WUIE:1;
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vuint32 DBFIE:1;
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vuint32 DBEIE:1;
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vuint32 DRIE:1;
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vuint32 DTIE:1;
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vuint32 HRIE:1;
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#endif
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} B;
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} LINIER_register;
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typedef union { /* LINFLEX LIN Status (Base+0x0008) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32 :16;
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vuint32 LINS:4;
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vuint32:2;
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vuint32 RMB:1;
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vuint32:1;
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vuint32 RBSY:1;
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vuint32 RPS:1;
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vuint32 WUF:1;
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vuint32 DBFF:1;
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vuint32 DBEF:1;
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vuint32 DRF:1;
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vuint32 DTF:1;
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vuint32 HRF:1;
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#endif
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} B;
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} LINSR_register;
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typedef union { /* LINFLEX LIN Error Status (Base+0x000C) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32 :16;
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vuint32 SZF:1;
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vuint32 OCF:1;
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vuint32 BEF:1;
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vuint32 CEF:1;
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vuint32 SFEF:1;
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vuint32 BDEF:1;
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vuint32 IDPEF:1;
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vuint32 FEF:1;
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vuint32 BOF:1;
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vuint32:6;
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vuint32 NF:1;
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#endif
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} B;
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} LINESR_register;
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typedef union { /* LINFLEX UART Mode Control (Base+0x0010) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32 :16;
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vuint32:1;
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vuint32 TDFL:2;
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vuint32:1;
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vuint32 RDFL:2;
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vuint32 RFBM:1;
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vuint32 TFBM:1;
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vuint32 WL1:1;
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vuint32 PC1:1;
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vuint32 RXEN:1;
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vuint32 TXEN:1;
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vuint32 PC0:1;
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vuint32 PCE:1;
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vuint32 WL:1;
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vuint32 UART:1;
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#endif
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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vuint32 UART:1;
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vuint32 WL:1;
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vuint32 PCE:1;
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vuint32 PC0:1;
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vuint32 TXEN:1;
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vuint32 RXEN:1;
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vuint32 PC1:1;
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vuint32 WL1:1;
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vuint32 TFBM:1;
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vuint32 RFBM:1;
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vuint32 RDFL:2;
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vuint32:1;
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vuint32 TDFL:2;
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vuint32:1;
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vuint32 :16;
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#endif
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} B;
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} UARTCR_register;
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typedef union { /* LINFLEX UART Mode Status (Base+0x0014) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32 :16;
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vuint32 SZF:1;
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vuint32 OCF:1;
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vuint32 PE:4; /*Can check all 4 RX'd bytes at once with array*/
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vuint32 RMB:1;
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vuint32 FEF:1;
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vuint32 BOF:1;
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vuint32 RPS:1;
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vuint32 WUF:1;
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vuint32:2;
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vuint32 DRF:1;
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vuint32 DTF:1;
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vuint32 NF:1;
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#endif
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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vuint32 NF:1;
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vuint32 DTF:1;
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vuint32 DRF:1;
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vuint32:2;
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vuint32 WUF:1;
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vuint32 RPS:1;
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vuint32 BOF:1;
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vuint32 FEF:1;
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vuint32 RMB:1;
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vuint32 PE:4; /*Can check all 4 RX'd bytes at once with array*/
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vuint32 OCF:1;
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vuint32 SZF:1;
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vuint32 :16;
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#endif
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} B;
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} UARTSR_register;
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typedef union { /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32 :16;
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vuint32:5;
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vuint32 LTOM:1;
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vuint32 IOT:1;
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vuint32 TOCE:1;
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vuint32 CNT:8;
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#endif
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} B;
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} LINTCSR_register;
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typedef union { /* LINFLEX LIN Output Compare (Base+0x001C) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32 :16;
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vuint32 OC2:8;
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vuint32 OC1:8;
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#endif
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} B;
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} LINOCR_register;
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typedef union { /* LINFLEX LIN Timeout Control (Base+0x0020) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32 :20;
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vuint32 RTO:4;
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vuint32:1;
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vuint32 HTO:7;
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#endif
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} B;
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} LINTOCR_register;
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typedef union { /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32:28;
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vuint32 DIV_F:4;
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#endif
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} B;
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} LINFBRR_register;
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typedef union { /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32:19;
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vuint32 DIV_M:13;
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#endif
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} B;
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} LINIBRR_register;
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typedef union { /* LINFLEX LIN Checksum Field (Base+0x002C) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32:24;
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vuint32 CF:8;
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#endif
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} B;
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} LINCFR_register;
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typedef union { /* LINFLEX LIN Control 2 (Base+0x0030) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32:17;
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vuint32 IOBE:1;
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vuint32 IOPE:1;
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vuint32 WURQ:1;
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vuint32 DDRQ:1;
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vuint32 DTRQ:1;
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vuint32 ABRQ:1;
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vuint32 HTRQ:1;
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vuint32:8;
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#endif
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} B;
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} LINCR2_register;
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typedef union { /* LINFLEX Buffer Identifier (Base+0x0034) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32:16;
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vuint32 DFL:6;
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vuint32 DIR:1;
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vuint32 CCS:1;
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vuint32:2;
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vuint32 ID:6;
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#endif
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} B;
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} BIDR_register;
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typedef union { /* LINFLEX Buffer Data LSB (Base+0x0038) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32 DATA3:8;
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vuint32 DATA2:8;
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vuint32 DATA1:8;
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vuint32 DATA0:8;
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#endif
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} B;
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} BDRL_register;
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typedef union { /* LINFLEX Buffer Data MSB (Base+0x003C */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32 DATA7:8;
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vuint32 DATA6:8;
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vuint32 DATA5:8;
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vuint32 DATA4:8;
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#endif
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} B;
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} BDRM_register;
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typedef union { /* LINFLEX Identifier Filter Enable (+0x0040) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32:24;
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vuint32 FACT:8;
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#endif
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} B;
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} IFER_register;
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typedef union { /* LINFLEX Identifier Filter Match Index (+0x0044)*/
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32:28;
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vuint32 IFMI:4;
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#endif
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} B;
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} IFMI_register;
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typedef union { /* LINFLEX Identifier Filter Mode (Base+0x0048) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32:28;
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vuint32 IFM:4;
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#endif
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} B;
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} IFMR_register;
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typedef union { /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32:16;
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vuint32:3;
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vuint32 DFL:3;
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vuint32 DIR:1;
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vuint32 CCS:1;
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vuint32:2;
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vuint32 ID:6;
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#endif
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} B;
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} IFCR_register;
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typedef union { /* LINFLEX Global Counter (+0x008C) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32:26;
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vuint32 TDFBM:1;
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vuint32 RDFBM:1;
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vuint32 TDLIS:1;
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vuint32 RDLIS:1;
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vuint32 STOP:1;
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vuint32 SR:1;
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#endif
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} B;
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} GCR_register;
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typedef union { /* LINFLEX UART preset timeout (+0x0090) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32:20;
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vuint32 PTO:12;
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#endif
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} B;
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} UARTPTO_register;
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typedef union { /* LINFLEX UART current timeout (+0x0094) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32:20;
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vuint32 CTO:12;
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#endif
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} B;
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} UARTCTO_register;
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typedef union { /* LINFLEX DMA Tx Enable (+0x0098) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32:16;
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vuint32 DTE15:1;
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vuint32 DTE14:1;
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vuint32 DTE13:1;
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vuint32 DTE12:1;
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vuint32 DTE11:1;
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vuint32 DTE10:1;
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vuint32 DTE9:1;
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vuint32 DTE8:1;
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vuint32 DTE7:1;
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vuint32 DTE6:1;
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vuint32 DTE5:1;
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vuint32 DTE4:1;
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vuint32 DTE3:1;
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vuint32 DTE2:1;
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vuint32 DTE1:1;
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vuint32 DTE0:1;
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#endif
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} B;
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} DMATXE_register;
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typedef union { /* LINFLEX DMA RX Enable (+0x009C) */
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vuint32 R;
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struct {
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#if __BYTE_ORDER == __BIG_ENDIAN
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vuint32:16;
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vuint32 DRE15:1;
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vuint32 DRE14:1;
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vuint32 DRE13:1;
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vuint32 DRE12:1;
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vuint32 DRE11:1;
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vuint32 DRE10:1;
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vuint32 DRE9:1;
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vuint32 DRE8:1;
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vuint32 DRE7:1;
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vuint32 DRE6:1;
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vuint32 DRE5:1;
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vuint32 DRE4:1;
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vuint32 DRE3:1;
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vuint32 DRE2:1;
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vuint32 DRE1:1;
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vuint32 DRE0:1;
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#endif
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} B;
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} DMARXE_register;
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// Helper to deal with w1c (Write 1 to clear) register fields
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template<typename REG>
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REG BitfieldRegister() {
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REG reg;
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reg.R = 0;
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return reg;
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}
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typedef struct {
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LINCR1_register LINCR1; /* LINFLEX LIN Control 1 (Base+0x0000) */
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LINIER_register LINIER; /* LINFLEX LIN Interrupt Enable (Base+0x0004) */
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LINSR_register LINSR; /* LINFLEX LIN Status (Base+0x0008) */
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LINESR_register LINESR; /* LINFLEX LIN Error Status (Base+0x000C) */
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UARTCR_register UARTCR; /* LINFLEX UART Mode Control (Base+0x0010) */
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UARTSR_register UARTSR; /* LINFLEX UART Mode Status (Base+0x0014) */
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LINTCSR_register LINTCSR; /* LINFLEX TimeOut Control Status ((Base+0x0018)*/
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LINOCR_register LINOCR; /* LINFLEX LIN Output Compare (Base+0x001C) */
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LINTOCR_register LINTOCR; /* LINFLEX LIN Timeout Control (Base+0x0020) */
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LINFBRR_register LINFBRR; /* LINFLEX LIN Fractional Baud Rate (+0x0024) */
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LINIBRR_register LINIBRR; /* LINFLEX LIN Integer Baud Rate (Base+0x0028) */
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LINCFR_register LINCFR; /* LINFLEX LIN Checksum Field (Base+0x002C) */
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LINCR2_register LINCR2; /* LINFLEX LIN Control 2 (Base+0x0030) */
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BIDR_register BIDR; /* LINFLEX Buffer Identifier (Base+0x0034) */
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BDRL_register BDRL; /* LINFLEX Buffer Data LSB (Base+0x0038) */
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BDRM_register BDRM; /* LINFLEX Buffer Data MSB (Base+0x003C */
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IFER_register IFER; /* LINFLEX Identifier Filter Enable (+0x0040) */
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IFMI_register IFMI; /* LINFLEX Identifier Filter Match Index (+0x0044)*/
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IFMR_register IFMR; /* LINFLEX Identifier Filter Mode (Base+0x0048) */
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IFCR_register IFCR[16]; /* LINFLEX Identifier Filter Control 0..15 (+0x004C-0x0088)*/
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GCR_register GCR; /* LINFLEX Global Counter (+0x008C) */
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UARTPTO_register UARTPTO; /* LINFLEX UART preset timeout (+0x0090) */
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UARTCTO_register UARTCTO; /* LINFLEX UART current timeout (+0x0094) */
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DMATXE_register DMATXE; /* LINFLEX DMA Tx Enable (+0x0098) */
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DMARXE_register DMARXE; /* LINFLEX DMA RX Enable (+0x009C) */
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} LINFlex;
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}
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class ArchUARTlinflex : public DebugUART {
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public:
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ArchUARTlinflex(addr_t base, int64 clock);
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~ArchUARTlinflex();
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void InitEarly();
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void InitPort(uint32 baud);
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void Enable();
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void Disable();
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int PutChar(char c);
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int GetChar(bool wait);
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void FlushTx();
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void FlushRx();
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private:
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template<typename TO, typename TA>
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void Out(TA* reg, TO value) {
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*(volatile TO*)(reg) = value;
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}
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template<typename TI, typename TA>
|
|
TI In(TA* reg) {
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|
return *(volatile TI*)(reg);
|
|
}
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|
|
|
virtual void Barrier();
|
|
LINFlexRegisters::LINFlex* LinflexCell() {
|
|
return reinterpret_cast<LINFlexRegisters::LINFlex*>(Base());
|
|
}
|
|
};
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|
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|
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|
ArchUARTlinflex *arch_get_uart_linflex(addr_t base, int64 clock);
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|
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|
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#endif
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