c6799d8ae1
* Reduce number of common DP registers in radeon_hd * Move to bitwise shifts as they will make more sense to more people in the long-run
59 lines
1.6 KiB
C
59 lines
1.6 KiB
C
/*
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* Copyright 2011, Haiku, Inc. All Rights Reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Alexander von Gluck, kallisti5@unixzen.com
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*
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* DisplayPort DRM Specifications:
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* Copyright © 2008 Keith Packard
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*/
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#ifndef __DISPLAYPORT_REG_H__
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#define __DISPLAYPORT_REG_H__
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/* TODO: get access to DisplayPort specifications and
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* place this into graphic private common code
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*/
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#define DP_TPS3_SUPPORTED (1 << 6)
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#define DP_LANE0_1_STATUS 0x202
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#define DP_LANE2_3_STATUS 0x203
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#define DP_LANE_CR_DONE (1 << 0)
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#define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
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#define DP_LANE_SYMBOL_LOCKED (1 << 2)
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#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE \
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| DP_LANE_CHANNEL_EQ_DONE \
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| DP_LANE_SYMBOL_LOCKED)
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#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
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#define DP_INTERLANE_ALIGN_DONE (1 << 0)
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#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
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#define DP_LINK_STATUS_UPDATED (1 << 7)
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#define DP_LINK_STATUS_SIZE 6
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#define DP_SINK_STATUS 0x205
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#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
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#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
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#define DP_ADJUST_REQUEST_LANE0_1 0x206
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#define DP_ADJUST_REQUEST_LANE2_3 0x207
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#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
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#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
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#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
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#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
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#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
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#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
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#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
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#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
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#define DP_SET_POWER 0x600
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#define DP_SET_POWER_D0 0x1
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#endif /*__DISPLAYPORT_REG_H__*/
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