c08ed2db65
Some SMT implementations (e.g. recent AMD microarchitectures) have separate L1d cache for each SMT thread (which AMD decides to call "cores"). This means that we shouldn't move threads to another logical processor too often even if it belongs to the same core. We aren't very strict about this as it would complicate load balancing, but we try to reduce unnecessary migrations. |
||
---|---|---|
.. | ||
boot | ||
glue | ||
kernel | ||
ldscripts | ||
libroot | ||
runtime_loader | ||
Jamfile |