b602e341ca
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12849 a95241bf-73f2-0310-859d-f6bbb57e9c96
419 lines
14 KiB
C
419 lines
14 KiB
C
/*
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Copyright 1999, Be Incorporated. All Rights Reserved.
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This file may be used under the terms of the Be Sample Code License.
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Other authors:
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Mark Watson;
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Apsed;
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Rudolf Cornelissen 10/2002-5/2005.
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*/
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#ifndef DRIVERINTERFACE_H
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#define DRIVERINTERFACE_H
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#include <Accelerant.h>
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#include "video_overlay.h"
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#include <Drivers.h>
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#include <PCI.h>
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#include <OS.h>
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#include "AGP.h"
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#define DRIVER_PREFIX "nv" // apsed
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/*
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Internal driver state (also for sharing info between driver and accelerant)
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*/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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typedef struct {
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sem_id sem;
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int32 ben;
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} benaphore;
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#define INIT_BEN(x) x.sem = create_sem(0, "NV "#x" benaphore"); x.ben = 0;
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#define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem);
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#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem);
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#define DELETE_BEN(x) delete_sem(x.sem);
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#define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */
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/*dualhead extensions to flags*/
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#define DUALHEAD_OFF (0<<6)
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#define DUALHEAD_CLONE (1<<6)
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#define DUALHEAD_ON (2<<6)
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#define DUALHEAD_SWITCH (3<<6)
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#define DUALHEAD_BITS (3<<6)
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#define DUALHEAD_CAPABLE (1<<8)
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#define TV_BITS (3<<9)
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#define TV_MON (0<<9
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#define TV_PAL (1<<9)
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#define TV_NTSC (2<<9)
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#define TV_CAPABLE (1<<11)
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#define TV_VIDEO (1<<12)
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#define SKD_MOVE_CURSOR 0x00000001
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#define SKD_PROGRAM_CLUT 0x00000002
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#define SKD_SET_START_ADDR 0x00000004
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#define SKD_SET_CURSOR 0x00000008
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#define SKD_HANDLER_INSTALLED 0x80000000
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enum {
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NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
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NV_GET_PCI,
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NV_SET_PCI,
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NV_DEVICE_NAME,
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NV_RUN_INTERRUPTS,
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NV_GET_NTH_AGP_INFO,
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NV_ENABLE_AGP,
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NV_ISA_OUT,
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NV_ISA_IN
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};
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/* handles to pre-defined engine commands */
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#define NV_ROP5_SOLID 0x00000000 /* 2D */
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#define NV_IMAGE_BLACK_RECTANGLE 0x00000001 /* 2D/3D */
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#define NV_IMAGE_PATTERN 0x00000002 /* 2D */
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//#define NV3_SURFACE_0 0x00000003 /* 3D: old cmd */
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//#define NV3_SURFACE_1 0x00000004 /* 3D: old cmd */
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//#define NV3_SURFACE_2 0x00000005 /* 3D: nolonger used */
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//#define NV3_SURFACE_3 0x00000006 /* 3D: nolonger used */
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#define NV4_SURFACE 0x00000010 /* 2D */
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#define NV10_CONTEXT_SURFACES_2D 0x00000010 /* 2D */
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//#define NV1_IMAGE_FROM_CPU 0x00000010 /* 2D: unused */
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#define NV_IMAGE_BLIT 0x00000011 /* 2D */
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/* fixme:
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* never use NV3_GDI_RECTANGLE_TEXT for DMA acceleration:
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* There's a hardware fault in the input->output colorspace conversion here.
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* Besides, in NV40 and up this command nolonger exists. Both 'facts' are confirmed
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* by testing.
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*/
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//#define NV3_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */
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#define NV4_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */
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#define NV4_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */
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#define NV10_CONTEXT_SURFACES_ARGB_ZS 0x00000013 /* 3D */
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#define NV4_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */
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#define NV10_DX5_TEXTURE_TRIANGLE 0x00000014 /* 3D */
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#define NV4_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */
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#define NV10_DX6_MULTI_TEXTURE_TRIANGLE 0x00000015 /* unused (yet?) */
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#define NV1_RENDER_SOLID_LIN 0x00000016 /* 2D: unused */
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/* max. number of overlay buffers */
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#define MAXBUFFERS 3
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/* internal used info on overlay buffers */
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typedef struct {
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uint16 slopspace;
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uint32 size;
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} int_buf_info;
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typedef struct { // apsed, see comments in nv.settings
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// for driver
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char accelerant[B_FILE_NAME_LENGTH];
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bool dumprom;
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// for accelerant
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uint32 logmask;
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uint32 memory;
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bool usebios;
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bool hardcursor;
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bool switchhead;
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bool force_pci;
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bool unhide_fw;
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bool pgm_panel;
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bool dma_acc;
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} nv_settings;
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/*shared info*/
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typedef struct {
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/*a few ID things*/
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uint16 vendor_id; /* PCI vendor ID, from pci_info */
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uint16 device_id; /* PCI device ID, from pci_info */
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uint8 revision; /* PCI device revsion, from pci_info */
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uint8 bus; /* PCI bus number, from pci_info */
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uint8 device; /* PCI device number on bus, from pci_info */
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uint8 function; /* PCI function number in device, from pci_info */
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/* bug workaround for 4.5.0 */
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uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/
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uint32 * clone_bugfix_regs;
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/*memory mappings*/
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area_id regs_area; /* Kernel's area_id for the memory mapped registers.
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It will be cloned into the accelerant's address
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space. */
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area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */
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area_id unaligned_dma_area; /* Area assigned for DMA. It will be (partially) mapped to an
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aligned area using MTRR-WC. */
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area_id dma_area; /* Aligned area assigned for DMA. The addresses are shared with all teams. */
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void *framebuffer; /* As viewed from virtual memory */
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void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */
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void *dma_buffer; /* As viewed from virtual memory */
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void *dma_buffer_pci; /* As viewed from the PCI bus (for DMA) */
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/*screenmode list*/
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area_id mode_area; /* Contains the list of display modes the driver supports */
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uint32 mode_count; /* Number of display modes in the list */
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/*flags - used by driver*/
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uint32 flags;
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/*vblank semaphore*/
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sem_id vblank; /* The vertical blank semaphore. Ownership will be
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transfered to the team opening the device first */
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/*cursor information*/
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struct {
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uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */
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uint16 hot_y; /* is 0,0 */
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uint16 x; /* The location of the cursor hot spot on the */
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uint16 y; /* desktop */
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uint16 width; /* Width and height of the cursor shape (always 16!) */
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uint16 height;
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bool is_visible; /* Is the cursor currently displayed? */
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bool dh_right; /* Is cursor on right side of stretched screen? */
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} cursor;
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/*colour lookup table*/
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uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */
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/*more display mode stuff*/
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display_mode dm; /* current display mode configuration: head1 */
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bool acc_mode; /* signals (non)accelerated mode */
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bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */
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bool crtc_switch_mode; /* signals dualhead switch mode if panels are used */
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/*frame buffer config - for BDirectScreen*/
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frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */
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/*acceleration engine*/
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struct {
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uint32 count; /* last dwgsync slot used */
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uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */
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benaphore lock; /* for serializing access to the acc engine */
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struct {
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uint32 handle[0x08]; /* FIFO channel's cmd handle for the owning cmd */
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uint32 ch_ptr[0x20]; /* cmd handle's ptr to it's assigned FIFO ch (if any) */
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} fifo;
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struct {
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uint32 put; /* last 32-bit-word adress given to engine to exec. to */
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uint32 current; /* first free 32-bit-word adress in buffer */
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uint32 free; /* nr. of useable free 32-bit words remaining in buffer */
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uint32 max; /* command buffer's useable size in 32-bit words */
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} dma;
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bool agp_mode; /* card is running in AGP mode */
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} engine;
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/* fixme:
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* the stuff below has to be extended and/or changed I guess:
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* for now only a single 3D 'clone' driver is supported. */
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/* pointers to first and last free memory adress for 3D use: cardmem local offsets */
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uint32 mem_low;
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uint32 mem_high;
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/* flag to inform 3D add-on to stop rendering (set by 2D, reset by 3D drv) */
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bool mode_changed;
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/* flag to inform 3D add-on a mode-change is currently in progress
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* (set and reset by 2D drv) */
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bool mode_changing;
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/* card info - information gathered from PINS (and other sources) */
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enum
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{ // card_type in order of date of NV chip design
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NV04 = 0,
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NV05,
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NV05M64,
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NV06,
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NV10,
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NV11,
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NV11M,
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NV15,
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NV17,
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NV17M,
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NV18,
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NV18M,
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NV20,
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NV25,
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NV28,
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NV30,
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NV31,
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NV34,
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NV35,
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NV36,
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NV38,
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NV40,
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NV41,
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NV43,
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NV44,
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NV45
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};
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enum
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{ // card_arch in order of date of NV chip design
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NV04A = 0,
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NV10A,
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NV20A,
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NV30A,
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NV40A
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};
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enum
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{ // tvout_chip_type in order of capability (more or less)
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NONE = 0,
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CH7003,
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CH7004,
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CH7005,
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CH7006,
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CH7007,
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CH7008,
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SAA7102,
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SAA7103,
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SAA7104,
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SAA7105,
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BT868,
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BT869,
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CX25870,
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CX25871,
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NVIDIA
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};
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struct
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{
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/* specialised registers for card initialisation read from NV BIOS (pins) */
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/* general card information */
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uint32 card_type; /* see card_type enum above */
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uint32 card_arch; /* see card_arch enum above */
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bool laptop; /* mobile chipset or not ('internal' flatpanel!) */
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bool slaved_tmds1; /* external TMDS encoder active on CRTC1 */
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bool slaved_tmds2; /* external TMDS encoder active on CRTC2 */
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bool master_tmds1; /* on die TMDS encoder active on CRTC1 */
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bool master_tmds2; /* on die TMDS encoder active on CRTC2 */
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bool tmds1_active; /* found panel on CRTC1 that is active */
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bool tmds2_active; /* found panel on CRTC2 that is active */
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display_timing p1_timing; /* 'modeline' fetched for panel 1 */
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display_timing p2_timing; /* 'modeline' fetched for panel 2 */
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float panel1_aspect; /* panel's aspect ratio */
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float panel2_aspect; /* panel's aspect ratio */
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bool crtc2_prim; /* using CRTC2 as primary CRTC */
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uint32 tvout_chip_type; /* see tvchip_type enum above */
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uint8 monitors; /* output devices connection matrix */
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status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */
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/* PINS */
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float f_ref; /* PLL reference-oscillator frequency (Mhz) */
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bool ext_pll; /* the extended PLL contains more dividers */
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uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */
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uint32 min_system_vco;
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uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */
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uint32 min_pixel_vco;
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uint32 max_video_vco; /* dac2 PLL VCO limits (Mhz) */
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uint32 min_video_vco;
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uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */
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uint32 std_memory_clock; /* card memory clock speed needed (Mhz) */
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uint32 max_dac1_clock; /* dac1 limits (Mhz) */
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uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */
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uint32 max_dac1_clock_16;
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uint32 max_dac1_clock_24;
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uint32 max_dac1_clock_32;
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uint32 max_dac1_clock_32dh;
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uint32 max_dac2_clock; /* dac2 limits (Mhz) */
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uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */
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uint32 max_dac2_clock_16;
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uint32 max_dac2_clock_24;
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uint32 max_dac2_clock_32;
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uint32 max_dac2_clock_32dh;
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bool secondary_head; /* presence of functions */
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bool tvout;
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bool primary_dvi;
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bool secondary_dvi;
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uint32 memory_size; /* memory (in bytes) */
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} ps;
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/* mirror of the ROM (copied in driver, because may not be mapped permanently) */
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uint8 rom_mirror[65536];
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/* some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */
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nv_settings settings;
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struct
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{
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overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */
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int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */
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overlay_token myToken; /* scaler is free/in use */
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benaphore lock; /* for creating buffers and aquiring overlay unit routines */
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bool crtc; /* location of overlay unit */
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/* variables needed for virtualscreens (move_overlay()): */
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bool active; /* true is overlay currently in use */
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overlay_window ow; /* current position of overlay output window */
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overlay_buffer ob; /* current inputbuffer in use */
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overlay_view my_ov; /* current corrected view in inputbuffer */
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uint32 h_ifactor; /* current 'unclipped' horizontal inverse scaling factor */
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uint32 v_ifactor; /* current 'unclipped' vertical inverse scaling factor */
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} overlay;
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} shared_info;
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/* Read or write a value in PCI configuration space */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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uint32 offset; /* Offset to read/write */
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uint32 size; /* Number of bytes to transfer */
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uint32 value; /* The value read or written */
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} nv_get_set_pci;
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/* Set some boolean condition (like enabling or disabling interrupts) */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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bool do_it; /* state to set */
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} nv_set_bool_state;
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/* Retrieve the area_id of the kernel/accelerant shared info */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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area_id shared_info_area; /* area_id containing the shared information */
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} nv_get_private_data;
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/* Retrieve the device name. Usefull for when we have a file handle, but want
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to know the device name (like when we are cloning the accelerant) */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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char *name; /* The name of the device, less the /dev root */
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} nv_device_name;
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/* Retrieve an AGP device interface if there. Usefull to find the AGP speed scheme
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used (pre 3.x or 3.x) */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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bool agp_bus;/* indicates if we have access to the AGP busmanager */
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uint8 index; /* device index in list of devices found */
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bool exist; /* we got AGP device info */
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agp_info agpi; /* AGP interface info of a device */
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} nv_nth_agp_info;
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/* Execute an AGP command */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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bool agp_bus;/* indicates if we have access to the AGP busmanager */
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uint32 cmd; /* actual command to execute */
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} nv_cmd_agp;
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/* Read or write a value in ISA I/O space */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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uint16 adress; /* Offset to read/write */
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uint8 size; /* Number of bytes to transfer */
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uint16 data; /* The value read or written */
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} nv_in_out_isa;
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enum {
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_WAIT_FOR_VBLANK = (1 << 0)
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};
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#if defined(__cplusplus)
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}
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#endif
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#endif
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