X512 fa557843f2 riscv: use atomic CSR bit set/clear operations, refactor ... Fix race conditions that cause broken timer interrupts. Change-Id: I78e13a18d394b1566977e894a1def16a66c9ca5f Reviewed-on: https://review.haiku-os.org/c/haiku/+/5883 Reviewed-by: X512 <danger_mail@list.ru> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>		2022-12-11 18:43:15 +00:00
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arm	kernel/arm: check for PXN and alignment fault in page fault handler	2022-09-05 17:29:49 +00:00
arm64	arm64: Add thread exit syscall in commpage.	2022-05-29 18:51:32 +00:00
m68k	rumtime_loader: fix TLS for riscv64	2022-03-27 16:15:41 +00:00
mipsel	rumtime_loader: fix TLS for riscv64	2022-03-27 16:15:41 +00:00
ppc	rumtime_loader: fix TLS for riscv64	2022-03-27 16:15:41 +00:00
riscv64	riscv: use atomic CSR bit set/clear operations, refactor	2022-12-11 18:43:15 +00:00
sparc	rumtime_loader: fix TLS for riscv64	2022-03-27 16:15:41 +00:00
x86	rumtime_loader: fix TLS for riscv64	2022-03-27 16:15:41 +00:00
x86_64	rumtime_loader: fix TLS for riscv64	2022-03-27 16:15:41 +00:00