310 lines
10 KiB
C
310 lines
10 KiB
C
/*
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Copyright 1999, Be Incorporated. All Rights Reserved.
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This file may be used under the terms of the Be Sample Code License.
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Other authors:
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Mark Watson;
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Apsed;
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Rudolf Cornelissen 10/2002-4/2006.
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*/
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#ifndef DRIVERINTERFACE_H
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#define DRIVERINTERFACE_H
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#include <Accelerant.h>
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#include "video_overlay.h"
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#include <Drivers.h>
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#include <PCI.h>
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#include <OS.h>
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#define DRIVER_PREFIX "matrox" // apsed
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#define DEVICE_FORMAT "%04x_%04x_%02x%02x%02x" // apsed
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/*
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Internal driver state (also for sharing info between driver and accelerant)
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*/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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typedef struct {
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sem_id sem;
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int32 ben;
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} benaphore;
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#define INIT_BEN(x) x.sem = create_sem(0, "G400 "#x" benaphore"); x.ben = 0;
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#define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem);
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#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem);
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#define DELETE_BEN(x) delete_sem(x.sem);
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#define GX00_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */
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/*dualhead extensions to flags*/
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#define DUALHEAD_OFF (0<<6)
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#define DUALHEAD_CLONE (1<<6)
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#define DUALHEAD_ON (2<<6)
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#define DUALHEAD_SWITCH (3<<6)
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#define DUALHEAD_BITS (3<<6)
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#define DUALHEAD_CAPABLE (1<<8)
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#define TV_BITS (3<<9)
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#define TV_MON (0<<9
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#define TV_PAL (1<<9)
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#define TV_NTSC (2<<9)
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#define TV_CAPABLE (1<<11)
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#define TV_VIDEO (1<<12)
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#define TV_PRIMARY (1<<13)
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#define SKD_MOVE_CURSOR 0x00000001
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#define SKD_PROGRAM_CLUT 0x00000002
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#define SKD_SET_START_ADDR 0x00000004
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#define SKD_SET_CURSOR 0x00000008
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#define SKD_HANDLER_INSTALLED 0x80000000
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enum {
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GX00_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
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GX00_GET_PCI,
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GX00_SET_PCI,
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GX00_DEVICE_NAME,
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GX00_RUN_INTERRUPTS
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};
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/* max. number of overlay buffers */
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#define MAXBUFFERS 3
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/* max. pixelclock speed the BES supports */
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#define BESMAXSPEED 135000
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/* internal used info on overlay buffers */
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typedef struct
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{
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uint16 slopspace;
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uint32 size;
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} int_buf_info;
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typedef struct settings { // apsed, see comments in mga.settings
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// for driver
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char accelerant[B_FILE_NAME_LENGTH];
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char primary[B_FILE_NAME_LENGTH];
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bool dumprom;
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// for accelerant
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uint32 logmask;
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uint32 memory;
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bool usebios;
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bool hardcursor;
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bool greensync;
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} settings;
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/* shared info */
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typedef struct {
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/* a few ID things */
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uint16 vendor_id; /* PCI vendor ID, from pci_info */
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uint16 device_id; /* PCI device ID, from pci_info */
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uint8 revision; /* PCI device revsion, from pci_info */
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uint8 bus; /* PCI bus number, from pci_info */
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uint8 device; /* PCI device number on bus, from pci_info */
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uint8 function; /* PCI function number in device, from pci_info */
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/* used to return status for INIT_ACCELERANT and CLONE_ACCELERANT */
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bool accelerant_in_use;
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/* bug workaround for 4.5.0 */
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uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/
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uint32 * clone_bugfix_regs;
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/*memory mappings*/
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area_id regs_area; /* Kernel's area_id for the memory mapped registers.
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It will be cloned into the accelerant's address
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space. */
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area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */
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area_id pseudo_dma_area; /* Pseudo dma area_id. Shared by all teams. */
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area_id dma_buffer_area; /* Area assigned for dma*/
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void *framebuffer; /* As viewed from virtual memory */
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void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */
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void *pseudo_dma; /* As viewed from virtual memory */
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void *dma_buffer; /* buffer for dma*/
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void *dma_buffer_pci; /* buffer for dma - from PCI bus*/
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/*screenmode list*/
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area_id mode_area; /* Contains the list of display modes the driver supports */
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uint32 mode_count; /* Number of display modes in the list */
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/*flags - used by driver*/
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uint32 flags;
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/*vblank semaphore*/
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sem_id vblank; /* The vertical blank semaphore. Ownership will be
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transfered to the team opening the device first */
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/*cursor information*/
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struct {
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uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */
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uint16 hot_y; /* is 0,0 */
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uint16 x; /* The location of the cursor hot spot on the */
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uint16 y; /* desktop */
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uint16 width; /* Width and height of the cursor shape (always 16!) */
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uint16 height;
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bool is_visible; /* Is the cursor currently displayed? */
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} cursor;
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/*colour lookup table*/
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uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */
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/*more display mode stuff*/
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display_mode dm; /* current display mode configuration: head1 */
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display_mode dm2; /* current display mode configuration: head2 */
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uint32 dpms_flags; /* current DPMS mode */
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bool switched_crtcs; /* dualhead stretch and switch mode info */
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bool acc_mode; /* signals (non)accelerated mode */
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bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */
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/*frame buffer config - for BDirectScreen*/
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frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */
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frame_buffer_config fbc2; /* bytes_per_row and start of frame buffer: head2 */
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accelerant_device_info adi; /* as returned by hook GET_ACCELERANT_DEVICE_INFO */
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/*acceleration engine*/
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struct {
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uint32 count; /* last dwgsync slot used */
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uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */
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benaphore lock; /* for serializing access to the acceleration engine */
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uint32 src_dst; /* G100 pre SRCORG/DSTORG registers */
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uint8 y_lin; /* MIL1/2 adress linearisation does not always work */
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uint8 depth;
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} engine;
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/* card info - information gathered from PINS (and other sources) */
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enum
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{ // card_type in order of date of MGA chip design
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MIL1 = 0,
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MYST,
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MIL2,
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G100,
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G200,
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G400,
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G400MAX,
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G450,
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G550
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} card_type;
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struct
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{
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/* specialised registers for card initialisation read from MGA BIOS (pins) */
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/* general card information */
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uint32 card_type; /* see card_type enum above */
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bool int_assigned; /* card has a useable INT assigned to it */
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status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */
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bool sdram; /* TRUE if SDRAM card: needed info for 2D acceleration */
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/* PINS */
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float f_ref; /* PLL reference-oscillator frequency (Mhz) */
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uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */
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uint32 min_system_vco;
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uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */
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uint32 min_pixel_vco;
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uint32 max_video_vco; /* dac2, maven PLL VCO limits (Mhz) */
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uint32 min_video_vco;
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uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */
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uint32 std_engine_clock_dh;
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uint32 max_dac1_clock; /* dac1 limits (Mhz) */
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uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */
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uint32 max_dac1_clock_16;
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uint32 max_dac1_clock_24;
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uint32 max_dac1_clock_32;
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uint32 max_dac1_clock_32dh;
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uint32 max_dac2_clock; /* dac2 limits (Mhz) */
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uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */
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uint32 max_dac2_clock_16;
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uint32 max_dac2_clock_24;
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uint32 max_dac2_clock_32;
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uint32 max_dac2_clock_32dh;
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bool secondary_head; /* presence of functions */
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bool tvout;
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bool primary_dvi;
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bool secondary_dvi;
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uint32 memory_size; /* memory (Mb) */
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uint32 mctlwtst_reg; /* memory control waitstate register */
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uint32 memrdbk_reg; /* memory readback register */
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uint32 option_reg; /* option register */
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uint32 option2_reg; /* option2 register */
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uint32 option3_reg; /* option3 register */
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uint32 option4_reg; /* option4 register */
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uint8 v3_option2_reg; /* pins v3 option2 register, not used for G100 */
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uint8 v3_clk_div; /* pins v3 memory and system clock division factors */
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uint8 v3_mem_type; /* pins v3 memory type info */
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uint16 v5_mem_type; /* pins v5 memory type info */
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} ps;
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/* mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb) */
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uint8 rom_mirror[32768];
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/* CRTC delay -> used in timing for MAVEN, depending on which CRTC is driving it */
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uint8 crtc_delay;
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/* MAVEN sync polarity offset from 'reset' situation: MAVEN sync polarity setup
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* works in a serial fashion without readback or handy reset options! */
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uint8 maven_syncpol_offset;
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/* On G450/G550 we need this info for secondary head DPMS functionality */
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bool crossed_conns;
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/* apsed: some configuration settings from ~/config/settings/kernel/drivers/mga.settings if exists */
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settings settings;
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struct
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{
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overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */
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int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */
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overlay_token myToken; /* scaler is free/in use */
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benaphore lock; /* for creating buffers and aquiring overlay unit routines */
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/* variables needed for virtualscreens (move_overlay()): */
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bool active; /* true is overlay currently in use */
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overlay_window ow; /* current position of overlay output window */
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overlay_buffer ob; /* current inputbuffer in use */
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overlay_view my_ov; /* current corrected view in inputbuffer */
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uint32 h_ifactor; /* current 'unclipped' horizontal inverse scaling factor */
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uint32 v_ifactor; /* current 'unclipped' vertical inverse scaling factor */
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} overlay;
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} shared_info;
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/* Read or write a value in PCI configuration space */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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uint32 offset; /* Offset to read/write */
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uint32 size; /* Number of bytes to transfer */
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uint32 value; /* The value read or written */
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} gx00_get_set_pci;
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/* Set some boolean condition (like enabling or disabling interrupts) */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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bool do_it; /* state to set */
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} gx00_set_bool_state;
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/* Retrieve the area_id of the kernel/accelerant shared info */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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area_id shared_info_area; /* area_id containing the shared information */
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} gx00_get_private_data;
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/* Retrieve the device name. Usefull for when we have a file handle, but want
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to know the device name (like when we are cloning the accelerant) */
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typedef struct {
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uint32 magic; /* magic number to make sure the caller groks us */
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char *name; /* The name of the device, less the /dev root */
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} gx00_device_name;
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enum {
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GX00_WAIT_FOR_VBLANK = (1 << 0)
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};
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#if defined(__cplusplus)
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}
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#endif
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#endif
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