100 lines
3.0 KiB
C
100 lines
3.0 KiB
C
/*
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* Copyright 2010-2012 Haiku, Inc. All rights reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Francois Revol
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* Ithamar R. Adema, ithamar.adema@team-embedded.nl
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* Alexander von Gluck, kallisti5@unixzen.com
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*/
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#ifndef _ARCH_ARM_ARM_MMU_H
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#define _ARCH_ARM_ARM_MMU_H
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/*
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* generic arm mmu definitions
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*/
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/*
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* L1 defines for the page directory (page table walk methods)
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*/
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#define ARM_MMU_L1_TYPE_FAULT 0x0
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// MMU Fault
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// 31 2 10
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// | |00|
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#define ARM_MMU_L1_TYPE_SECTION 0x2
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// Single step table walk, 4096 entries
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// 1024K pages, 16K consumed
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// 31 20 19 12 11 10 9 8 5 432 10
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// | page table address | 0? | AP |0| domain |1CB|10|
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#define ARM_MMU_L1_TYPE_FINE 0x3
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// Three(?) step table walk, 1024 entries
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// 1K, 4K, 64K pages, 4K consumed
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// 31 12 11 9 8 5 432 10
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// | page table address | 0? | domain |100|11|
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#define ARM_MMU_L1_TYPE_COARSE 0x1
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// Two step table walk, 256 entries
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// 4K(Haiku), 64K pages, 1K consumed
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// 31 10 9 8 5 432 10
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// | page table address |0| domain |000|01|
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// the domain is not used so and the ? is implementation specified... have not
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// found it in the cortex A8 reference... so I set t to 0
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// page table must obviously be on multiple of 1KB
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/*
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* L2-Page descriptors... now things get really complicated...
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* there are three different types of pages large pages (64KB) and small(4KB)
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* and "small extended".
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* only small extende is used by now....
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* and there is a new and a old format of page table entries
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* I will use the old format...
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*/
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#define ARM_MMU_L2_TYPE_LARGE 0x1
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#define ARM_MMU_L2_TYPE_SMALLEXT 0x3
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/* for new format entries (cortex-a8) */
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#define ARM_MMU_L2_TYPE_SMALLNEW 0x2
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// for B C and TEX see ARM arm B4-11
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#define ARM_MMU_L2_FLAG_B 0x4
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#define ARM_MMU_L2_FLAG_C 0x8
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#define ARM_MMU_L2_FLAG_TEX 0 // use 0b000 as TEX
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#define ARM_MMU_L2_FLAG_AP_RW 0x30
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// allow read and write for user and system
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#define ARM_MMU_L1_TABLE_ENTRY_COUNT 4096
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#define ARM_MMU_L1_TABLE_SIZE (ARM_MMU_L1_TABLE_ENTRY_COUNT \
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* sizeof(uint32))
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#define ARM_MMU_L2_COARSE_ENTRY_COUNT 256
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#define ARM_MMU_L2_COARSE_TABLE_SIZE (ARM_MMU_L2_COARSE_ENTRY_COUNT \
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* sizeof(uint32))
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#define ARM_MMU_L2_FINE_ENTRY_COUNT 1024
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#define ARM_MMU_L2_FINE_TABLE_SIZE (ARM_MMU_L2_FINE_ENTRY_COUNT \
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* sizeof(uint32))
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/*
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* definitions for CP15 r1
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*/
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#define CR_R1_MMU 0x1 // enable MMU
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#define CP_R1_XP 0x800000
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// if XP=0 then use backwards comaptible translation tables
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#define VADDR_TO_PDENT(va) ((va) >> 20)
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#define VADDR_TO_PTENT(va) (((va) & 0xff000) >> 12)
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#define VADDR_TO_PGOFF(va) ((va) & 0x0fff)
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#define ARM_PDE_ADDRESS_MASK 0xfffffc00
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#define ARM_PDE_TYPE_MASK 0x00000003
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#define ARM_PTE_ADDRESS_MASK 0xfffff000
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#define ARM_PTE_TYPE_MASK 0x00000003
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#endif /* _ARCH_ARM_ARM_MMU_H */
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