196 lines
5.7 KiB
C
196 lines
5.7 KiB
C
/*
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* Copyright 2008, Dustin Howett, dustin.howett@gmail.com. All rights reserved.
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* Copyright 2005, Axel Dörfler, axeld@pinc-software.de. All rights reserved.
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* Distributed under the terms of the MIT License.
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*
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* Copyright 2001-2002, Travis Geiselbrecht. All rights reserved.
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* Distributed under the terms of the NewOS License.
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*/
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#ifndef _KERNEL_ARCH_x86_ARCH_APIC_H
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#define _KERNEL_ARCH_x86_ARCH_APIC_H
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#define MP_FLOATING_SIGNATURE '_PM_'
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#define MP_CONFIG_TABLE_SIGNATURE 'PCMP'
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#define APIC_ENABLE 0x100
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#define APIC_FOCUS (~(1 << 9))
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#define APIC_SIV (0xff)
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// offsets to APIC register
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#define APIC_ID 0x020
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#define APIC_VERSION 0x030
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#define APIC_TASK_PRIORITY 0x080
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#define APIC_ARBITRATION_PRIORITY 0x090
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#define APIC_PROCESSOR_PRIORITY 0x0a0
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#define APIC_EOI 0x0b0
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#define APIC_LOGICAL_DEST 0x0d0
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#define APIC_DEST_FORMAT 0x0e0
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#define APIC_SPURIOUS_INTR_VECTOR 0x0f0
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#define APIC_ERROR_STATUS 0x280
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#define APIC_INTR_COMMAND_1 0x300 // bits 0-31
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#define APIC_INTR_COMMAND_2 0x310 // bits 32-63
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#define APIC_LVT_TIMER 0x320
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#define APIC_LVT_THERMAL_SENSOR 0x330
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#define APIC_LVT_PERFMON_COUNTERS 0x340
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#define APIC_LVT_LINT0 0x350
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#define APIC_LVT_LINT1 0x360
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#define APIC_LVT_ERROR 0x370
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#define APIC_INITIAL_TIMER_COUNT 0x380
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#define APIC_CURRENT_TIMER_COUNT 0x390
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#define APIC_TIMER_DIVIDE_CONFIG 0x3e0
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/* standard APIC interrupt defines */
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#define APIC_DELIVERY_MODE_FIXED 0
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#define APIC_DELIVERY_MODE_LOWESTPRI (1 << 8) // ICR1 only
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#define APIC_DELIVERY_MODE_SMI (2 << 8)
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#define APIC_DELIVERY_MODE_NMI (4 << 8)
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#define APIC_DELIVERY_MODE_INIT (5 << 8)
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#define APIC_DELIVERY_MODE_STARTUP (6 << 8) // ICR1 only
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#define APIC_DELIVERY_MODE_ExtINT (7 << 8) // LINT0/1 only
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#define APIC_DELIVERY_STATUS (1 << 12)
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#define APIC_TRIGGER_MODE_LEVEL (1 << 15)
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/* Interrupt Command defines */
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#define APIC_INTR_COMMAND_1_MASK 0xfff3f000
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#define APIC_INTR_COMMAND_2_MASK 0x00ffffff
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#define APIC_INTR_COMMAND_1_DEST_MODE_PHYSICAL 0
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#define APIC_INTR_COMMAND_1_DEST_MODE_LOGICAL (1 << 11)
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#define APIC_INTR_COMMAND_1_ASSERT (1 << 14)
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#define APIC_INTR_COMMAND_1_DEST_FIELD 0
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#define APIC_INTR_COMMAND_1_DEST_SELF (1 << 18)
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#define APIC_INTR_COMMAND_1_DEST_ALL (2 << 18)
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#define APIC_INTR_COMMAND_1_DEST_ALL_BUT_SELF (3 << 18)
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/* Local Vector Table defines */
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#define APIC_LVT_MASKED (1 << 16)
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// timer defines
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#define APIC_LVT_TIMER_MASK 0xfffcef00
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// LINT0/1 defines
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#define APIC_LVT_LINT_MASK 0xfffe0800
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#define APIC_LVT_LINT_INPUT_POLARITY (1 << 13)
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// Timer Divide Config Divisors
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#define APIC_TIMER_DIVIDE_CONFIG_1 0x0b
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#define APIC_TIMER_DIVIDE_CONFIG_2 0x00
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#define APIC_TIMER_DIVIDE_CONFIG_4 0x01
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#define APIC_TIMER_DIVIDE_CONFIG_8 0x02
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#define APIC_TIMER_DIVIDE_CONFIG_16 0x03
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#define APIC_TIMER_DIVIDE_CONFIG_32 0x08
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#define APIC_TIMER_DIVIDE_CONFIG_64 0x09
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#define APIC_TIMER_DIVIDE_CONFIG_128 0x0a
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/*
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#define APIC_LVT_DM 0x00000700
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#define APIC_LVT_DM_ExtINT 0x00000700
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#define APIC_LVT_DM_NMI 0x00000400
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#define APIC_LVT_IIPP 0x00002000
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#define APIC_LVT_TM 0x00008000
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#define APIC_LVT_M 0x00010000
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#define APIC_LVT_OS 0x00020000
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#define APIC_TPR_PRIO 0x000000ff
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#define APIC_TPR_INT 0x000000f0
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#define APIC_TPR_SUB 0x0000000f
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#define APIC_SVR_SWEN 0x00000100
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#define APIC_SVR_FOCUS 0x00000200
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#define IOAPIC_ID 0x0
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#define IOAPIC_VERSION 0x1
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#define IOAPIC_ARB 0x2
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#define IOAPIC_REDIR_TABLE 0x10
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#define IPI_CACHE_FLUSH 0x40
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#define IPI_INV_TLB 0x41
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#define IPI_INV_PTE 0x42
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#define IPI_INV_RESCHED 0x43
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#define IPI_STOP 0x44
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*/
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struct mp_config_table {
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uint32 signature; /* "PCMP" */
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uint16 base_table_length; /* length of the base table entries and this structure */
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uint8 spec_revision; /* spec supported, 1 for 1.1 or 4 for 1.4 */
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uint8 checksum; /* checksum, all bytes add up to zero */
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char oem[8]; /* oem identification, not null-terminated */
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char product[12]; /* product name, not null-terminated */
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void *oem_table; /* addr of oem-defined table, zero if none */
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uint16 oem_length; /* length of oem table */
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uint16 num_base_entries; /* number of entries in base table */
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uint32 apic; /* address of apic */
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uint16 ext_length; /* length of extended section */
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uint8 ext_checksum; /* checksum of extended table entries */
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uint8 reserved;
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};
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struct mp_floating_struct {
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uint32 signature; /* "_MP_" */
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struct mp_config_table *config_table; /* address of mp configuration table */
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uint8 config_length; /* length of the table in 16-byte units */
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uint8 spec_revision; /* spec supported, 1 for 1.1 or 4 for 1.4 */
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uint8 checksum; /* checksum, all bytes add up to zero */
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uint8 mp_feature_1; /* mp system configuration type if no mpc */
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uint8 mp_feature_2; /* imcrp */
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uint8 mp_feature_3, mp_feature_4, mp_feature_5; /* reserved */
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};
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/* base config entry types */
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enum {
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MP_BASE_PROCESSOR = 0,
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MP_BASE_BUS,
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MP_BASE_IO_APIC,
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MP_BASE_IO_INTR,
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MP_BASE_LOCAL_INTR,
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};
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struct mp_base_processor {
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uint8 type;
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uint8 apic_id;
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uint8 apic_version;
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uint8 cpu_flags;
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uint32 signature; /* stepping, model, family, each four bits */
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uint32 feature_flags;
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uint32 res1, res2;
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};
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struct mp_base_ioapic {
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uint8 type;
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uint8 ioapic_id;
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uint8 ioapic_version;
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uint8 ioapic_flags;
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uint32 *addr;
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};
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struct mp_base_bus {
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uint8 type;
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uint8 bus_id;
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char name[6];
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};
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struct mp_base_interrupt {
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uint8 type;
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uint8 interrupt_type;
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uint16 polarity : 2;
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uint16 trigger_mode : 2;
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uint16 _reserved : 12;
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uint8 source_bus_id;
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uint8 source_bus_irq;
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uint8 dest_apic_id;
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uint8 dest_apic_int;
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};
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enum {
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MP_INTR_TYPE_INT = 0,
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MP_INTR_TYPE_NMI,
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MP_INTR_TYPE_SMI,
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MP_INTR_TYPE_ExtINT,
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};
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#endif /* _KERNEL_ARCH_x86_ARCH_APIC_H */
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