85 lines
3.8 KiB
C
85 lines
3.8 KiB
C
/*
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**
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** Naive RealTek 8139C driver for the DC Broadband Adapter. Some
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** assistance on names of things from the NetBSD-DC sources.
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**
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** (c)2001 Dan Potter
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** License: X11
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**
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*/
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#ifndef _RTL_8139C_H
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#define _RTL_8139C_H
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/* RTL8139C register definitions */
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#define RT_IDR0 0x00 /* Mac address */
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#define RT_MAR0 0x08 /* Multicast filter */
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#define RT_TXSTATUS0 0x10 /* Transmit status (4 32bit regs) */
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#define RT_TXADDR0 0x20 /* Tx descriptors (also 4 32bit) */
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#define RT_RXBUF 0x30 /* Receive buffer start address */
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#define RT_RXEARLYCNT 0x34 /* Early Rx byte count */
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#define RT_RXEARLYSTATUS 0x36 /* Early Rx status */
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#define RT_CHIPCMD 0x37 /* Command register */
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#define RT_RXBUFTAIL 0x38 /* Current address of packet read (queue tail) */
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#define RT_RXBUFHEAD 0x3A /* Current buffer address (queue head) */
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#define RT_INTRMASK 0x3C /* Interrupt mask */
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#define RT_INTRSTATUS 0x3E /* Interrupt status */
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#define RT_TXCONFIG 0x40 /* Tx config */
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#define RT_RXCONFIG 0x44 /* Rx config */
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#define RT_TIMER 0x48 /* A general purpose counter */
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#define RT_RXMISSED 0x4C /* 24 bits valid, write clears */
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#define RT_CFG9346 0x50 /* 93C46 command register */
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#define RT_CONFIG0 0x51 /* Configuration reg 0 */
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#define RT_CONFIG1 0x52 /* Configuration reg 1 */
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#define RT_TIMERINT 0x54 /* Timer interrupt register (32 bits) */
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#define RT_MEDIASTATUS 0x58 /* Media status register */
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#define RT_CONFIG3 0x59 /* Config register 3 */
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#define RT_CONFIG4 0x5A /* Config register 4 */
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#define RT_MULTIINTR 0x5C /* Multiple interrupt select */
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#define RT_MII_TSAD 0x60 /* Transmit status of all descriptors (16 bits) */
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#define RT_MII_BMCR 0x62 /* Basic Mode Control Register (16 bits) */
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#define RT_MII_BMSR 0x64 /* Basic Mode Status Register (16 bits) */
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#define RT_AS_ADVERT 0x66 /* Auto-negotiation advertisement reg (16 bits) */
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#define RT_AS_LPAR 0x68 /* Auto-negotiation link partner reg (16 bits) */
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#define RT_AS_EXPANSION 0x6A /* Auto-negotiation expansion reg (16 bits) */
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/* RTL8193C command bits; or these together and write teh resulting value
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into CHIPCMD to execute it. */
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#define RT_CMD_RESET 0x10
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#define RT_CMD_RX_ENABLE 0x08
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#define RT_CMD_TX_ENABLE 0x04
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#define RT_CMD_RX_BUF_EMPTY 0x01
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/* RTL8139C interrupt status bits */
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#define RT_INT_PCIERR 0x8000 /* PCI Bus error */
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#define RT_INT_TIMEOUT 0x4000 /* Set when TCTR reaches TimerInt value */
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#define RT_INT_RXFIFO_OVERFLOW 0x0040 /* Rx FIFO overflow */
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#define RT_INT_RXFIFO_UNDERRUN 0x0020 /* Packet underrun / link change */
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#define RT_INT_RXBUF_OVERFLOW 0x0010 /* Rx BUFFER overflow */
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#define RT_INT_TX_ERR 0x0008
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#define RT_INT_TX_OK 0x0004
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#define RT_INT_RX_ERR 0x0002
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#define RT_INT_RX_OK 0x0001
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/* RTL8139C transmit status bits */
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#define RT_TX_CARRIER_LOST 0x80000000 /* Carrier sense lost */
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#define RT_TX_ABORTED 0x40000000 /* Transmission aborted */
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#define RT_TX_OUT_OF_WINDOW 0x20000000 /* Out of window collision */
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#define RT_TX_STATUS_OK 0x00008000 /* Status ok: a good packet was transmitted */
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#define RT_TX_UNDERRUN 0x00004000 /* Transmit FIFO underrun */
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#define RT_TX_HOST_OWNS 0x00002000 /* Set to 1 when DMA operation is completed */
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#define RT_TX_SIZE_MASK 0x00001fff /* Descriptor size mask */
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/* RTL8139C receive status bits */
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#define RT_RX_MULTICAST 0x00008000 /* Multicast packet */
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#define RT_RX_PAM 0x00004000 /* Physical address matched */
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#define RT_RX_BROADCAST 0x00002000 /* Broadcast address matched */
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#define RT_RX_BAD_SYMBOL 0x00000020 /* Invalid symbol in 100TX packet */
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#define RT_RX_RUNT 0x00000010 /* Packet size is <64 bytes */
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#define RT_RX_TOO_LONG 0x00000008 /* Packet size is >4K bytes */
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#define RT_RX_CRC_ERR 0x00000004 /* CRC error */
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#define RT_RX_FRAME_ALIGN 0x00000002 /* Frame alignment error */
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#define RT_RX_STATUS_OK 0x00000001 /* Status ok: a good packet was received */
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#endif
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