f9412d9f8a
* MMU mapping * EL2 to EL1 transition (FreeBSD/Jaroslaw Pelczar) * Initial implementation for cache cleaning and TLB invalidations (ARM) * Processor Helper functions * Additional Logging in boot process Change-Id: Idcee93583418a3c3528c5d9586d3add487f9d5ca Reviewed-on: https://review.haiku-os.org/c/haiku/+/4888 Reviewed-by: Adrien Destugues <pulkomandy@gmail.com> Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
128 lines
4.2 KiB
C
128 lines
4.2 KiB
C
/*-
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* Copyright (c) 2014 Andrew Turner
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* Copyright (c) 2014-2015 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Andrew Turner under
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* sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PTE_H_
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#define _MACHINE_PTE_H_
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#ifndef LOCORE
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typedef uint64_t pd_entry_t; /* page directory entry */
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typedef uint64_t pt_entry_t; /* page table entry */
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#endif
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/* Block and Page attributes */
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/* TODO: Add the upper attributes */
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#define ATTR_MASK_H UINT64_C(0xfff0000000000000)
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#define ATTR_MASK_L UINT64_C(0x0000000000000fff)
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#define ATTR_MASK (ATTR_MASK_H | ATTR_MASK_L)
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/* Bits 58:55 are reserved for software */
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#define ATTR_SW_DIRTY (1UL << 56)
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#define ATTR_UXN (1UL << 54)
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#define ATTR_PXN (1UL << 53)
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#define ATTR_XN (ATTR_PXN | ATTR_UXN)
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#define ATTR_CONTIGUOUS (1UL << 52)
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#define ATTR_DBM (1UL << 51)
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#define ATTR_nG (1 << 11)
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#define ATTR_AF (1 << 10)
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#define ATTR_SH(x) ((x) << 8)
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#define ATTR_SH_MASK ATTR_SH(3)
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#define ATTR_SH_NS 0 /* Non-shareable */
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#define ATTR_SH_OS 2 /* Outer-shareable */
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#define ATTR_SH_IS 3 /* Inner-shareable */
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#define ATTR_AP_RW_BIT (1 << 7)
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#define ATTR_AP(x) ((x) << 6)
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#define ATTR_AP_MASK ATTR_AP(3)
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#define ATTR_AP_RW (0 << 1)
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#define ATTR_AP_RO (1 << 1)
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#define ATTR_AP_USER (1 << 0)
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#define ATTR_NS (1 << 5)
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#define ATTR_IDX(x) ((x) << 2)
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#define ATTR_IDX_MASK (7 << 2)
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#define ATTR_DEFAULT (ATTR_AF | ATTR_SH(ATTR_SH_IS))
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#define ATTR_DESCR_MASK 3
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/* Level 0 table, 512GiB per entry */
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#define L0_SHIFT 39
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#define L0_SIZE (1ul << L0_SHIFT)
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#define L0_OFFSET (L0_SIZE - 1ul)
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#define L0_INVAL 0x0 /* An invalid address */
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/* 0x1 Level 0 doesn't support block translation */
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/* 0x2 also marks an invalid address */
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#define L0_TABLE 0x3 /* A next-level table */
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/* Level 1 table, 1GiB per entry */
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#define L1_SHIFT 30
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#define L1_SIZE (1 << L1_SHIFT)
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#define L1_OFFSET (L1_SIZE - 1)
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#define L1_INVAL L0_INVAL
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#define L1_BLOCK 0x1
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#define L1_TABLE L0_TABLE
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/* Level 2 table, 2MiB per entry */
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#define L2_SHIFT 21
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#define L2_SIZE (1 << L2_SHIFT)
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#define L2_OFFSET (L2_SIZE - 1)
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#define L2_INVAL L1_INVAL
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#define L2_BLOCK L1_BLOCK
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#define L2_TABLE L1_TABLE
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#define L2_BLOCK_MASK UINT64_C(0xffffffe00000)
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/* Level 3 table, 4KiB per entry */
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#define L3_SHIFT 12
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#define L3_SIZE (1 << L3_SHIFT)
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#define L3_OFFSET (L3_SIZE - 1)
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#define L3_SHIFT 12
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#define L3_INVAL 0x0
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/* 0x1 is reserved */
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/* 0x2 also marks an invalid address */
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#define L3_PAGE 0x3
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#define L0_ENTRIES_SHIFT 9
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#define L0_ENTRIES (1 << L0_ENTRIES_SHIFT)
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#define L0_ADDR_MASK (L0_ENTRIES - 1)
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#define Ln_ENTRIES_SHIFT 9
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#define Ln_ENTRIES (1 << Ln_ENTRIES_SHIFT)
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#define Ln_ADDR_MASK (Ln_ENTRIES - 1)
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#define Ln_TABLE_MASK ((1 << 12) - 1)
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#define pmap_l0_index(va) (((va) >> L0_SHIFT) & L0_ADDR_MASK)
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#define pmap_l1_index(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK)
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#define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK)
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#define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK)
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#endif /* !_MACHINE_PTE_H_ */
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/* End of pte.h */
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