745a40d78a
Set AP[2:0] and XN flags based on page attributes. PXN is not implemented as it seems to be available only in L1 descriptors on ARMv7. Set TEX, B, C flags based on memoryType: * B_MTR_UC is mapped to Strongly Ordered (TEX=0, B=0, C=0) * B_MTR_WC is mapped to Shareable Device Memory (TEX=0, B=1, C=0) * B_MTR_WT is mapped to Outer and Inner Write-Through, no Write-Allocate (TEX=0, B=0, C=1) * B_MTR_WB is mapped to Outer and Inner Write-Back, no Write-Allocate (TEx=0, B=1, C=1) * B_MTR_WP has no direct equivalent on the ARM so it's mapped as B_MTR_WB * default is Write-Back Implement ARMPagingMethod32Bit::AttributesToPageTableEntryFlags() for mapping from page attributes to AP[2:0] and XN flags. Implement ARMPagingMethod32Bit::PageTableEntryFlagsToAttributes() for the reverse mapping used in Query() and QueryInterrupt() i.e. recover page attributes from AP[2:0] and XN flags. Implement ARMPagingMethod32Bit::MemoryTypeToPageTableEntryFlags() fr mapping from memoryType to TEX, B, C flags. Implement ARMVMTranslationMap32Bit::Protect() which used to be commented out. Accessed and modified flags are not implemented yet, so no such flags are returned from Query() and QueryInterrupt(). Also because of this, we just invalidate TLB on any call to Protect() without checking whether the page has been accessed. Change-Id: I027af5c02bd6218d9f92a58044aeb26373e1956b Reviewed-on: https://review.haiku-os.org/c/haiku/+/5236 Reviewed-by: Adrien Destugues <pulkomandy@gmail.com> Reviewed-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com> Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
103 lines
3.1 KiB
C
103 lines
3.1 KiB
C
/*
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* Copyright 2010-2012 Haiku, Inc. All rights reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Francois Revol
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* Ithamar R. Adema, ithamar.adema@team-embedded.nl
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* Alexander von Gluck, kallisti5@unixzen.com
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*/
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#ifndef _ARCH_ARM_ARM_MMU_H
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#define _ARCH_ARM_ARM_MMU_H
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/*
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* generic arm mmu definitions
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*/
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/*
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* L1 defines for the page directory (page table walk methods)
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*/
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#define ARM_MMU_L1_TYPE_FAULT 0x0
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// MMU Fault
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// 31 2 10
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// | |00|
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#define ARM_MMU_L1_TYPE_SECTION 0x2
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// Single step table walk, 4096 entries
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// 1024K pages, 16K consumed
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// 31 20 19 12 11 10 9 8 5 432 10
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// | page table address | 0? | AP |0| domain |1CB|10|
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#define ARM_MMU_L1_TYPE_FINE 0x3
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// Three(?) step table walk, 1024 entries
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// 1K, 4K, 64K pages, 4K consumed
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// 31 12 11 9 8 5 432 10
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// | page table address | 0? | domain |100|11|
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#define ARM_MMU_L1_TYPE_COARSE 0x1
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// Two step table walk, 256 entries
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// 4K(Haiku), 64K pages, 1K consumed
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// 31 10 9 8 5 432 10
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// | page table address |0| domain |000|01|
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// the domain is not used so and the ? is implementation specified... have not
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// found it in the cortex A8 reference... so I set t to 0
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// page table must obviously be on multiple of 1KB
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#define ARM_MMU_L2_TYPE_LARGE 0x1
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#define ARM_MMU_L2_TYPE_SMALLNEW 0x2
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#define ARM_MMU_L2_TYPE_SMALLEXT 0x3
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#define ARM_MMU_L2_FLAG_XN 0x001
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#define ARM_MMU_L2_FLAG_B 0x004
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#define ARM_MMU_L2_FLAG_C 0x008
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#define ARM_MMU_L2_FLAG_AP0 0x010
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#define ARM_MMU_L2_FLAG_AP1 0x020
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#define ARM_MMU_L2_FLAG_TEX0 0x040
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#define ARM_MMU_L2_FLAG_TEX1 0x080
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#define ARM_MMU_L2_FLAG_TEX2 0x100
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#define ARM_MMU_L2_FLAG_AP2 0x200
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#define ARM_MMU_L2_FLAG_S 0x400
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#define ARM_MMU_L2_FLAG_NG 0x800
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#define ARM_MMU_L2_FLAG_AP_KRW 0x010
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// allow read and write for kernel only
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#define ARM_MMU_L2_FLAG_AP_RW 0x030
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// allow read and write for user and system
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#define ARM_MMU_L1_TABLE_ENTRY_COUNT 4096
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#define ARM_MMU_L1_TABLE_SIZE (ARM_MMU_L1_TABLE_ENTRY_COUNT \
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* sizeof(uint32))
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#define ARM_MMU_L2_COARSE_ENTRY_COUNT 256
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#define ARM_MMU_L2_COARSE_TABLE_SIZE (ARM_MMU_L2_COARSE_ENTRY_COUNT \
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* sizeof(uint32))
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#define ARM_MMU_L2_FINE_ENTRY_COUNT 1024
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#define ARM_MMU_L2_FINE_TABLE_SIZE (ARM_MMU_L2_FINE_ENTRY_COUNT \
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* sizeof(uint32))
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/*
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* definitions for CP15 r1
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*/
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#define CR_R1_MMU 0x1 // enable MMU
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#define CP_R1_XP 0x800000
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// if XP=0 then use backwards comaptible translation tables
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#define VADDR_TO_PDENT(va) ((va) >> 20)
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#define VADDR_TO_PTENT(va) (((va) & 0xff000) >> 12)
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#define VADDR_TO_PGOFF(va) ((va) & 0x0fff)
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#define ARM_PDE_ADDRESS_MASK 0xfffffc00
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#define ARM_PDE_TYPE_MASK 0x00000003
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#define ARM_PTE_ADDRESS_MASK 0xfffff000
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#define ARM_PTE_TYPE_MASK 0x00000003
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#define ARM_PTE_PROTECTION_MASK 0x00000231 // AP[2:0], XN
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#define ARM_PTE_MEMORY_TYPE_MASK 0x000001cc // TEX, B, C
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#endif /* _ARCH_ARM_ARM_MMU_H */
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