e02e12de8a
Probably only works under Haiku due to the new area flags. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12219 a95241bf-73f2-0310-859d-f6bbb57e9c96
271 lines
12 KiB
C
271 lines
12 KiB
C
/*
|
|
Copyright (c) 2002, Thomas Kurschel
|
|
|
|
|
|
Part of Radeon driver
|
|
|
|
Unsorted list of remaining Radeon registers
|
|
*/
|
|
|
|
|
|
#ifndef _RADEON_REGS_H
|
|
#define _RADEON_REGS_H
|
|
|
|
|
|
#define RADEON_AMCGPIO_A_REG 0x01a0
|
|
#define RADEON_AMCGPIO_EN_REG 0x01a8
|
|
#define RADEON_AMCGPIO_MASK 0x0194
|
|
#define RADEON_AMCGPIO_Y_REG 0x01a4
|
|
#define RADEON_ATTRDR 0x03c1 /* VGA */
|
|
#define RADEON_ATTRDW 0x03c0 /* VGA */
|
|
#define RADEON_ATTRX 0x03c0 /* VGA */
|
|
#define RADEON_AUX_SC_CNTL 0x1660
|
|
# define RADEON_AUX1_SC_EN (1 << 0)
|
|
# define RADEON_AUX1_SC_MODE_OR (0 << 1)
|
|
# define RADEON_AUX1_SC_MODE_NAND (1 << 1)
|
|
# define RADEON_AUX2_SC_EN (1 << 2)
|
|
# define RADEON_AUX2_SC_MODE_OR (0 << 3)
|
|
# define RADEON_AUX2_SC_MODE_NAND (1 << 3)
|
|
# define RADEON_AUX3_SC_EN (1 << 4)
|
|
# define RADEON_AUX3_SC_MODE_OR (0 << 5)
|
|
# define RADEON_AUX3_SC_MODE_NAND (1 << 5)
|
|
#define RADEON_AUX1_SC_BOTTOM 0x1670
|
|
#define RADEON_AUX1_SC_LEFT 0x1664
|
|
#define RADEON_AUX1_SC_RIGHT 0x1668
|
|
#define RADEON_AUX1_SC_TOP 0x166c
|
|
#define RADEON_AUX2_SC_BOTTOM 0x1680
|
|
#define RADEON_AUX2_SC_LEFT 0x1674
|
|
#define RADEON_AUX2_SC_RIGHT 0x1678
|
|
#define RADEON_AUX2_SC_TOP 0x167c
|
|
#define RADEON_AUX3_SC_BOTTOM 0x1690
|
|
#define RADEON_AUX3_SC_LEFT 0x1684
|
|
#define RADEON_AUX3_SC_RIGHT 0x1688
|
|
#define RADEON_AUX3_SC_TOP 0x168c
|
|
#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8
|
|
#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc
|
|
|
|
|
|
#define RADEON_CLR_CMP_CLR_3D 0x1a24
|
|
#define RADEON_CLR_CMP_CLR_DST 0x15c8
|
|
#define RADEON_CLR_CMP_CLR_SRC 0x15c4
|
|
#define RADEON_CLR_CMP_CNTL 0x15c0
|
|
# define RADEON_SRC_CMP_EQ_COLOR (4 << 0)
|
|
# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)
|
|
# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)
|
|
#define RADEON_CLR_CMP_MASK 0x15cc
|
|
# define RADEON_CLR_CMP_MSK 0xffffffff
|
|
#define RADEON_CLR_CMP_MASK_3D 0x1A28
|
|
#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c
|
|
#define RADEON_CONFIG_APER_0_BASE 0x0100
|
|
#define RADEON_CONFIG_APER_1_BASE 0x0104
|
|
#define RADEON_CONFIG_APER_SIZE 0x0108
|
|
#define RADEON_CONFIG_BONDS 0x00e8
|
|
#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114
|
|
#define RADEON_CONFIG_REG_1_BASE 0x010c
|
|
#define RADEON_CONFIG_REG_APER_SIZE 0x0110
|
|
#define RADEON_CONFIG_XSTRAP 0x00e4
|
|
#define RADEON_CONSTANT_COLOR_C 0x1d34
|
|
# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff
|
|
# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff
|
|
# define RADEON_CONSTANT_COLOR_ZERO 0x00000000
|
|
#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
|
|
#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
|
|
|
|
#define RADEON_TV_DAC_CNTL 0x088c
|
|
# define RADEON_TV_DAC_STD_MASK 0x0300
|
|
# define RADEON_TV_DAC_RDACPD (1 << 24)
|
|
# define RADEON_TV_DAC_GDACPD (1 << 25)
|
|
# define RADEON_TV_DAC_BDACPD (1 << 26)
|
|
|
|
#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820
|
|
#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824
|
|
#define RADEON_DISP_MISC_CNTL 0x0d00
|
|
# define RADEON_SOFT_RESET_GRPH_PP (1 << 0)
|
|
|
|
|
|
#define RADEON_DST_BRES_DEC 0x1630
|
|
#define RADEON_DST_BRES_ERR 0x1628
|
|
#define RADEON_DST_BRES_INC 0x162c
|
|
#define RADEON_DST_BRES_LNTH 0x1634
|
|
#define RADEON_DST_BRES_LNTH_SUB 0x1638
|
|
#define RADEON_DST_HEIGHT 0x1410
|
|
#define RADEON_DST_HEIGHT_WIDTH 0x143c
|
|
#define RADEON_DST_HEIGHT_WIDTH_8 0x158c
|
|
#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4
|
|
#define RADEON_DST_HEIGHT_Y 0x15a0
|
|
#define RADEON_DST_OFFSET 0x1404
|
|
#define RADEON_DST_PITCH 0x1408
|
|
#define RADEON_DST_PITCH_OFFSET_C 0x1c80
|
|
# define RADEON_PITCH_SHIFT 21
|
|
# define RADEON_DST_TILE_LINEAR (0 << 30)
|
|
# define RADEON_DST_TILE_MACRO (1 << 30)
|
|
# define RADEON_DST_TILE_MICRO (2 << 30)
|
|
# define RADEON_DST_TILE_BOTH (3 << 30)
|
|
#define RADEON_DST_WIDTH 0x140c
|
|
#define RADEON_DST_WIDTH_HEIGHT 0x1598
|
|
#define RADEON_DST_WIDTH_X 0x1588
|
|
#define RADEON_DST_WIDTH_X_INCY 0x159c
|
|
#define RADEON_DST_X 0x141c
|
|
#define RADEON_DST_X_SUB 0x15a4
|
|
#define RADEON_DST_X_Y 0x1594
|
|
#define RADEON_DST_Y 0x1420
|
|
#define RADEON_DST_Y_SUB 0x15a8
|
|
#define RADEON_DST_Y_X 0x1438
|
|
|
|
#define RADEON_FLUSH_1 0x1704
|
|
#define RADEON_FLUSH_2 0x1708
|
|
#define RADEON_FLUSH_3 0x170c
|
|
#define RADEON_FLUSH_4 0x1710
|
|
#define RADEON_FLUSH_5 0x1714
|
|
#define RADEON_FLUSH_6 0x1718
|
|
#define RADEON_FLUSH_7 0x171c
|
|
#define RADEON_FOG_3D_TABLE_START 0x1810
|
|
#define RADEON_FOG_3D_TABLE_END 0x1814
|
|
#define RADEON_FOG_3D_TABLE_DENSITY 0x181c
|
|
#define RADEON_FOG_TABLE_INDEX 0x1a14
|
|
#define RADEON_FOG_TABLE_DATA 0x1a18
|
|
|
|
#define RADEON_GENENB 0x03c3 /* VGA */
|
|
#define RADEON_GENFC_RD 0x03ca /* VGA */
|
|
#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */
|
|
#define RADEON_GENMO_RD 0x03cc /* VGA */
|
|
#define RADEON_GENMO_WT 0x03c2 /* VGA */
|
|
#define RADEON_GENS0 0x03c2 /* VGA */
|
|
#define RADEON_GENS1 0x03da /* VGA, 0x03ba */
|
|
|
|
#define RADEON_GRPH8_DATA 0x03cf /* VGA */
|
|
#define RADEON_GRPH8_IDX 0x03ce /* VGA */
|
|
#define RADEON_GUI_DEBUG0 0x16a0
|
|
#define RADEON_GUI_DEBUG1 0x16a4
|
|
#define RADEON_GUI_DEBUG2 0x16a8
|
|
#define RADEON_GUI_DEBUG3 0x16ac
|
|
#define RADEON_GUI_DEBUG4 0x16b0
|
|
#define RADEON_GUI_DEBUG5 0x16b4
|
|
#define RADEON_GUI_DEBUG6 0x16b8
|
|
#define RADEON_GUI_SCRATCH_REG0 0x15e0
|
|
#define RADEON_GUI_SCRATCH_REG1 0x15e4
|
|
#define RADEON_GUI_SCRATCH_REG2 0x15e8
|
|
#define RADEON_GUI_SCRATCH_REG3 0x15ec
|
|
#define RADEON_GUI_SCRATCH_REG4 0x15f0
|
|
#define RADEON_GUI_SCRATCH_REG5 0x15f4
|
|
#define RADEON_HOST_DATA0 0x17c0
|
|
#define RADEON_HOST_DATA1 0x17c4
|
|
#define RADEON_HOST_DATA2 0x17c8
|
|
#define RADEON_HOST_DATA3 0x17cc
|
|
#define RADEON_HOST_DATA4 0x17d0
|
|
#define RADEON_HOST_DATA5 0x17d4
|
|
#define RADEON_HOST_DATA6 0x17d8
|
|
#define RADEON_HOST_DATA7 0x17dc
|
|
#define RADEON_HOST_DATA_LAST 0x17e0
|
|
#define RADEON_HW_DEBUG 0x0128
|
|
#define RADEON_HW_DEBUG2 0x011c
|
|
|
|
#define RADEON_I2C_CNTL_1 0x0094
|
|
|
|
#define RADEON_LEAD_BRES_DEC 0x1608
|
|
#define RADEON_LEAD_BRES_LNTH 0x161c
|
|
#define RADEON_LEAD_BRES_LNTH_SUB 0x1624
|
|
#define RADEON_LVDS_PLL_CNTL 0x02d4
|
|
|
|
# define RADEON_HSYNC_DELAY_SHIFT 28
|
|
# define RADEON_HSYNC_DELAY_MASK (0xf << 28)
|
|
|
|
#define RADEON_MDGPIO_A_REG 0x01ac
|
|
#define RADEON_MDGPIO_EN_REG 0x01b0
|
|
#define RADEON_MDGPIO_MASK 0x0198
|
|
#define RADEON_MDGPIO_Y_REG 0x01b4
|
|
|
|
#define RADEON_MEM_STR_CNTL 0x0150
|
|
#define RADEON_MEM_VGA_RP_SEL 0x003c
|
|
#define RADEON_MEM_VGA_WP_SEL 0x0038
|
|
#define RADEON_MM_INDEX 0x0000
|
|
#define RADEON_MPLL_CNTL 0x000e /* PLL */
|
|
#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */
|
|
#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */
|
|
|
|
#define RADEON_N_VIF_COUNT 0x0248
|
|
|
|
#define RADEON_PCI_GART_PAGE 0x017c
|
|
#define RADEON_PLANE_3D_MASK_C 0x1d44
|
|
#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */
|
|
|
|
#define RADEON_SC_BOTTOM 0x164c
|
|
#define RADEON_SC_BOTTOM_RIGHT 0x16f0
|
|
#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c
|
|
#define RADEON_SC_LEFT 0x1640
|
|
#define RADEON_SC_RIGHT 0x1644
|
|
#define RADEON_SC_TOP 0x1648
|
|
#define RADEON_SC_TOP_LEFT 0x16ec
|
|
#define RADEON_SC_TOP_LEFT_C 0x1c88
|
|
# define RADEON_SC_SIGN_MASK_LO 0x8000
|
|
# define RADEON_SC_SIGN_MASK_HI 0x80000000
|
|
#define RADEON_SEQ8_DATA 0x03c5 /* VGA */
|
|
#define RADEON_SEQ8_IDX 0x03c4 /* VGA */
|
|
#define RADEON_SNAPSHOT_F_COUNT 0x0244
|
|
#define RADEON_SNAPSHOT_VH_COUNTS 0x0240
|
|
#define RADEON_SNAPSHOT_VIF_COUNT 0x024c
|
|
#define RADEON_SRC_OFFSET 0x15ac
|
|
#define RADEON_SRC_PITCH 0x15b0
|
|
#define RADEON_SRC_SC_BOTTOM 0x165c
|
|
#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4
|
|
#define RADEON_SRC_SC_RIGHT 0x1654
|
|
#define RADEON_SRC_X 0x1414
|
|
#define RADEON_SRC_X_Y 0x1590
|
|
#define RADEON_SRC_Y 0x1418
|
|
#define RADEON_SRC_Y_X 0x1434
|
|
#define RADEON_SURFACE_CNTL 0x0b00
|
|
# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
|
|
# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
|
|
# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
|
|
#define RADEON_SURFACE0_INFO 0x0b0c
|
|
#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
|
|
#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
|
|
#define RADEON_SURFACE1_INFO 0x0b1c
|
|
#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
|
|
#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
|
|
#define RADEON_SURFACE2_INFO 0x0b2c
|
|
#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
|
|
#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
|
|
#define RADEON_SURFACE3_INFO 0x0b3c
|
|
#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
|
|
#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
|
|
#define RADEON_SURFACE4_INFO 0x0b4c
|
|
#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
|
|
#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
|
|
#define RADEON_SURFACE5_INFO 0x0b5c
|
|
#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
|
|
#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
|
|
#define RADEON_SURFACE6_INFO 0x0b6c
|
|
#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
|
|
#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
|
|
#define RADEON_SURFACE7_INFO 0x0b7c
|
|
#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
|
|
#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
|
|
#define RADEON_SW_SEMAPHORE 0x013c
|
|
|
|
#define RADEON_TMDS_CRC 0x02a0
|
|
#define RADEON_TRAIL_BRES_DEC 0x1614
|
|
#define RADEON_TRAIL_BRES_ERR 0x160c
|
|
#define RADEON_TRAIL_BRES_INC 0x1610
|
|
#define RADEON_TRAIL_X 0x1618
|
|
#define RADEON_TRAIL_X_SUB 0x1620
|
|
|
|
#define RADEON_VGA_DDA_CONFIG 0x02e8 // Rage 128 reg
|
|
#define RADEON_VGA_DDA_ON_OFF 0x02ec
|
|
#define RADEON_VID_BUFFER_CONTROL 0x0900
|
|
#define RADEON_VIDEOMUX_CNTL 0x0190
|
|
|
|
#define RADEON_OVR_CLR 0x0230
|
|
#define RADEON_OVR_WID_LEFT_RIGHT 0x0234
|
|
#define RADEON_OVR_WID_TOP_BOTTOM 0x0238
|
|
|
|
|
|
#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */
|
|
#define RADEON_XCLK_CNTL 0x000d /* PLL */
|
|
#define RADEON_XDLL_CNTL 0x000c /* PLL */
|
|
#define RADEON_XPLL_CNTL 0x000b /* PLL */
|
|
|
|
|
|
#endif
|
|
|