2da9ebb7f3
* Caching these values could result in missed state changes. * We may want to re-implement later. * Highlights that all DP AUX communication is broken during my testing.
51 lines
1006 B
C
51 lines
1006 B
C
/*
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* Copyright 2012 Haiku, Inc. All rights reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Alexander von Gluck, kallisti5@unixzen.com
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*/
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#ifndef _DP_H
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#define _DP_H
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#include <Accelerant.h>
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#include "dp_raw.h"
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#include <GraphicsDefs.h>
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#include <OS.h>
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typedef struct {
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// Required configuration
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bool valid; // Is valid DP information
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uint32 auxPin; // Normally GPIO pin on GPU
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uint8 revision; // DP Revision from DPCD
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int laneCount;
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uint32 linkRate; // DP Link Speed 162000, 270000, 540000
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// Internal State information
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uint8 linkStatus[DP_LINK_STATUS_SIZE];
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uint8 trainingAttempts;
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uint8 trainingSet[4];
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int trainingReadInterval;
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} dp_info;
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typedef struct {
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uint16 address;
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uint8 request;
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uint8 reply;
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void* buffer;
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size_t size;
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} dp_aux_msg;
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uint32 dp_encode_link_rate(uint32 linkRate);
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uint32 dp_decode_link_rate(uint32 rawLinkRate);
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uint32 dp_get_pixel_clock_max(int linkRate, int laneCount, int bpp);
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#endif /* _DP_H */
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