0acc7a44b6
Unfinished. the TLB entries require setting 3 registers plus another field for the PID. Didn't yet decide how to store this in the page tables.
135 lines
2.9 KiB
C
135 lines
2.9 KiB
C
/*
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** Copyright 2003, Axel Dörfler, axeld@pinc-software.de. All rights reserved.
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** Distributed under the terms of the OpenBeOS License.
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*/
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#ifndef _KERNEL_ARCH_PPC_MMU_AMCC440_H
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#define _KERNEL_ARCH_PPC_MMU_AMCC440_H
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#include <SupportDefs.h>
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#include <string.h>
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#include <arch_cpu.h>
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/*** TLB - translation lookaside buffer ***/
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#define TLB_COUNT 64
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/** valid tlb length values */
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enum tlb_length {
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TLB_LENGTH_1kB = 0x0,
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TLB_LENGTH_4kB = 0x1,
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TLB_LENGTH_16kB = 0x2,
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TLB_LENGTH_64kB = 0x3,
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TLB_LENGTH_256kB = 0x4,
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TLB_LENGTH_1MB = 0x5,
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TLB_LENGTH_16MB = 0x7,
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TLB_LENGTH_256MB = 0x9,
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};
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#define TLB_V 0x200
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/** structure of a real TLB entry */
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//FIXME
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struct tlb_entry {
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// word 0
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uint32 effective_page_number : 22;
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uint32 valid : 1;
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uint32 translation_address_space : 1;
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uint32 page_size : 4;
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uint32 parity_1 : 4;
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//uint32 translation_id : 8;
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//FIXME:rest is Classic stuff
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// word 0
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// upper 32 bit
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uint32 page_index : 15; // BEPI, block effective page index
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uint32 _reserved0 : 4;
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uint32 length : 11;
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uint32 kernel_valid : 1; // Vs, Supervisor-state valid
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uint32 user_valid : 1; // Vp, User-state valid
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// lower 32 bit
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uint32 physical_block_number : 15; // BPRN
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uint32 write_through : 1; // WIMG
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uint32 caching_inhibited : 1;
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uint32 memory_coherent : 1;
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uint32 guarded : 1;
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uint32 _reserved1 : 1;
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uint32 protection : 2;
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tlb_entry()
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{
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Clear();
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}
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void SetVirtualAddress(void *address)
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{
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page_index = uint32(address) >> 17;
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}
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void SetPhysicalAddress(void *address)
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{
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physical_block_number = uint32(address) >> 17;
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}
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void Clear()
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{
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memset((void *)this, 0, sizeof(tlb_entry));
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}
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};
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#if 0 // XXX:Classic
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/*** PTE - page table entry ***/
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enum pte_protection {
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PTE_READ_ONLY = 3,
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PTE_READ_WRITE = 2,
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};
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struct page_table_entry {
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// upper 32 bit
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uint32 valid : 1;
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uint32 virtual_segment_id : 24;
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uint32 secondary_hash : 1;
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uint32 abbr_page_index : 6;
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// lower 32 bit
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uint32 physical_page_number : 20;
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uint32 _reserved0 : 3;
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uint32 referenced : 1;
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uint32 changed : 1;
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uint32 write_through : 1; // WIMG
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uint32 caching_inhibited : 1;
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uint32 memory_coherent : 1;
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uint32 guarded : 1;
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uint32 _reserved1 : 1;
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uint32 page_protection : 2;
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static uint32 PrimaryHash(uint32 virtualSegmentID, uint32 virtualAddress);
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static uint32 SecondaryHash(uint32 virtualSegmentID, uint32 virtualAddress);
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static uint32 SecondaryHash(uint32 primaryHash);
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};
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struct page_table_entry_group {
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struct page_table_entry entry[8];
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};
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extern void ppc_get_page_table(page_table_entry_group **_pageTable, size_t *_size);
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extern void ppc_set_page_table(page_table_entry_group *pageTable, size_t size);
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static inline segment_descriptor
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ppc_get_segment_register(void *virtualAddress)
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{
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return (segment_descriptor)get_sr(virtualAddress);
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}
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static inline void
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ppc_set_segment_register(void *virtualAddress, segment_descriptor segment)
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{
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set_sr(virtualAddress, *(uint32 *)&segment);
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}
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#endif
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#endif /* _KERNEL_ARCH_PPC_MMU_AMCC440_H */
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