309 lines
8.6 KiB
C
309 lines
8.6 KiB
C
/*
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* Copyright 2002-2007, Axel Dörfler, axeld@pinc-software.de. All rights reserved.
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* Distributed under the terms of the MIT License.
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*
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* Copyright 2001-2002, Travis Geiselbrecht. All rights reserved.
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* Distributed under the terms of the NewOS License.
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*/
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#ifndef _KERNEL_ARCH_x86_CPU_H
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#define _KERNEL_ARCH_x86_CPU_H
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#ifndef _ASSEMBLER
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#include <module.h>
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#include <arch/x86/descriptors.h>
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#endif // !_ASSEMBLER
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// MSR registers (possibly Intel specific)
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#define IA32_MSR_APIC_BASE 0x1b
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#define IA32_MSR_MTRR_CAPABILITIES 0xfe
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#define IA32_MSR_SYSENTER_CS 0x174
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#define IA32_MSR_SYSENTER_ESP 0x175
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#define IA32_MSR_SYSENTER_EIP 0x176
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#define IA32_MSR_MTRR_DEFAULT_TYPE 0x2ff
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#define IA32_MSR_MTRR_PHYSICAL_BASE_0 0x200
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#define IA32_MSR_MTRR_PHYSICAL_MASK_0 0x201
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// x86 features from cpuid eax 1, edx register
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#define IA32_FEATURE_FPU 0x00000001 // x87 fpu
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#define IA32_FEATURE_VME 0x00000002 // virtual 8086
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#define IA32_FEATURE_DE 0x00000004 // debugging extensions
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#define IA32_FEATURE_PSE 0x00000008 // page size extensions
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#define IA32_FEATURE_TSC 0x00000010 // rdtsc instruction
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#define IA32_FEATURE_MSR 0x00000020 // rdmsr/wrmsr instruction
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#define IA32_FEATURE_PAE 0x00000040 // extended 3 level page table addressing
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#define IA32_FEATURE_MCE 0x00000080 // machine check exception
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#define IA32_FEATURE_CX8 0x00000100 // cmpxchg8b instruction
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#define IA32_FEATURE_APIC 0x00000200 // local apic on chip
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#define IA32_FEATURE_SEP 0x00000800 // SYSENTER/SYSEXIT
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#define IA32_FEATURE_MTRR 0x00001000 // MTRR
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#define IA32_FEATURE_PGE 0x00002000 // paging global bit
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#define IA32_FEATURE_MCA 0x00004000 // machine check architecture
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#define IA32_FEATURE_CMOV 0x00008000 // cmov instruction
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#define IA32_FEATURE_PAT 0x00010000 // page attribute table
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#define IA32_FEATURE_PSE36 0x00020000 // page size extensions with 4MB pages
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#define IA32_FEATURE_PSN 0x00040000 // processor serial number
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#define IA32_FEATURE_CLFSH 0x00080000 // cflush instruction
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#define IA32_FEATURE_DS 0x00200000 // debug store
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#define IA32_FEATURE_ACPI 0x00400000 // thermal monitor and clock ctrl
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#define IA32_FEATURE_MMX 0x00800000 // mmx instructions
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#define IA32_FEATURE_FXSR 0x01000000 // FXSAVE/FXRSTOR instruction
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#define IA32_FEATURE_SSE 0x02000000 // SSE
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#define IA32_FEATURE_SSE2 0x04000000 // SSE2
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#define IA32_FEATURE_SS 0x08000000 // self snoop
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#define IA32_FEATURE_HTT 0x10000000 // hyperthreading
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#define IA32_FEATURE_TM 0x20000000 // thermal monitor
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#define IA32_FEATURE_PBE 0x80000000 // pending break enable
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// x86 features from cpuid eax 1, ecx register
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#define IA32_FEATURE_EXT_SSE3 0x00000001 // SSE3
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#define IA32_FEATURE_EXT_MONITOR 0x00000008 // MONITOR/MWAIT
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#define IA32_FEATURE_EXT_DSCPL 0x00000010 // CPL qualified debug store
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#define IA32_FEATURE_EXT_EST 0x00000080 // speedstep
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#define IA32_FEATURE_EXT_TM2 0x00000100 // thermal monitor 2
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#define IA32_FEATURE_EXT_CNXTID 0x00000400 // L1 context ID
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// x86 features from cpuid eax 0x80000001, edx register (AMD)
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// only care about the ones that are unique to this register
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#define IA32_FEATURE_AMD_EXT_SYSCALL (1<<11) // SYSCALL/SYSRET
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#define IA32_FEATURE_AMD_EXT_NX (1<<20) // no execute bit
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#define IA32_FEATURE_AMD_EXT_MMXEXT (1<<22) // mmx extensions
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#define IA32_FEATURE_AMD_EXT_FFXSR (1<<25) // fast FXSAVE/FXRSTOR
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#define IA32_FEATURE_AMD_EXT_RDTSCP (1<<27) // rdtscp instruction
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#define IA32_FEATURE_AMD_EXT_LONG (1<<29) // long mode
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#define IA32_FEATURE_AMD_EXT_3DNOWEXT (1<<30) // 3DNow! extensions
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#define IA32_FEATURE_AMD_EXT_3DNOW (1<<31) // 3DNow!
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// cr4 flags
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#define IA32_CR4_GLOBAL_PAGES (1UL << 7)
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// Memory type ranges
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#define IA32_MTR_UNCACHED 0
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#define IA32_MTR_WRITE_COMBINING 1
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#define IA32_MTR_WRITE_THROUGH 4
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#define IA32_MTR_WRITE_PROTECTED 5
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#define IA32_MTR_WRITE_BACK 6
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// iframe types
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#define IFRAME_TYPE_SYSCALL 0x1
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#define IFRAME_TYPE_OTHER 0x2
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#define IFRAME_TYPE_MASK 0xf
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#ifndef _ASSEMBLER
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typedef struct x86_optimized_functions {
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void (*memcpy)(void* dest, const void* source, size_t count);
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void* memcpy_end;
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} x86_optimized_functions;
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typedef struct x86_cpu_module_info {
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module_info info;
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uint32 (*count_mtrrs)(void);
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void (*init_mtrrs)(void);
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void (*set_mtrr)(uint32 index, uint64 base, uint64 length, uint8 type);
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status_t (*get_mtrr)(uint32 index, uint64 *_base, uint64 *_length,
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uint8 *_type);
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void (*get_optimized_functions)(x86_optimized_functions* functions);
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} x86_cpu_module_info;
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struct tss {
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uint16 prev_task;
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uint16 unused0;
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uint32 sp0;
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uint32 ss0;
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uint32 sp1;
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uint32 ss1;
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uint32 sp2;
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uint32 ss2;
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uint32 cr3;
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uint32 eip, eflags, eax, ecx, edx, ebx, esp, ebp, esi, edi;
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uint32 es, cs, ss, ds, fs, gs;
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uint32 ldt_seg_selector;
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uint16 unused1;
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uint16 io_map_base;
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};
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struct iframe {
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uint32 type; // iframe type
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uint32 gs;
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uint32 fs;
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uint32 es;
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uint32 ds;
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uint32 edi;
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uint32 esi;
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uint32 ebp;
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uint32 esp;
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uint32 ebx;
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uint32 edx;
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uint32 ecx;
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uint32 eax;
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uint32 orig_eax;
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uint32 orig_edx;
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uint32 vector;
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uint32 error_code;
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uint32 eip;
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uint32 cs;
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uint32 flags;
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uint32 user_esp;
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uint32 user_ss;
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};
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// features
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enum x86_feature_type {
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FEATURE_COMMON = 0, // cpuid eax=1, ecx register
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FEATURE_EXT, // cpuid eax=1, edx register
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FEATURE_EXT_AMD, // cpuid eax=0x80000001, edx register (AMD)
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FEATURE_NUM
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};
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enum x86_vendors {
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VENDOR_INTEL = 0,
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VENDOR_AMD,
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VENDOR_CYRIX,
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VENDOR_UMC,
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VENDOR_NEXGEN,
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VENDOR_CENTAUR,
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VENDOR_RISE,
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VENDOR_TRANSMETA,
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VENDOR_NSC,
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VENDOR_NUM,
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VENDOR_UNKNOWN,
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};
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typedef struct arch_cpu_info {
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// saved cpu info
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enum x86_vendors vendor;
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enum x86_feature_type feature[FEATURE_NUM];
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char model_name[49];
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const char *vendor_name;
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int type;
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int family;
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int extended_family;
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int stepping;
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int model;
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int extended_model;
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char feature_string[256];
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// local TSS for this cpu
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struct tss tss;
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struct tss double_fault_tss;
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} arch_cpu_info;
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define nop() __asm__ ("nop"::)
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struct arch_thread;
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void __x86_setup_system_time(uint32 cv_factor);
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void i386_context_switch(struct arch_thread *old_state, struct arch_thread *new_state, addr_t new_pgdir);
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void x86_userspace_thread_exit(void);
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void x86_end_userspace_thread_exit(void);
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void x86_enter_userspace(addr_t entry, addr_t stackTop);
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void i386_set_tss_and_kstack(addr_t kstack);
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void i386_switch_stack_and_call(addr_t stack, void (*func)(void *), void *arg);
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void i386_swap_pgdir(addr_t new_pgdir);
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void i386_fnsave(void *fpu_state);
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void i386_fxsave(void *fpu_state);
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void i386_frstor(const void *fpu_state);
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void i386_fxrstor(const void *fpu_state);
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void i386_fnsave_swap(void *old_fpu_state, const void *new_fpu_state);
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void i386_fxsave_swap(void *old_fpu_state, const void *new_fpu_state);
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uint32 x86_read_ebp();
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uint32 x86_read_cr0();
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void x86_write_cr0(uint32 value);
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uint32 x86_read_cr4();
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void x86_write_cr4(uint32 value);
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uint64 x86_read_msr(uint32 registerNumber);
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void x86_write_msr(uint32 registerNumber, uint64 value);
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void x86_set_task_gate(int32 n, int32 segment);
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uint32 x86_count_mtrrs(void);
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void x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type);
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status_t x86_get_mtrr(uint32 index, uint64 *_base, uint64 *_length, uint8 *_type);
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bool x86_check_feature(uint32 feature, enum x86_feature_type type);
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#define read_cr3(value) \
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__asm__("movl %%cr3,%0" : "=r" (value))
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#define write_cr3(value) \
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__asm__("movl %0,%%cr3" : : "r" (value))
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#define read_dr3(value) \
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__asm__("movl %%dr3,%0" : "=r" (value))
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#define write_dr3(value) \
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__asm__("movl %0,%%dr3" : : "r" (value))
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#define invalidate_TLB(va) \
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__asm__("invlpg (%0)" : : "r" (va))
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#define wbinvd() \
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__asm__("wbinvd")
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#define out8(value,port) \
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__asm__ ("outb %%al,%%dx" : : "a" (value), "d" (port))
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#define out16(value,port) \
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__asm__ ("outw %%ax,%%dx" : : "a" (value), "d" (port))
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#define out32(value,port) \
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__asm__ ("outl %%eax,%%dx" : : "a" (value), "d" (port))
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#define in8(port) ({ \
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uint8 _v; \
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__asm__ volatile ("inb %%dx,%%al" : "=a" (_v) : "d" (port)); \
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_v; \
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})
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#define in16(port) ({ \
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uint16 _v; \
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__asm__ volatile ("inw %%dx,%%ax":"=a" (_v) : "d" (port)); \
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_v; \
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})
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#define in32(port) ({ \
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uint32 _v; \
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__asm__ volatile ("inl %%dx,%%eax":"=a" (_v) : "d" (port)); \
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_v; \
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})
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#define out8_p(value,port) \
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__asm__ ("outb %%al,%%dx\n" \
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"\tjmp 1f\n" \
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"1:\tjmp 1f\n" \
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"1:" : : "a" (value), "d" (port))
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#define in8_p(port) ({ \
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uint8 _v; \
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__asm__ volatile ("inb %%dx,%%al\n" \
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"\tjmp 1f\n" \
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"1:\tjmp 1f\n" \
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"1:" : "=a" (_v) : "d" (port)); \
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_v; \
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})
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extern segment_descriptor *gGDT;
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#ifdef __cplusplus
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} // extern "C" {
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#endif
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#endif // !_ASSEMBLER
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#endif /* _KERNEL_ARCH_x86_CPU_H */
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