565 lines
11 KiB
C
565 lines
11 KiB
C
/*
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** Copyright 2003-2004, Axel Dörfler, axeld@pinc-software.de. All rights reserved.
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** Distributed under the terms of the MIT License.
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*/
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#ifndef _KERNEL_ARCH_M68K_CPU_H
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#define _KERNEL_ARCH_M68K_CPU_H
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#ifndef _ASSEMBLER
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#include <arch/m68k/arch_thread_types.h>
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#include <kernel.h>
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#endif // !_ASSEMBLER
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#define CPU_MAX_CACHE_LEVEL 8
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#define CACHE_LINE_SIZE 16
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#define set_ac()
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#define clear_ac()
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#define SR_IP_MASK 0x0700
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#define SR_S 0x2000
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#define M68K_SR_S 13
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#define M68K_SR_T_MASK 0xC000
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#define M68K_SR_T0 14
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#define M68K_SR_T1 15
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#ifndef _ASSEMBLER
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/* 68k has many different possible stack frames, differentiated by a 4 bit number,
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* but they also depend on the cpu type.
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* cf. mint/sys/arch/check_exc.h
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*/
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/* definitions for special status word */
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// 020 as well
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struct mc68030_ssw {
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uint16 fc:1;
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uint16 fb:1;
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uint16 rc:1;
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uint16 rb:1;
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uint16 :3;
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uint16 df:1;
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uint16 rm:1;
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uint16 rw:1;
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uint16 size:2;
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uint16 :1;
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uint16 as:3;
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} _PACKED;
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struct mc68040_ssw {
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uint16 cp:1;
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uint16 cu:1;
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uint16 ct:1;
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uint16 cm:1;
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uint16 ma:1;
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uint16 atc:1;
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uint16 lk:1;
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uint16 rw:1;
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uint16 :1;
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uint16 size:2;
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uint16 tt:2;
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uint16 tm:3;
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} _PACKED;
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struct mc68060_fslw {
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uint32 :4;
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uint32 ma:1;
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uint32 :1;
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uint32 lk:1;
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uint32 rw:2; //XXX ??
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uint32 size:2;
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uint32 tt:2;
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uint32 tm:2;
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uint32 io:1;
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uint32 pbe:1;
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uint32 sbe:1;
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uint32 pta:1;
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uint32 ptb:1;
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uint32 il:1;
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uint32 pf:1;
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uint32 sb:1;
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uint32 wp:1;
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uint32 twe:1;
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uint32 re:1;
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uint32 we:1;
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uint32 ttr:1;
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uint32 bpe:1;
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uint32 :1;
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uint32 see:1;
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} _PACKED;
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/* raw exception frames */
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struct mc680x0_type_0_frame {
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uint16 sr;
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addr_t pc;
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uint16 type:4;
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uint16 vector:12;
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};
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struct mc680x0_type_1_frame {
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uint16 sr;
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addr_t pc;
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uint16 type:4;
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uint16 vector:12;
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};
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struct mc680x0_type_2_frame {
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uint16 sr;
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addr_t pc;
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uint16 type:4;
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uint16 vector:12;
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addr_t instruction_address;
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};
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struct mc680x0_type_3_frame {
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uint16 sr;
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addr_t pc;
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uint16 type:4;
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uint16 vector:12;
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addr_t effective_address;
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};
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struct mc68040_type_7_frame {
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uint16 sr;
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addr_t pc;
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uint16 type:4;
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uint16 vector:12;
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addr_t effective_address;
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struct mc68040_ssw ssw;
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// write-back status
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uint16 wb3s;
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uint16 wb2s;
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uint16 wb1s;
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addr_t fault_address;
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addr_t wb3a;
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uint32 wb3d;
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addr_t wb2a;
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uint32 wb2d;
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addr_t wb1a;
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uint32 wb1d; // also pd0
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uint32 pd1;
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uint32 pd2;
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uint32 pd3;
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};
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struct mc680x0_type_9_frame {
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uint16 sr;
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addr_t pc;
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uint16 type:4;
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uint16 vector:12;
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addr_t instruction_address;
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uint16 intregs[4];
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};
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struct mc68030_type_a_frame {
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uint16 sr;
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addr_t pc;
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uint16 type:4;
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uint16 vector:12;
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uint16 intreg1;
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struct mc68030_ssw ssw;
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uint16 instpipe_c;
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uint16 instpipe_b;
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addr_t fault_address;
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uint16 intregs2[2];
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uint32 dataout;
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uint16 intregs3[2];
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};
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struct mc68030_type_b_frame {
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uint16 sr;
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addr_t pc;
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uint16 type:4;
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uint16 vector:12;
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uint16 intreg1;
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struct mc68030_ssw ssw;
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uint16 instpipe_c;
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uint16 instpipe_b;
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addr_t fault_address;
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uint16 intregs2[2];
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uint32 dataout;
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uint16 intregs3[4];
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uint32 stbaddr;
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uint16 intregs4[2];
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uint32 datain;
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uint16 intregs5[3];
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uint16 intinfo;
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uint16 intregs6[18];
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};
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//XXX: add 060 frames
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struct mc680x0_frame {
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union {
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struct {
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uint16 sr;
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addr_t pc;
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uint16 type:4;
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uint16 vector:12;
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};
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struct mc680x0_type_0_frame type_0;
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struct mc680x0_type_1_frame type_1;
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struct mc680x0_type_3_frame type_3;
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struct mc680x0_type_2_frame type_2;
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struct mc68040_type_7_frame type_7;
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struct mc680x0_type_9_frame type_9;
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struct mc68030_type_a_frame type_a;
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struct mc68030_type_b_frame type_b;
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// XXX: add 060 frames
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};
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};
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struct mc680x0_null_fpu_state {
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uint8 version; // 0
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uint8 type; // undefined
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uint16 dummy;
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};
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struct mc680x0_type_00_fpu_state {
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uint8 version;
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uint8 type; // 0
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uint16 dummy;
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};
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struct mc680x0_type_28_fpu_state {
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uint8 version;
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uint8 type; // 0x28
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uint16 dummy;
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// XXX: replace dummies
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uint32 dummies[0x28/4];
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};
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struct mc680x0_type_60_fpu_state {
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uint8 version;
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uint8 type; // 0x60
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uint16 dummy;
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// XXX: replace dummies
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uint32 dummies[0x60/4];
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};
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//XXX: those are 040, add others
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// biggest known:
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struct mc68882_type_d4_fpu_state {
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uint8 version;
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uint8 type; // 0xd4
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uint16 dummy;
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// XXX: replace dummies
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uint32 dummies[0xd4/4];
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};
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struct mc680x0_fpu_state {
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union {
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struct {
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uint8 version;
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uint8 type; // 0x60
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uint16 dummy;
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};
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struct mc680x0_null_fpu_state null;
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struct mc680x0_type_00_fpu_state type_00;
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struct mc680x0_type_28_fpu_state type_28;
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struct mc680x0_type_60_fpu_state type_60;
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struct mc68882_type_d4_fpu_state type_d4;
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};
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};
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// 96-bit format
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struct mc680x0_fp_data_reg {
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uint8 data[12];
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};
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struct mc680x0_fp_control_regs {
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uint32 fpcr;
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uint32 fpsr;
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uint32 fpiar;
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};
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#warning M68K: check for missing regs/movem
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struct iframe {
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/* fpu data registers */
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#warning M68K: sizeof(fp*)
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struct mc680x0_fp_data_reg fp[8];
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/* fpu control registers */
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struct mc680x0_fp_control_regs fpc;
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/* fpu state */
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struct mc680x0_fpu_state fpu;
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/* data and address registers */
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uint32 d[8];
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uint32 a[7];
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/* cpu exception frame, including sr, pc, format and vector */
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struct mc680x0_frame cpu;
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/* uint32 vector;
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uint32 srr0;
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uint32 srr1;
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uint32 dar;
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uint32 dsisr;
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uint32 lr;
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uint32 cr;
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uint32 xer;
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uint32 ctr;
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uint32 fpscr;
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uint32 r31;
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uint32 r30;
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uint32 r29;
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uint32 r28;
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uint32 r27;
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uint32 r26;
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uint32 r25;
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uint32 r24;
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uint32 r23;
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uint32 r22;
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uint32 r21;
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uint32 r20;
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uint32 r19;
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uint32 r18;
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uint32 r17;
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uint32 r16;
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uint32 r15;
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uint32 r14;
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uint32 r13;
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uint32 r12;
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uint32 r11;
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uint32 r10;
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uint32 r9;
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uint32 r8;
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uint32 r7;
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uint32 r6;
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uint32 r5;
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uint32 r4;
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uint32 r3;
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uint32 r2;
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uint32 r1;
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uint32 r0;
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double f31;
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double f30;
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double f29;
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double f28;
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double f27;
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double f26;
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double f25;
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double f24;
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double f23;
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double f22;
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double f21;
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double f20;
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double f19;
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double f18;
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double f17;
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double f16;
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double f15;
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double f14;
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double f13;
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double f12;
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double f11;
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double f10;
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double f9;
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double f8;
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double f7;
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double f6;
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double f5;
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double f4;
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double f3;
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double f2;
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double f1;
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double f0;*/
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} _PACKED;
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#if 0 /* ppc */
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enum machine_state {
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MSR_EXCEPTIONS_ENABLED = 1L << 15, // EE
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MSR_PRIVILEGE_LEVEL = 1L << 14, // PR
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MSR_FP_AVAILABLE = 1L << 13, // FP
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MSR_MACHINE_CHECK_ENABLED = 1L << 12, // ME
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MSR_EXCEPTION_PREFIX = 1L << 6, // IP
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MSR_INST_ADDRESS_TRANSLATION = 1L << 5, // IR
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MSR_DATA_ADDRESS_TRANSLATION = 1L << 4, // DR
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};
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//struct block_address_translation;
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#endif
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typedef struct arch_cpu_info {
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int null;
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} arch_cpu_info;
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if 0
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//PPC stuff
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extern uint32 get_sdr1(void);
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extern void set_sdr1(uint32 value);
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extern uint32 get_sr(void *virtualAddress);
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extern void set_sr(void *virtualAddress, uint32 value);
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extern uint32 get_msr(void);
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extern uint32 set_msr(uint32 value);
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extern uint32 get_pvr(void);
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extern void set_ibat0(struct block_address_translation *bat);
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extern void set_ibat1(struct block_address_translation *bat);
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extern void set_ibat2(struct block_address_translation *bat);
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extern void set_ibat3(struct block_address_translation *bat);
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extern void set_dbat0(struct block_address_translation *bat);
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extern void set_dbat1(struct block_address_translation *bat);
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extern void set_dbat2(struct block_address_translation *bat);
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extern void set_dbat3(struct block_address_translation *bat);
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extern void get_ibat0(struct block_address_translation *bat);
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extern void get_ibat1(struct block_address_translation *bat);
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extern void get_ibat2(struct block_address_translation *bat);
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extern void get_ibat3(struct block_address_translation *bat);
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extern void get_dbat0(struct block_address_translation *bat);
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extern void get_dbat1(struct block_address_translation *bat);
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extern void get_dbat2(struct block_address_translation *bat);
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extern void get_dbat3(struct block_address_translation *bat);
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extern void reset_ibats(void);
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extern void reset_dbats(void);
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#endif
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//extern void sethid0(unsigned int val);
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//extern unsigned int getl2cr(void);
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//extern void setl2cr(unsigned int val);
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extern long long get_time_base(void);
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void __m68k_setup_system_time(vint32 *cvFactor);
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// defined in libroot: os/arch/system_time.c
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int64 __m68k_get_time_base(void);
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// defined in libroot: os/arch/system_time_asm.S
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extern void m68k_context_switch(void **_oldStackPointer, void *newStackPointer);
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extern bool m68k_set_fault_handler(addr_t *handlerLocation, addr_t handler)
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__attribute__((noinline));
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extern bool m68k_is_hw_register_readable(addr_t address);
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extern bool m68k_is_hw_register_writable(addr_t address, uint16 value);
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// defined in kernel: arch/m68k/cpu_asm.S
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static inline void
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arch_cpu_idle(void)
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{
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// TODO: M68K CPU idle call
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// there isn't really any insn for this. Maybe NOP/FNOP?
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// TODO: make a 060 module using LPSTOP
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//asm volatile ("lpstop");
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}
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static inline void
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arch_cpu_pause(void)
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{
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// TODO: M68K STOP call
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// the problem is STOP wants an immediate to put into SR
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// but we don't want to overwrite it.
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//asm volatile("stop #0" : : : "memory");
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}
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#ifdef __cplusplus
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}
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#endif
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struct m68k_cpu_ops {
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void (*flush_insn_pipeline)(void);
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void (*flush_atc_all)(void);
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void (*flush_atc_user)(void);
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void (*flush_atc_addr)(addr_t addr);
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void (*flush_dcache)(addr_t address, size_t len);
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void (*flush_icache)(addr_t address, size_t len);
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void (*idle)(void);
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};
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extern struct m68k_cpu_ops cpu_ops;
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//#define
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#if 0
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#define eieio() asm volatile("eieio")
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#define isync() asm volatile("isync")
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#define tlbsync() asm volatile("tlbsync")
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#define ppc_sync() asm volatile("sync")
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#define tlbia() asm volatile("tlbia")
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#define tlbie(addr) asm volatile("tlbie %0" :: "r" (addr))
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#endif
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#if 0
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// XXX: not used: we just use decimal chip number, like 68030
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// m68k processor version.
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enum m68k_processor_version {
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/* those two we don't support */
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CPU_68000 = 0x0000,
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CPU_68010 = 0x0001,
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/* maybe with a pmmu and fpu */
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CPU_68020 = 0x0002,
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/* should work */
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CPU_68030 = 0x0003,
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CPU_68040 = 0x0004,
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CPU_68060 = 0x0006,
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/* mask */
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CPU_MASK = 0x000F
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};
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enum m68k_fpu_version {
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/* we don't support */
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FPU_NONE = 0x0000,
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FPU_68881 = 0x0010,
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FPU_68882 = 0x0020,
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FPU_030 = 0x0030,
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FPU_040 = 0x0040,
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FPU_060 = 0x0060,
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FPU_MASK = 0x00F0
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};
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enum m68k_mmu_version {
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MMU_NONE = 0x0000,
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MMU_68551 = 0x0100,
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MMU_68030 = 0x0300,
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MMU_68040 = 0x0400,
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MMU_68060 = 0x0600,
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MMU_MASK = 0x0F00
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};
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#endif
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extern int arch_cpu_type;
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extern int arch_fpu_type;
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extern int arch_mmu_type;
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extern int arch_platform;
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extern int arch_machine;
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/*
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Use of (some) special purpose registers.
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XXX: those regs aren't implemented/accessed the same way on different cpus...
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SRP[63-32]: current Thread*
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SRP[31-0] :
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CAAR : can we use it ??
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MSP :
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PPC:
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SPRG0: per CPU physical address pointer to an ppc_cpu_exception_context
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structure
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SPRG1: scratch
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SPRG2: current Thread*
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SPRG3: TLS base pointer (only for userland threads)
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*/
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#endif // !_ASSEMBLER
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#endif /* _KERNEL_ARCH_PPC_CPU_H */
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