a513041013
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@5919 a95241bf-73f2-0310-859d-f6bbb57e9c96
302 lines
11 KiB
C
302 lines
11 KiB
C
/* NM registers definitions and macros for access to */
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//old:
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/* PCI_config_space */
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#define NMCFG_DEVID 0x00
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#define NMCFG_DEVCTRL 0x04
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#define NMCFG_CLASS 0x08
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#define NMCFG_HEADER 0x0c
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#define NMCFG_NMBASE2 0x10
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#define NMCFG_NMBASE1 0x14
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#define NMCFG_NMBASE3 0x18 // >= MYST
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#define NMCFG_SUBSYSIDR 0x2c // >= MYST
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#define NMCFG_ROMBASE 0x30
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#define NMCFG_CAP_PTR 0x34 // >= MIL2
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#define NMCFG_INTCTRL 0x3c
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#define NMCFG_OPTION 0x40
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#define NMCFG_NM_INDEX 0x44
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#define NMCFG_NM_DATA 0x48
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#define NMCFG_SUBSYSIDW 0x4c // >= MYST
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#define NMCFG_OPTION2 0x50 // >= G100
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#define NMCFG_OPTION3 0x54 // >= G400
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#define NMCFG_OPTION4 0x58 // >= G450
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#define NMCFG_PM_IDENT 0xdc // >= G100
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#define NMCFG_PM_CSR 0xe0 // >= G100
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#define NMCFG_AGP_IDENT 0xf0 // >= MIL2
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#define NMCFG_AGP_STS 0xf4 // >= MIL2
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#define NMCFG_AGP_CMD 0xf8 // >= MIL2
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//end old.
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/* neomagic ISA direct registers */
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/* VGA standard registers: */
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#define NMISA8_ATTRINDW 0x03c0
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#define NMISA8_ATTRINDR 0x03c1
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#define NMISA8_ATTRDATW 0x03c0
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#define NMISA8_ATTRDATR 0x03c1
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#define NMISA8_SEQIND 0x03c4
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#define NMISA8_SEQDAT 0x03c5
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#define NMISA16_SEQIND 0x03c4
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#define NMISA8_CRTCIND 0x03d4
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#define NMISA8_CRTCDAT 0x03d5
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#define NMISA16_CRTCIND 0x03d4
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#define NMISA8_GRPHIND 0x03ce
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#define NMISA8_GRPHDAT 0x03cf
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#define NMISA16_GRPHIND 0x03ce
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/* neomagic PCI direct registers */
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#define NM2PCI8_SEQIND 0x03c4
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#define NM2PCI8_SEQDAT 0x03c5
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#define NM2PCI16_SEQIND 0x03c4
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#define NM2PCI8_GRPHIND 0x03ce
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#define NM2PCI8_GRPHDAT 0x03cf
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#define NM2PCI16_GRPHIND 0x03ce
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/* neomagic ISA GENERAL direct registers */
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/* VGA standard registers: */
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#define NMISA8_MISCW 0x03c2
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#define NMISA8_MISCR 0x03cc
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#define NMISA8_INSTAT1 0x03da
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/* neomagic ISA (DAC) COLOR direct registers (VGA palette RAM) */
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/* VGA standard registers: */
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#define NMISA8_PALMASK 0x03c6
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#define NMISA8_PALINDR 0x03c7
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#define NMISA8_PALINDW 0x03c8
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#define NMISA8_PALDATA 0x03c9
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/* neomagic ISA CRTC indexed registers */
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/* VGA standard registers: */
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#define NMCRTCX_HTOTAL 0x00
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#define NMCRTCX_HDISPE 0x01
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#define NMCRTCX_HBLANKS 0x02
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#define NMCRTCX_HBLANKE 0x03
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#define NMCRTCX_HSYNCS 0x04
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#define NMCRTCX_HSYNCE 0x05
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#define NMCRTCX_VTOTAL 0x06
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#define NMCRTCX_OVERFLOW 0x07
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#define NMCRTCX_PRROWSCN 0x08
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#define NMCRTCX_MAXSCLIN 0x09
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#define NMCRTCX_VGACURCTRL 0x0a
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#define NMCRTCX_FBSTADDH 0x0c
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#define NMCRTCX_FBSTADDL 0x0d
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#define NMCRTCX_VSYNCS 0x10
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#define NMCRTCX_VSYNCE 0x11
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#define NMCRTCX_VDISPE 0x12
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#define NMCRTCX_PITCHL 0x13
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#define NMCRTCX_VBLANKS 0x15
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#define NMCRTCX_VBLANKE 0x16
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#define NMCRTCX_MODECTL 0x17
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#define NMCRTCX_LINECOMP 0x18
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/* NeoMagic specific registers: */
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#define NMCRTCX_VEXT 0x70 /* >= NM2200 */
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/* neomagic ISA SEQUENCER indexed registers */
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/* VGA standard registers: */
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#define NMSEQX_RESET 0x00
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#define NMSEQX_CLKMODE 0x01
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#define NMSEQX_MEMMODE 0x04
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/* NeoMagic BES registers: (> NM2070) (accessible via mapped I/O: >= NM2097) */
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#define NMSEQX_BESCTRL2 0x08
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#define NMSEQX_0x09 0x09 //??
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#define NMSEQX_0x0a 0x0a //??
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#define NMSEQX_BUF2ORGL 0x0c
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#define NMSEQX_BUF2ORGM 0x0d
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#define NMSEQX_BUF2ORGH 0x0e
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#define NMSEQX_VSCOORD1L 0x14 /* >= NM2200(?), so clipping done via buffer startadress instead */
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#define NMSEQX_VSCOORD2L 0x15 /* >= NM2200(?), so clipping done via buffer startadress instead */
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#define NMSEQX_VSCOORD21H 0x16 /* >= NM2200(?), so clipping done via buffer startadress instead */
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#define NMSEQX_HSCOORD1L 0x17 /* >= NM2200(?), so clipping done via buffer startadress instead */
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#define NMSEQX_HSCOORD2L 0x18 /* >= NM2200(?), so clipping done via buffer startadress instead */
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#define NMSEQX_HSCOORD21H 0x19 /* >= NM2200(?), so clipping done via buffer startadress instead */
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#define NMSEQX_BUF2PITCHL 0x1a
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#define NMSEQX_BUF2PITCHH 0x1b
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#define NMSEQX_0x1c 0x1c //??
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#define NMSEQX_0x1d 0x1d //??
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#define NMSEQX_0x1e 0x1e //??
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#define NMSEQX_0x1f 0x1f //??
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/* neomagic ISA ATTRIBUTE indexed registers */
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/* VGA standard registers: */
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#define NMATBX_MODECTL 0x10
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#define NMATBX_OSCANCOLOR 0x11
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#define NMATBX_COLPLANE_EN 0x12
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#define NMATBX_HORPIXPAN 0x13
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#define NMATBX_COLSEL 0x14
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/* neomagic ISA GRAPHICS indexed registers */
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/* VGA standard registers: */
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#define NMGRPHX_ENSETRESET 0x01
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#define NMGRPHX_DATAROTATE 0x03
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#define NMGRPHX_READMAPSEL 0x04
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#define NMGRPHX_MODE 0x05
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#define NMGRPHX_MISC 0x06
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#define NMGRPHX_BITMASK 0x08
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/* NeoMagic specific registers: */
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#define NMGRPHX_GRPHXLOCK 0x09
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#define NMGRPHX_GENLOCK 0x0a
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#define NMGRPHX_FBSTADDE 0x0e
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#define NMGRPHX_CRTC_PITCHE 0x0f
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#define NMGRPHX_IFACECTRL 0x11
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#define NMGRPHX_PANELCTRL1 0x20
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#define NMGRPHX_PANELTYPE 0x21
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#define NMGRPHX_PANELCTRL2 0x25
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#define NMGRPHX_PANELVCENT1 0x28
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#define NMGRPHX_PANELVCENT2 0x29
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#define NMGRPHX_PANELVCENT3 0x2a
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#define NMGRPHX_PANELCTRL3 0x30 /* > NM2070 */
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#define NMGRPHX_PANELVCENT4 0x32 /* > NM2070 */
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#define NMGRPHX_PANELHCENT1 0x33 /* > NM2070 */
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#define NMGRPHX_PANELHCENT2 0x34 /* > NM2070 */
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#define NMGRPHX_PANELHCENT3 0x35 /* > NM2070 */
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#define NMGRPHX_PANELHCENT4 0x36 /* >= NM2160 */
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#define NMGRPHX_PANELVCENT5 0x37 /* >= NM2200 */
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#define NMGRPHX_PANELHCENT5 0x38 /* >= NM2200 */
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#define NMGRPHX_CURCTRL 0x82
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#define NMGRPHX_COLDEPTH 0x90
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/* (NeoMagic pixelPLL set C registers) */
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#define NMGRPHX_PLLC_NL 0x9b
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#define NMGRPHX_PLLC_NH 0x8f /* >= NM2200 */
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#define NMGRPHX_PLLC_M 0x9f
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/* NeoMagic BES registers: (> NM2070) (accessible via mapped I/O: >= NM2097) */
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#define NMGRPHX_BESCTRL1 0xb0
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#define NMGRPHX_HDCOORD21H 0xb1
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#define NMGRPHX_HDCOORD1L 0xb2
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#define NMGRPHX_HDCOORD2L 0xb3
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#define NMGRPHX_VDCOORD21H 0xb4
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#define NMGRPHX_VDCOORD1L 0xb5
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#define NMGRPHX_VDCOORD2L 0xb6
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#define NMGRPHX_BUF1ORGH 0xb7
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#define NMGRPHX_BUF1ORGM 0xb8
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#define NMGRPHX_BUF1ORGL 0xb9
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#define NMGRPHX_BUF1PITCHH 0xba
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#define NMGRPHX_BUF1PITCHL 0xbb
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#define NMGRPHX_0xbc 0xbc //??
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#define NMGRPHX_0xbd 0xbd //??
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#define NMGRPHX_0xbe 0xbe //??
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#define NMGRPHX_0xbf 0xbf //??
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#define NMGRPHX_XSCALEH 0xc0
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#define NMGRPHX_XSCALEL 0xc1
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#define NMGRPHX_YSCALEH 0xc2
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#define NMGRPHX_YSCALEL 0xc3
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#define NMGRPHX_BRIGHTNESS 0xc4
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#define NMGRPHX_COLKEY_R 0xc5
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#define NMGRPHX_COLKEY_G 0xc6
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#define NMGRPHX_COLKEY_B 0xc7
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/* NeoMagic specific PCI cursor registers < NM2200 */
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#define NMCR1_CURCTRL 0x0100
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#define NMCR1_CURX 0x0104
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#define NMCR1_CURY 0x0108
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#define NMCR1_CURBGCOLOR 0x010c
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#define NMCR1_CURFGCOLOR 0x0110
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#define NMCR1_CURADDRESS 0x0114
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/* NeoMagic specific PCI cursor registers >= NM2200 */
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#define NMCR1_22CURCTRL 0x1000
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#define NMCR1_22CURX 0x1004
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#define NMCR1_22CURY 0x1008
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#define NMCR1_22CURBGCOLOR 0x100c
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#define NMCR1_22CURFGCOLOR 0x1010
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#define NMCR1_22CURADDRESS 0x1014
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//old:
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/* NM ACCeleration registers */
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#define NMACC_DWGCTL 0x1C00
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#define NMACC_MACCESS 0x1C04
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#define NMACC_MCTLWTST 0x1C08
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#define NMACC_ZORG 0x1C0C
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#define NMACC_PLNWT 0x1C1C
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#define NMACC_BCOL 0x1C20
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#define NMACC_FCOL 0x1C24
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#define NMACC_XYSTRT 0x1C40
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#define NMACC_XYEND 0x1C44
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#define NMACC_SGN 0x1C58
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#define NMACC_LEN 0x1C5C
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#define NMACC_AR0 0x1C60
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#define NMACC_AR3 0x1C6C
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#define NMACC_AR5 0x1C74
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#define NMACC_CXBNDRY 0x1C80
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#define NMACC_FXBNDRY 0x1C84
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#define NMACC_YDSTLEN 0x1C88
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#define NMACC_PITCH 0x1C8C
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#define NMACC_YDST 0x1C90
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#define NMACC_YDSTORG 0x1C94
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#define NMACC_YTOP 0x1C98
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#define NMACC_YBOT 0x1C9C
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#define NMACC_CXLEFT 0x1CA0
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#define NMACC_CXRIGHT 0x1CA4
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#define NMACC_FXLEFT 0x1CA8
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#define NMACC_FXRIGHT 0x1CAC
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#define NMACC_STATUS 0x1E14
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#define NMACC_ICLEAR 0x1E18 /* required for interrupt stuff */
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#define NMACC_IEN 0x1E1C /* required for interrupt stuff */
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#define NMACC_RST 0x1E40
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#define NMACC_MEMRDBK 0x1E44
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#define NMACC_OPMODE 0x1E54
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#define NMACC_PRIMADDRESS 0x1E58
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#define NMACC_PRIMEND 0x1E5C
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#define NMACC_TEXORG 0x2C24 // >= G100
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#define NMACC_DWGSYNC 0x2C4C // >= G200
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#define NMACC_TEXORG1 0x2CA4 // >= G200
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#define NMACC_TEXORG2 0x2CA8 // >= G200
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#define NMACC_TEXORG3 0x2CAC // >= G200
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#define NMACC_TEXORG4 0x2CB0 // >= G200
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#define NMACC_SRCORG 0x2CB4 // >= G200
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#define NMACC_DSTORG 0x2CB8 // >= G200
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//end old.
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/* Macros for convenient accesses to the NM chips */
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/* primary PCI register area */
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#define NM_REG8(r_) ((vuint8 *)regs)[(r_)]
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#define NM_REG16(r_) ((vuint16 *)regs)[(r_) >> 1]
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#define NM_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]
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/* secondary PCI register area */
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#define NM_2REG8(r_) ((vuint8 *)regs2)[(r_)]
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#define NM_2REG16(r_) ((vuint16 *)regs2)[(r_) >> 1]
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#define NM_2REG32(r_) ((vuint32 *)regs2)[(r_) >> 2]
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/* read and write to PCI config space */
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#define CFGR(A) (nm_pci_access.offset=NMCFG_##A, ioctl(fd,NM_GET_PCI, &nm_pci_access,sizeof(nm_pci_access)), nm_pci_access.value)
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#define CFGW(A,B) (nm_pci_access.offset=NMCFG_##A, nm_pci_access.value = B, ioctl(fd,NM_SET_PCI,&nm_pci_access,sizeof(nm_pci_access)))
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//old:
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/* read and write from the powergraphics registers */
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#define ACCR(A) (NM_REG32(NMACC_##A))
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#define ACCW(A,B) (NM_REG32(NMACC_##A)=B)
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#define ACCGO(A,B) (NM_REG32(NMACC_##A + 0x0100)=B)
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//end old.
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/* read and write from first CRTC (mapped) */
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#define CR1R(A) (NM_REG32(NMCR1_##A))
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#define CR1W(A,B) (NM_REG32(NMCR1_##A) = (B))
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/* read and write from ISA I/O space */
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#define ISAWB(A,B)(nm_isa_access.adress=NMISA8_##A, nm_isa_access.data = (uint8)B, nm_isa_access.size = 1, ioctl(fd,NM_ISA_OUT, &nm_isa_access,sizeof(nm_isa_access)))
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#define ISAWW(A,B)(nm_isa_access.adress=NMISA16_##A, nm_isa_access.data = B, nm_isa_access.size = 2, ioctl(fd,NM_ISA_OUT, &nm_isa_access,sizeof(nm_isa_access)))
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#define ISARB(A) (nm_isa_access.adress=NMISA8_##A, ioctl(fd,NM_ISA_IN, &nm_isa_access,sizeof(nm_isa_access)), (uint8)nm_isa_access.data)
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#define ISARW(A) (nm_isa_access.adress=NMISA16_##A, ioctl(fd,NM_ISA_IN, &nm_isa_access,sizeof(nm_isa_access)), nm_isa_access.data)
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/* read and write from ISA CRTC indexed registers */
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#define ISACRTCW(A,B)(ISAWW(CRTCIND, ((NMCRTCX_##A) | ((B) << 8))))
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#define ISACRTCR(A) (ISAWB(CRTCIND, (NMCRTCX_##A)), ISARB(CRTCDAT))
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/* read and write from ISA GRAPHICS indexed registers */
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#define ISAGRPHW(A,B)(ISAWW(GRPHIND, ((NMGRPHX_##A) | ((B) << 8))))
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#define ISAGRPHR(A) (ISAWB(GRPHIND, (NMGRPHX_##A)), ISARB(GRPHDAT))
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/* read and write from PCI GRAPHICS indexed registers (>= NM2097) */
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#define PCIGRPHW(A,B)(NM_2REG16(NM2PCI16_GRPHIND) = ((NMGRPHX_##A) | ((B) << 8)))
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#define PCIGRPHR(A) (NM_2REG8(NM2PCI8_GRPHIND) = (NMGRPHX_##A), NM_2REG8(NM2PCI8_GRPHDAT))
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/* read and write from ISA SEQUENCER indexed registers */
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#define ISASEQW(A,B)(ISAWW(SEQIND, ((NMSEQX_##A) | ((B) << 8))))
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#define ISASEQR(A) (ISAWB(SEQIND, (NMSEQX_##A)), ISARB(SEQDAT))
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/* read and write from PCI SEQUENCER indexed registers (>= NM2097) */
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#define PCISEQW(A,B)(NM_2REG16(NM2PCI16_SEQIND) = ((NMSEQX_##A) | ((B) << 8)))
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#define PCISEQR(A) (NM_2REG8(NM2PCI8_SEQIND) = (NMSEQX_##A), NM_2REG8(NM2PCI8_SEQDAT))
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/* read and write from ISA ATTRIBUTE indexed registers */
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#define ISAATBW(A,B)((void)ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISAWB(ATTRDATW, (B)))
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#define ISAATBR(A) ((void)ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISARB(ATTRDATR))
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