511 lines
16 KiB
C
511 lines
16 KiB
C
/*
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* Copyright 2002-2009, Axel Dörfler, axeld@pinc-software.de.
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* Copyright 2012, Alex Smith, alex@alex-smith.me.uk.
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* Distributed under the terms of the MIT License.
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*
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* Copyright 2001-2002, Travis Geiselbrecht. All rights reserved.
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* Distributed under the terms of the NewOS License.
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*/
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#ifndef _KERNEL_ARCH_x86_CPU_H
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#define _KERNEL_ARCH_x86_CPU_H
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#ifndef _ASSEMBLER
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#include <module.h>
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#include <arch/x86/descriptors.h>
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#ifdef __x86_64__
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# include <arch/x86/64/iframe.h>
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#else
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# include <arch/x86/32/iframe.h>
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#endif
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#endif // !_ASSEMBLER
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#define CPU_MAX_CACHE_LEVEL 8
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#define CACHE_LINE_SIZE 64
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// MSR registers (possibly Intel specific)
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#define IA32_MSR_TSC 0x10
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#define IA32_MSR_APIC_BASE 0x1b
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#define IA32_MSR_PLATFORM_INFO 0xce
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#define IA32_MSR_MPERF 0xe7
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#define IA32_MSR_APERF 0xe8
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#define IA32_MSR_MTRR_CAPABILITIES 0xfe
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#define IA32_MSR_SYSENTER_CS 0x174
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#define IA32_MSR_SYSENTER_ESP 0x175
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#define IA32_MSR_SYSENTER_EIP 0x176
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#define IA32_MSR_PERF_STATUS 0x198
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#define IA32_MSR_PERF_CTL 0x199
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#define IA32_MSR_TURBO_RATIO_LIMIT 0x1ad
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#define IA32_MSR_ENERGY_PERF_BIAS 0x1b0
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#define IA32_MSR_MTRR_DEFAULT_TYPE 0x2ff
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#define IA32_MSR_MTRR_PHYSICAL_BASE_0 0x200
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#define IA32_MSR_MTRR_PHYSICAL_MASK_0 0x201
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#define IA32_MSR_EFER 0xc0000080
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// MSR APIC BASE bits
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#define IA32_MSR_APIC_BASE_BSP 0x00000100
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#define IA32_MSR_APIC_BASE_X2APIC 0x00000400
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#define IA32_MSR_APIC_BASE_ENABLED 0x00000800
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#define IA32_MSR_APIC_BASE_ADDRESS 0xfffff000
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// MSR EFER bits
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// reference
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#define IA32_MSR_EFER_SYSCALL (1 << 0)
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#define IA32_MSR_EFER_NX (1 << 11)
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// X2APIC MSRs.
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#define IA32_MSR_APIC_ID 0x00000802
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#define IA32_MSR_APIC_VERSION 0x00000803
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#define IA32_MSR_APIC_TASK_PRIORITY 0x00000808
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#define IA32_MSR_APIC_PROCESSOR_PRIORITY 0x0000080a
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#define IA32_MSR_APIC_EOI 0x0000080b
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#define IA32_MSR_APIC_LOGICAL_DEST 0x0000080d
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#define IA32_MSR_APIC_SPURIOUS_INTR_VECTOR 0x0000080f
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#define IA32_MSR_APIC_ERROR_STATUS 0x00000828
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#define IA32_MSR_APIC_INTR_COMMAND 0x00000830
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#define IA32_MSR_APIC_LVT_TIMER 0x00000832
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#define IA32_MSR_APIC_LVT_THERMAL_SENSOR 0x00000833
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#define IA32_MSR_APIC_LVT_PERFMON_COUNTERS 0x00000834
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#define IA32_MSR_APIC_LVT_LINT0 0x00000835
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#define IA32_MSR_APIC_LVT_LINT1 0x00000836
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#define IA32_MSR_APIC_LVT_ERROR 0x00000837
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#define IA32_MSR_APIC_INITIAL_TIMER_COUNT 0x00000838
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#define IA32_MSR_APIC_CURRENT_TIMER_COUNT 0x00000839
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#define IA32_MSR_APIC_TIMER_DIVIDE_CONFIG 0x0000083e
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// x86_64 MSRs.
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#define IA32_MSR_STAR 0xc0000081
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#define IA32_MSR_LSTAR 0xc0000082
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#define IA32_MSR_FMASK 0xc0000084
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#define IA32_MSR_FS_BASE 0xc0000100
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#define IA32_MSR_GS_BASE 0xc0000101
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#define IA32_MSR_KERNEL_GS_BASE 0xc0000102
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// K8 MSR registers
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#define K8_MSR_IPM 0xc0010055
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// x86 features from cpuid eax 1, edx register
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// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-5)
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#define IA32_FEATURE_FPU (1 << 0) // x87 fpu
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#define IA32_FEATURE_VME (1 << 1) // virtual 8086
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#define IA32_FEATURE_DE (1 << 2) // debugging extensions
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#define IA32_FEATURE_PSE (1 << 3) // page size extensions
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#define IA32_FEATURE_TSC (1 << 4) // rdtsc instruction
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#define IA32_FEATURE_MSR (1 << 5) // rdmsr/wrmsr instruction
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#define IA32_FEATURE_PAE (1 << 6) // extended 3 level page table addressing
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#define IA32_FEATURE_MCE (1 << 7) // machine check exception
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#define IA32_FEATURE_CX8 (1 << 8) // cmpxchg8b instruction
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#define IA32_FEATURE_APIC (1 << 9) // local apic on chip
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// (1 << 10) // Reserved
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#define IA32_FEATURE_SEP (1 << 11) // SYSENTER/SYSEXIT
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#define IA32_FEATURE_MTRR (1 << 12) // MTRR
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#define IA32_FEATURE_PGE (1 << 13) // paging global bit
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#define IA32_FEATURE_MCA (1 << 14) // machine check architecture
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#define IA32_FEATURE_CMOV (1 << 15) // cmov instruction
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#define IA32_FEATURE_PAT (1 << 16) // page attribute table
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#define IA32_FEATURE_PSE36 (1 << 17) // page size extensions with 4MB pages
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#define IA32_FEATURE_PSN (1 << 18) // processor serial number
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#define IA32_FEATURE_CLFSH (1 << 19) // cflush instruction
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// (1 << 20) // Reserved
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#define IA32_FEATURE_DS (1 << 21) // debug store
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#define IA32_FEATURE_ACPI (1 << 22) // thermal monitor and clock ctrl
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#define IA32_FEATURE_MMX (1 << 23) // mmx instructions
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#define IA32_FEATURE_FXSR (1 << 24) // FXSAVE/FXRSTOR instruction
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#define IA32_FEATURE_SSE (1 << 25) // SSE
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#define IA32_FEATURE_SSE2 (1 << 26) // SSE2
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#define IA32_FEATURE_SS (1 << 27) // self snoop
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#define IA32_FEATURE_HTT (1 << 28) // hyperthreading
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#define IA32_FEATURE_TM (1 << 29) // thermal monitor
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#define IA32_FEATURE_IA64 (1 << 30) // IA64 processor emulating x86
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#define IA32_FEATURE_PBE (1 << 31) // pending break enable
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// x86 features from cpuid eax 1, ecx register
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// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-4)
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#define IA32_FEATURE_EXT_SSE3 (1 << 0) // SSE3
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#define IA32_FEATURE_EXT_PCLMULQDQ (1 << 1) // PCLMULQDQ Instruction
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#define IA32_FEATURE_EXT_DTES64 (1 << 2) // 64-Bit Debug Store
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#define IA32_FEATURE_EXT_MONITOR (1 << 3) // MONITOR/MWAIT
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#define IA32_FEATURE_EXT_DSCPL (1 << 4) // CPL qualified debug store
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#define IA32_FEATURE_EXT_VMX (1 << 5) // Virtual Machine Extensions
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#define IA32_FEATURE_EXT_SMX (1 << 6) // Safer Mode Extensions
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#define IA32_FEATURE_EXT_EST (1 << 7) // Enhanced SpeedStep
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#define IA32_FEATURE_EXT_TM2 (1 << 8) // Thermal Monitor 2
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#define IA32_FEATURE_EXT_SSSE3 (1 << 9) // Supplemental SSE-3
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#define IA32_FEATURE_EXT_CNXTID (1 << 10) // L1 Context ID
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// (1 << 11) // Reserved
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#define IA32_FEATURE_EXT_FMA (1 << 12) // Fused Multiply Add
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#define IA32_FEATURE_EXT_CX16 (1 << 13) // CMPXCHG16B
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#define IA32_FEATURE_EXT_XTPR (1 << 14) // xTPR Update Control
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#define IA32_FEATURE_EXT_PDCM (1 << 15) // Perfmon and Debug Capability
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// (1 << 16) // Reserved
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#define IA32_FEATURE_EXT_PCID (1 << 17) // Process Context Identifiers
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#define IA32_FEATURE_EXT_DCA (1 << 18) // Direct Cache Access
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#define IA32_FEATURE_EXT_SSE4_1 (1 << 19) // SSE4.1
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#define IA32_FEATURE_EXT_SSE4_2 (1 << 20) // SSE4.2
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#define IA32_FEATURE_EXT_X2APIC (1 << 21) // Extended xAPIC Support
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#define IA32_FEATURE_EXT_MOVBE (1 << 22) // MOVBE Instruction
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#define IA32_FEATURE_EXT_POPCNT (1 << 23) // POPCNT Instruction
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#define IA32_FEATURE_EXT_TSCDEADLINE (1 << 24) // Time Stamp Counter Deadline
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#define IA32_FEATURE_EXT_AES (1 << 25) // AES Instruction Extensions
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#define IA32_FEATURE_EXT_XSAVE (1 << 26) // XSAVE/XSTOR States
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#define IA32_FEATURE_EXT_OSXSAVE (1 << 27) // OS-Enabled XSAVE
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#define IA32_FEATURE_EXT_AVX (1 << 28) // Advanced Vector Extensions
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#define IA32_FEATURE_EXT_F16C (1 << 29) // 16-bit FP conversion
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#define IA32_FEATURE_EXT_RDRND (1 << 30) // RDRAND instruction
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#define IA32_FEATURE_EXT_HYPERVISOR (1 << 31) // Running on a hypervisor
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// x86 features from cpuid eax 0x80000001, ecx register (AMD)
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#define IA32_FEATURE_AMD_EXT_CMPLEGACY (1 << 1) // Core MP legacy mode
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#define IA32_FEATURE_AMD_EXT_TOPOLOGY (1 << 22) // Topology extensions
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// x86 features from cpuid eax 0x80000001, edx register (AMD)
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// only care about the ones that are unique to this register
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#define IA32_FEATURE_AMD_EXT_SYSCALL (1 << 11) // SYSCALL/SYSRET
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#define IA32_FEATURE_AMD_EXT_NX (1 << 20) // no execute bit
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#define IA32_FEATURE_AMD_EXT_MMXEXT (1 << 22) // mmx extensions
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#define IA32_FEATURE_AMD_EXT_FFXSR (1 << 25) // fast FXSAVE/FXRSTOR
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#define IA32_FEATURE_AMD_EXT_RDTSCP (1 << 27) // rdtscp instruction
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#define IA32_FEATURE_AMD_EXT_LONG (1 << 29) // long mode
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#define IA32_FEATURE_AMD_EXT_3DNOWEXT (1 << 30) // 3DNow! extensions
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#define IA32_FEATURE_AMD_EXT_3DNOW (1 << 31) // 3DNow!
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// some of the features from cpuid eax 0x80000001, edx register (AMD) are also
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// available on Intel processors
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#define IA32_FEATURES_INTEL_EXT (IA32_FEATURE_AMD_EXT_SYSCALL \
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| IA32_FEATURE_AMD_EXT_NX \
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| IA32_FEATURE_AMD_EXT_RDTSCP \
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| IA32_FEATURE_AMD_EXT_LONG)
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// x86 defined features from cpuid eax 5, ecx register
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#define IA32_FEATURE_POWER_MWAIT (1 << 0)
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#define IA32_FEATURE_INTERRUPT_MWAIT (1 << 1)
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// x86 defined features from cpuid eax 6, eax register
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// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11)
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#define IA32_FEATURE_DTS (1 << 0) //Digital Thermal Sensor
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#define IA32_FEATURE_ITB (1 << 1) //Intel Turbo Boost Technology
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#define IA32_FEATURE_ARAT (1 << 2) //Always running APIC Timer
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#define IA32_FEATURE_PLN (1 << 4) //Power Limit Notification
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#define IA32_FEATURE_ECMD (1 << 5) //Extended Clock Modulation Duty
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#define IA32_FEATURE_PTM (1 << 6) //Package Thermal Management
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// x86 defined features from cpuid eax 6, ecx register
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// reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11)
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#define IA32_FEATURE_APERFMPERF (1 << 0) //IA32_APERF, IA32_MPERF
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#define IA32_FEATURE_EPB (1 << 3) //IA32_ENERGY_PERF_BIAS
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// x86 defined features from cpuid eax 0x80000007, edx register
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#define IA32_FEATURE_INVARIANT_TSC (1 << 8)
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// cr4 flags
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#define IA32_CR4_PAE (1UL << 5)
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#define IA32_CR4_GLOBAL_PAGES (1UL << 7)
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// Memory type ranges
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#define IA32_MTR_UNCACHED 0
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#define IA32_MTR_WRITE_COMBINING 1
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#define IA32_MTR_WRITE_THROUGH 4
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#define IA32_MTR_WRITE_PROTECTED 5
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#define IA32_MTR_WRITE_BACK 6
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// EFLAGS register
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#define X86_EFLAGS_CARRY 0x00000001
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#define X86_EFLAGS_RESERVED1 0x00000002
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#define X86_EFLAGS_PARITY 0x00000004
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#define X86_EFLAGS_AUXILIARY_CARRY 0x00000010
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#define X86_EFLAGS_ZERO 0x00000040
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#define X86_EFLAGS_SIGN 0x00000080
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#define X86_EFLAGS_TRAP 0x00000100
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#define X86_EFLAGS_INTERRUPT 0x00000200
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#define X86_EFLAGS_DIRECTION 0x00000400
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#define X86_EFLAGS_OVERFLOW 0x00000800
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#define X86_EFLAGS_IO_PRIVILEG_LEVEL 0x00003000
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#define X86_EFLAGS_IO_PRIVILEG_LEVEL_SHIFT 12
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#define X86_EFLAGS_NESTED_TASK 0x00004000
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#define X86_EFLAGS_RESUME 0x00010000
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#define X86_EFLAGS_V86_MODE 0x00020000
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#define X86_EFLAGS_ALIGNMENT_CHECK 0x00040000
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#define X86_EFLAGS_VIRTUAL_INTERRUPT 0x00080000
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#define X86_EFLAGS_VIRTUAL_INTERRUPT_PENDING 0x00100000
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#define X86_EFLAGS_ID 0x00200000
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#define X86_EFLAGS_USER_FLAGS (X86_EFLAGS_CARRY | X86_EFLAGS_PARITY \
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| X86_EFLAGS_AUXILIARY_CARRY | X86_EFLAGS_ZERO | X86_EFLAGS_SIGN \
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| X86_EFLAGS_DIRECTION | X86_EFLAGS_OVERFLOW)
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// iframe types
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#define IFRAME_TYPE_SYSCALL 0x1
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#define IFRAME_TYPE_OTHER 0x2
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#define IFRAME_TYPE_MASK 0xf
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#ifndef _ASSEMBLER
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struct X86PagingStructures;
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typedef struct x86_mtrr_info {
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uint64 base;
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uint64 size;
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uint8 type;
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} x86_mtrr_info;
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typedef struct x86_optimized_functions {
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void (*memcpy)(void* dest, const void* source, size_t count);
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void* memcpy_end;
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void (*memset)(void* dest, int value, size_t count);
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void* memset_end;
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} x86_optimized_functions;
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typedef struct x86_cpu_module_info {
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module_info info;
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uint32 (*count_mtrrs)(void);
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void (*init_mtrrs)(void);
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void (*set_mtrr)(uint32 index, uint64 base, uint64 length,
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uint8 type);
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status_t (*get_mtrr)(uint32 index, uint64* _base, uint64* _length,
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uint8* _type);
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void (*set_mtrrs)(uint8 defaultType, const x86_mtrr_info* infos,
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uint32 count);
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void (*get_optimized_functions)(x86_optimized_functions* functions);
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} x86_cpu_module_info;
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// features
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enum x86_feature_type {
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FEATURE_COMMON = 0, // cpuid eax=1, ecx register
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FEATURE_EXT, // cpuid eax=1, edx register
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FEATURE_EXT_AMD_ECX, // cpuid eax=0x80000001, ecx register (AMD)
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FEATURE_EXT_AMD, // cpuid eax=0x80000001, edx register (AMD)
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FEATURE_5_ECX, // cpuid eax=5, ecx register
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FEATURE_6_EAX, // cpuid eax=6, eax registers
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FEATURE_6_ECX, // cpuid eax=6, ecx registers
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FEATURE_EXT_7_EDX, // cpuid eax=0x80000007, edx register
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FEATURE_NUM
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};
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enum x86_vendors {
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VENDOR_INTEL = 0,
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VENDOR_AMD,
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VENDOR_CYRIX,
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VENDOR_UMC,
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VENDOR_NEXGEN,
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VENDOR_CENTAUR,
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VENDOR_RISE,
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VENDOR_TRANSMETA,
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VENDOR_NSC,
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VENDOR_NUM,
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VENDOR_UNKNOWN,
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};
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typedef struct arch_cpu_info {
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// saved cpu info
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enum x86_vendors vendor;
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uint32 feature[FEATURE_NUM];
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char model_name[49];
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const char* vendor_name;
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int type;
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int family;
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int extended_family;
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int stepping;
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int model;
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int extended_model;
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struct X86PagingStructures* active_paging_structures;
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size_t dr6; // temporary storage for debug registers (cf.
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size_t dr7; // x86_exit_user_debug_at_kernel_entry())
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// local TSS for this cpu
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struct tss tss;
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#ifndef __x86_64__
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struct tss double_fault_tss;
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#endif
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} arch_cpu_info;
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#define nop() __asm__ ("nop"::)
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#define x86_read_cr0() ({ \
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size_t _v; \
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__asm__("mov %%cr0,%0" : "=r" (_v)); \
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_v; \
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})
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#define x86_write_cr0(value) \
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__asm__("mov %0,%%cr0" : : "r" (value))
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#define x86_read_cr2() ({ \
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size_t _v; \
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__asm__("mov %%cr2,%0" : "=r" (_v)); \
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_v; \
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})
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#define x86_read_cr3() ({ \
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size_t _v; \
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__asm__("mov %%cr3,%0" : "=r" (_v)); \
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_v; \
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})
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#define x86_write_cr3(value) \
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__asm__("mov %0,%%cr3" : : "r" (value))
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#define x86_read_cr4() ({ \
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size_t _v; \
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__asm__("mov %%cr4,%0" : "=r" (_v)); \
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_v; \
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})
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#define x86_write_cr4(value) \
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__asm__("mov %0,%%cr4" : : "r" (value))
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#define x86_read_dr3() ({ \
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size_t _v; \
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__asm__("mov %%dr3,%0" : "=r" (_v)); \
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_v; \
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})
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#define x86_write_dr3(value) \
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__asm__("mov %0,%%dr3" : : "r" (value))
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#define invalidate_TLB(va) \
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__asm__("invlpg (%0)" : : "r" (va))
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#define wbinvd() \
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__asm__("wbinvd")
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#define out8(value,port) \
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__asm__ ("outb %%al,%%dx" : : "a" (value), "d" (port))
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#define out16(value,port) \
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__asm__ ("outw %%ax,%%dx" : : "a" (value), "d" (port))
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#define out32(value,port) \
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__asm__ ("outl %%eax,%%dx" : : "a" (value), "d" (port))
|
|
|
|
#define in8(port) ({ \
|
|
uint8 _v; \
|
|
__asm__ volatile ("inb %%dx,%%al" : "=a" (_v) : "d" (port)); \
|
|
_v; \
|
|
})
|
|
|
|
#define in16(port) ({ \
|
|
uint16 _v; \
|
|
__asm__ volatile ("inw %%dx,%%ax":"=a" (_v) : "d" (port)); \
|
|
_v; \
|
|
})
|
|
|
|
#define in32(port) ({ \
|
|
uint32 _v; \
|
|
__asm__ volatile ("inl %%dx,%%eax":"=a" (_v) : "d" (port)); \
|
|
_v; \
|
|
})
|
|
|
|
#define out8_p(value,port) \
|
|
__asm__ ("outb %%al,%%dx\n" \
|
|
"\tjmp 1f\n" \
|
|
"1:\tjmp 1f\n" \
|
|
"1:" : : "a" (value), "d" (port))
|
|
|
|
#define in8_p(port) ({ \
|
|
uint8 _v; \
|
|
__asm__ volatile ("inb %%dx,%%al\n" \
|
|
"\tjmp 1f\n" \
|
|
"1:\tjmp 1f\n" \
|
|
"1:" : "=a" (_v) : "d" (port)); \
|
|
_v; \
|
|
})
|
|
|
|
|
|
extern void (*gCpuIdleFunc)(void);
|
|
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
struct arch_thread;
|
|
|
|
#ifdef __x86_64__
|
|
void __x86_setup_system_time(uint64 conversionFactor,
|
|
uint64 conversionFactorNsecs);
|
|
#else
|
|
void __x86_setup_system_time(uint32 conversionFactor,
|
|
uint32 conversionFactorNsecs, bool conversionFactorNsecsShift);
|
|
#endif
|
|
|
|
void x86_context_switch(struct arch_thread* oldState,
|
|
struct arch_thread* newState);
|
|
void x86_userspace_thread_exit(void);
|
|
void x86_end_userspace_thread_exit(void);
|
|
void x86_swap_pgdir(addr_t newPageDir);
|
|
void x86_fxsave(void* fpuState);
|
|
void x86_fxrstor(const void* fpuState);
|
|
void x86_noop_swap(void* oldFpuState, const void* newFpuState);
|
|
void x86_fxsave_swap(void* oldFpuState, const void* newFpuState);
|
|
addr_t x86_get_stack_frame();
|
|
uint64 x86_read_msr(uint32 registerNumber);
|
|
void x86_write_msr(uint32 registerNumber, uint64 value);
|
|
uint32 x86_count_mtrrs(void);
|
|
void x86_set_mtrr(uint32 index, uint64 base, uint64 length, uint8 type);
|
|
status_t x86_get_mtrr(uint32 index, uint64* _base, uint64* _length,
|
|
uint8* _type);
|
|
void x86_set_mtrrs(uint8 defaultType, const x86_mtrr_info* infos,
|
|
uint32 count);
|
|
void x86_init_fpu();
|
|
bool x86_check_feature(uint32 feature, enum x86_feature_type type);
|
|
void* x86_get_double_fault_stack(int32 cpu, size_t* _size);
|
|
int32 x86_double_fault_get_cpu(void);
|
|
|
|
void x86_invalid_exception(iframe* frame);
|
|
void x86_fatal_exception(iframe* frame);
|
|
void x86_unexpected_exception(iframe* frame);
|
|
void x86_hardware_interrupt(iframe* frame);
|
|
void x86_page_fault_exception(iframe* iframe);
|
|
|
|
#ifndef __x86_64__
|
|
|
|
void x86_fnsave(void* fpuState);
|
|
void x86_frstor(const void* fpuState);
|
|
void x86_fnsave_swap(void* oldFpuState, const void* newFpuState);
|
|
|
|
#endif
|
|
|
|
|
|
static inline void
|
|
arch_cpu_idle(void)
|
|
{
|
|
gCpuIdleFunc();
|
|
}
|
|
|
|
|
|
static inline void
|
|
arch_cpu_pause(void)
|
|
{
|
|
asm volatile("pause" : : : "memory");
|
|
}
|
|
|
|
|
|
#ifdef __cplusplus
|
|
} // extern "C" {
|
|
#endif
|
|
|
|
#endif // !_ASSEMBLER
|
|
|
|
#endif /* _KERNEL_ARCH_x86_CPU_H */
|