221 lines
7.9 KiB
C
221 lines
7.9 KiB
C
/*
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* Copyright 2005, Axel Dörfler, axeld@pinc-software.de. All rights reserved.
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* Copyright 2002-04, Thomas Kurschel. All rights reserved.
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*
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* Distributed under the terms of the MIT License.
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*/
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#ifndef _IDE_PCI_H
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#define _IDE_PCI_H
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/*
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IDE adapter library
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Module to simplify writing an IDE adapter driver.
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The interface is not very abstract, i.e. the actual driver is
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free to access any controller or channel data of this library.
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*/
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#include <bus/PCI.h>
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#include <bus/IDE.h>
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#include <device_manager.h>
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// one Physical Region Descriptor (PRD)
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// (one region must not cross 64K boundary;
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// the PRD table must not cross a 64K boundary)
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typedef struct prd_entry {
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uint32 address; // physical address of block (must be even)
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uint16 count; // size of block, 0 stands for 65536 (must be even)
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uint8 res6;
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LBITFIELD8_2(
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res7_0 : 7,
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EOT : 1 // 1 for last entry
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);
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} prd_entry;
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// command register
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typedef struct ide_bm_command {
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LBITFIELD8_4(
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start_stop : 1, // start BM by changing from 0 to 1;
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// stop BM by changing from 1 to 0
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res0_1 : 2,
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from_device : 1, // true - read from device, false - write to device
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res0_4 : 4
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);
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} ide_bm_command;
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// status register
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typedef struct ide_bm_status {
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LBITFIELD8_7(
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active : 1, // 1, if BM is active
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error : 1, // 1, if error occured; write 1 to reset
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interrupt : 1, // 1, if INTRQ was raised, write 1 to reset
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res0_3 : 2,
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device0_dma : 1, // 1, if BIOS/driver has setup DMA for device 0
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device1_dma : 1, // 1, if BIOS/driver has setup DMA for device 1
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simplex : 1 // 1, if only one channel can use DMA at a time
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);
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} ide_bm_status;
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// offset of bus master registers
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enum {
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ide_bm_command_reg = 0, // see ide_bm_command
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ide_bm_status_reg = 2, // see ide_bm_status
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ide_bm_prdt_address = 4 // offset of PRDT register; content must be dword-aligned
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};
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// bit mask in class_api of PCI configuration
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// (for adapters that can run in compatability mode)
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enum {
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ide_api_primary_native = 1, // primary channel is in native mode
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ide_api_primary_fixed = 2, // primary channel can be switched to native mode
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ide_api_secondary_native = 4, // secondary channel is in native mode
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ide_api_secondary_fixed = 8 // secondary channel can be switched to native mode
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};
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// (maximum) size of S/G table
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// there are so many restrictions that we want to keep it inside one page
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// to be sure that we fulfill them all
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#define IDE_ADAPTER_MAX_SG_COUNT (B_PAGE_SIZE / sizeof( prd_entry ))
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// channel node items
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// io address of command block (uint16)
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#define IDE_ADAPTER_COMMAND_BLOCK_BASE "ide_adapter/command_block_base"
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// io address of control block (uint16)
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#define IDE_ADAPTER_CONTROL_BLOCK_BASE "ide_adapter/control_block_base"
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// interrupt number (uint8)
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// can also be defined in controller node if both channels use same IRQ!
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#define IDE_ADAPTER_INTNUM "ide_adapter/irq"
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// non-zero if primary channel, else secondary channel (uint8)
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#define IDE_ADAPTER_IS_PRIMARY "ide_adapter/is_primary"
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// controller node items
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// io address of bus master registers (uint16)
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#define IDE_ADAPTER_BUS_MASTER_BASE "ide_adapter/bus_master_base"
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// info about one channel
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typedef struct ide_adapter_channel_info {
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pci_device_module_info *pci;
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pci_device device;
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uint16 command_block_base; // io address command block
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uint16 control_block_base; // io address control block
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uint16 bus_master_base;
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int intnum; // interrupt number
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uint32 lost; // != 0 if device got removed, i.e. if it must not
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// be accessed anymore
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ide_channel ide_channel;
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device_node_handle node;
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int32 (*inthand)( void *arg );
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area_id prd_area;
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prd_entry *prdt;
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uint32 prdt_phys;
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uint32 dmaing;
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} ide_adapter_channel_info;
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// info about controller
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typedef struct ide_adapter_controller_info {
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pci_device_module_info *pci;
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pci_device device;
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uint16 bus_master_base;
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uint32 lost; // != 0 if device got removed, i.e. if it must not
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// be accessed anymore
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device_node_handle node;
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} ide_adapter_controller_info;
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// interface of IDE adapter library
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typedef struct {
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module_info info;
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// function calls that can be forwarded from actual driver
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status_t (*write_command_block_regs)(ide_adapter_channel_info *channel,
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ide_task_file *tf, ide_reg_mask mask);
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status_t (*read_command_block_regs)(ide_adapter_channel_info *channel,
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ide_task_file *tf, ide_reg_mask mask);
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uint8 (*get_altstatus) (ide_adapter_channel_info *channel);
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status_t (*write_device_control) (ide_adapter_channel_info *channel, uint8 val);
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status_t (*write_pio)(ide_adapter_channel_info *channel, uint16 *data, int count, bool force_16bit);
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status_t (*read_pio)(ide_adapter_channel_info *channel, uint16 *data, int count, bool force_16bit);
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status_t (*prepare_dma)(ide_adapter_channel_info *channel, const physical_entry *sg_list,
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size_t sg_list_count, bool to_device);
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status_t (*start_dma)(ide_adapter_channel_info *channel);
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status_t (*finish_dma)(ide_adapter_channel_info *channel);
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// default functions that should be replaced by a more specific version
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// (copy them from source code of this library and modify them at will)
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int32 (*inthand)(void *arg);
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// functions that must be called by init/uninit etc. of channel driver
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status_t (*init_channel)(device_node_handle node, ide_channel ide_channel,
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ide_adapter_channel_info **cookie, size_t total_data_size,
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int32 (*inthand)(void *arg));
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status_t (*uninit_channel)(ide_adapter_channel_info *channel);
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void (*channel_removed)(device_node_handle node, ide_adapter_channel_info *channel);
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// publish channel node
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status_t (*publish_channel)(device_node_handle controller_node,
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const char *channel_module_name, uint16 command_block_base,
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uint16 control_block_base, uint8 intnum, bool can_dma,
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bool is_primary, const char *name,
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io_resource_handle *resources, device_node_handle *node);
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// verify channel configuration and publish node on success
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status_t (*detect_channel)(pci_device_module_info *pci, pci_device pci_device,
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device_node_handle controller_node, const char *channel_module_name,
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bool controller_can_dma, uint16 command_block_base,
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uint16 control_block_base, uint16 bus_master_base,
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uint8 intnum, bool is_primary, const char *name,
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device_node_handle *node, bool supports_compatibility_mode);
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// functions that must be called by init/uninit etc. of controller driver
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status_t (*init_controller)(device_node_handle node, void *user_cookie,
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ide_adapter_controller_info **cookie, size_t total_data_size);
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status_t (*uninit_controller)(ide_adapter_controller_info *controller);
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void (*controller_removed)(device_node_handle node, ide_adapter_controller_info *controller);
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// publish controller node
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status_t (*publish_controller)(device_node_handle parent, uint16 bus_master_base,
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io_resource_handle *resources, const char *controller_driver,
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const char *controller_driver_type, const char *controller_name,
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bool can_dma, bool can_cq, uint32 dma_alignment, uint32 dma_boundary,
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uint32 max_sg_block_size, device_node_handle *node);
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// verify controller configuration and publish node on success
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status_t (*detect_controller)(pci_device_module_info *pci, pci_device pci_device,
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device_node_handle parent, uint16 bus_master_base,
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const char *controller_driver, const char *controller_driver_type,
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const char *controller_name, bool can_dma, bool can_cq,
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uint32 dma_alignment, uint32 dma_boundary, uint32 max_sg_block_size,
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device_node_handle *node);
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// standard master probe for controller that registers controller and channel nodes
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status_t (*probe_controller)(device_node_handle parent, const char *controller_driver,
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const char *controller_driver_type, const char *controller_name,
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const char *channel_module_name, bool can_dma, bool can_cq,
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uint32 dma_alignment, uint32 dma_boundary, uint32 max_sg_block_size,
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bool supports_compatibility_mode);
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} ide_adapter_interface;
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#define IDE_ADAPTER_MODULE_NAME "generic/ide_adapter/v1"
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#endif /* _IDE_PCI_H */
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