162 lines
5.5 KiB
C
162 lines
5.5 KiB
C
/*
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* Copyright 2002/03, Thomas Kurschel. All rights reserved.
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* Distributed under the terms of the MIT License.
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*/
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/*
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PCI bus manager
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*/
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#ifndef _PCI2_H
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#define _PCI2_H
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#include <device_manager.h>
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#include <PCI.h>
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// currently, this structure is disabled to avoid collision with R5 header
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#if 0
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typedef struct pci_info {
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ushort vendor_id; /* vendor id */
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ushort device_id; /* device id */
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uchar bus; /* bus number */
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uchar device; /* device number on bus */
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uchar function; /* function number in device */
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uchar revision; /* revision id */
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uchar class_api; /* specific register interface type */
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uchar class_sub; /* specific device function */
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uchar class_base; /* device type (display vs network, etc) */
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uchar line_size; /* cache line size in 32 bit words */
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uchar latency; /* latency timer */
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uchar header_type; /* header type */
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uchar bist; /* built-in self-test */
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uchar reserved; /* filler, for alignment */
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union {
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struct {
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ulong cardbus_cis; /* CardBus CIS pointer */
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ushort subsystem_id; /* subsystem (add-in card) id */
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ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */
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ulong rom_base; /* rom base address, viewed from host */
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ulong rom_base_pci; /* rom base addr, viewed from pci */
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ulong rom_size; /* rom size */
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ulong base_registers[6]; /* base registers, viewed from host */
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ulong base_registers_pci[6]; /* base registers, viewed from pci */
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ulong base_register_sizes[6]; /* size of what base regs point to */
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uchar base_register_flags[6]; /* flags from base address fields */
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uchar interrupt_line; /* interrupt line */
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uchar interrupt_pin; /* interrupt pin */
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uchar min_grant; /* burst period @ 33 Mhz */
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uchar max_latency; /* how often PCI access needed */
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} h0;
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struct {
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ulong base_registers[2]; /* base registers, viewed from host */
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ulong base_registers_pci[2]; /* base registers, viewed from pci */
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ulong base_register_sizes[2]; /* size of what base regs point to */
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uchar base_register_flags[2]; /* flags from base address fields */
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uchar primary_bus;
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uchar secondary_bus;
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uchar subordinate_bus;
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uchar secondary_latency;
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uchar io_base;
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uchar io_limit;
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ushort secondary_status;
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ushort memory_base;
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ushort memory_limit;
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ushort prefetchable_memory_base;
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ushort prefetchable_memory_limit;
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ulong prefetchable_memory_base_upper32;
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ulong prefetchable_memory_limit_upper32;
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ushort io_base_upper16;
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ushort io_limit_upper16;
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ulong rom_base; /* rom base address, viewed from host */
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ulong rom_base_pci; /* rom base addr, viewed from pci */
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uchar interrupt_line; /* interrupt line */
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uchar interrupt_pin; /* interrupt pin */
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ushort bridge_control;
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} h1;
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} u;
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} pci_info;
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#endif
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typedef struct pci_device_info *pci_device;
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// Interface to one PCI device.
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// Actually, this is a _function_ of a device only, but
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// pci_function_module_info would be a bit non-intuitive
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typedef struct pci_device_module_info {
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driver_module_info info;
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uint8 (*read_io_8)(pci_device device, int mapped_io_addr);
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void (*write_io_8)(pci_device device, int mapped_io_addr, uint8 value);
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uint16 (*read_io_16)(pci_device device, int mapped_io_addr);
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void (*write_io_16)(pci_device device, int mapped_io_addr, uint16 value);
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uint32 (*read_io_32)(pci_device device, int mapped_io_addr);
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void (*write_io_32)(pci_device device, int mapped_io_addr, uint32 value);
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uint32 (*read_pci_config)(pci_device device,
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uchar offset, /* offset in configuration space */
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uchar size); /* # bytes to read (1, 2 or 4) */
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void (*write_pci_config)(pci_device device,
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uchar offset, /* offset in configuration space */
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uchar size, /* # bytes to write (1, 2 or 4) */
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uint32 value); /* value to write */
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void *(*ram_address)(pci_device device, const void *physical_address_in_system_memory);
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/* status_t (*allocate_iomem)( void *base, size_t len, const char *name );
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status_t (*release_iomem)( void *base, size_t len );
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status_t (*allocate_ioports)( uint16 ioport_base, size_t len, const char *name );
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status_t (*release_ioports)( uint16 ioport_base, size_t len );*/
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status_t (*get_pci_info)(pci_device device, struct pci_info *info);
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} pci_device_module_info;
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// directory of PCI drivers
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#define PCI_DRIVERS_DIR "pci"
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// attributes of PCI device nodes
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// bus idx (uint8)
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#define PCI_DEVICE_BUS_ITEM "pci/bus"
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// device idx (uint8)
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#define PCI_DEVICE_DEVICE_ITEM "pci/device"
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// function idx (uint8)
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#define PCI_DEVICE_FUNCTION_ITEM "pci/function"
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// vendor id (uint16)
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#define PCI_DEVICE_VENDOR_ID_ITEM "pci/vendor_id"
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// device id (uint16)
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#define PCI_DEVICE_DEVICE_ID_ITEM "pci/device_id"
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// subsystem id (uint16)
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#define PCI_DEVICE_SUBSYSTEM_ID_ITEM "pci/subsystem_id"
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// subvendor id (uint16)
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#define PCI_DEVICE_SUBVENDOR_ID_ITEM "pci/subvendor_id"
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// device base class (uint16)
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#define PCI_DEVICE_BASE_CLASS_ID_ITEM "pci/class/base_id"
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// device subclass (uint16)
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#define PCI_DEVICE_SUB_CLASS_ID_ITEM "pci/class/sub_id"
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// device api (uint16)
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#define PCI_DEVICE_API_ID_ITEM "pci/class/api_id"
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// dynamic consumer patterns for PCI devices
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#define PCI_DEVICE_DYNAMIC_CONSUMER_0 \
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PCI_DRIVERS_DIR "/" \
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"vendor %" PCI_DEVICE_VENDOR_ID_ITEM "%|" \
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", device %" PCI_DEVICE_DEVICE_ID_ITEM "%|" \
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", subsystem %" PCI_DEVICE_SUBSYSTEM_ID_ITEM "%|" \
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", subvendor %" PCI_DEVICE_SUBVENDOR_ID_ITEM "%"
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#define PCI_DEVICE_DYNAMIC_CONSUMER_1 \
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PCI_DRIVERS_DIR "/" \
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"base_class %" PCI_DEVICE_BASE_CLASS_ID_ITEM "%|" \
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", sub_class %" PCI_DEVICE_SUB_CLASS_ID_ITEM "%|" \
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", api %" PCI_DEVICE_API_ID_ITEM "%"
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#endif
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