600 lines
21 KiB
C++
600 lines
21 KiB
C++
/*******************************************************************************
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/
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/ File: PCI.h
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/
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/ Description: Interface to the PCI bus.
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/ For more information, see "PCI Local Bus Specification, Revision 2.1",
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/ PCI Special Interest Group, 1995.
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/
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/ Copyright 1993-98, Be Incorporated, All Rights Reserved.
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/
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*******************************************************************************/
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#ifndef _PCI_H
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#define _PCI_H
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//#include <BeBuild.h>
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//#include <SupportDefs.h>
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#include <bus_manager.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* -----
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pci device info
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----- */
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typedef struct pci_info {
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ushort vendor_id; /* vendor id */
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ushort device_id; /* device id */
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uchar bus; /* bus number */
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uchar device; /* device number on bus */
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uchar function; /* function number in device */
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uchar revision; /* revision id */
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uchar class_api; /* specific register interface type */
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uchar class_sub; /* specific device function */
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uchar class_base; /* device type (display vs network, etc) */
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uchar line_size; /* cache line size in 32 bit words */
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uchar latency; /* latency timer */
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uchar header_type; /* header type */
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uchar bist; /* built-in self-test */
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uchar reserved; /* filler, for alignment */
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union {
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struct {
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ulong cardbus_cis; /* CardBus CIS pointer */
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ushort subsystem_id; /* subsystem (add-in card) id */
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ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */
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ulong rom_base; /* rom base address, viewed from host */
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ulong rom_base_pci; /* rom base addr, viewed from pci */
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ulong rom_size; /* rom size */
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ulong base_registers[6]; /* base registers, viewed from host */
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ulong base_registers_pci[6]; /* base registers, viewed from pci */
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ulong base_register_sizes[6]; /* size of what base regs point to */
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uchar base_register_flags[6]; /* flags from base address fields */
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uchar interrupt_line; /* interrupt line */
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uchar interrupt_pin; /* interrupt pin */
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uchar min_grant; /* burst period @ 33 Mhz */
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uchar max_latency; /* how often PCI access needed */
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} h0;
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struct {
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ulong base_registers[2]; /* base registers, viewed from host */
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ulong base_registers_pci[2]; /* base registers, viewed from pci */
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ulong base_register_sizes[2]; /* size of what base regs point to */
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uchar base_register_flags[2]; /* flags from base address fields */
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uchar primary_bus;
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uchar secondary_bus;
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uchar subordinate_bus;
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uchar secondary_latency;
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uchar io_base;
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uchar io_limit;
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ushort secondary_status;
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ushort memory_base;
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ushort memory_limit;
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ushort prefetchable_memory_base;
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ushort prefetchable_memory_limit;
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ulong prefetchable_memory_base_upper32;
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ulong prefetchable_memory_limit_upper32;
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ushort io_base_upper16;
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ushort io_limit_upper16;
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ulong rom_base; /* rom base address, viewed from host */
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ulong rom_base_pci; /* rom base addr, viewed from pci */
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uchar interrupt_line; /* interrupt line */
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uchar interrupt_pin; /* interrupt pin */
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ushort bridge_control;
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ushort subsystem_id; /* subsystem (add-in card) id */
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ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */
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} h1;
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struct {
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ushort subsystem_id; /* subsystem (add-in card) id */
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ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */
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} h2;
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} u;
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} pci_info;
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typedef struct pci_module_info pci_module_info;
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struct pci_module_info {
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bus_manager_info binfo;
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uint8 (*read_io_8) (int mapped_io_addr);
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void (*write_io_8) (int mapped_io_addr, uint8 value);
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uint16 (*read_io_16) (int mapped_io_addr);
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void (*write_io_16) (int mapped_io_addr, uint16 value);
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uint32 (*read_io_32) (int mapped_io_addr);
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void (*write_io_32) (int mapped_io_addr, uint32 value);
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long (*get_nth_pci_info) (
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long index, /* index into pci device table */
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pci_info *info /* caller-supplied buffer for info */
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);
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uint32 (*read_pci_config) (
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uchar bus, /* bus number */
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uchar device, /* device # on bus */
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uchar function, /* function # in device */
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uchar offset, /* offset in configuration space */
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uchar size /* # bytes to read (1, 2 or 4) */
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);
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void (*write_pci_config) (
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uchar bus, /* bus number */
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uchar device, /* device # on bus */
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uchar function, /* function # in device */
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uchar offset, /* offset in configuration space */
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uchar size, /* # bytes to write (1, 2 or 4) */
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uint32 value /* value to write */
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);
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void * (*ram_address) (const void *physical_address_in_system_memory);
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};
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#define B_PCI_MODULE_NAME "bus_managers/pci/v1"
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/* ---
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offsets in PCI configuration space to the elements of the predefined
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header common to all header types
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--- */
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#define PCI_vendor_id 0x00 /* (2 byte) vendor id */
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#define PCI_device_id 0x02 /* (2 byte) device id */
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#define PCI_command 0x04 /* (2 byte) command */
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#define PCI_status 0x06 /* (2 byte) status */
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#define PCI_revision 0x08 /* (1 byte) revision id */
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#define PCI_class_api 0x09 /* (1 byte) specific register interface type */
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#define PCI_class_sub 0x0a /* (1 byte) specific device function */
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#define PCI_class_base 0x0b /* (1 byte) device type (display vs network, etc) */
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#define PCI_line_size 0x0c /* (1 byte) cache line size in 32 bit words */
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#define PCI_latency 0x0d /* (1 byte) latency timer */
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#define PCI_header_type 0x0e /* (1 byte) header type */
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#define PCI_bist 0x0f /* (1 byte) built-in self-test */
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/* ---
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offsets in PCI configuration space to the elements of the predefined
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header common to header types 0x00 and 0x01
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--- */
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#define PCI_base_registers 0x10 /* base registers (size varies) */
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#define PCI_interrupt_line 0x3c /* (1 byte) interrupt line */
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#define PCI_interrupt_pin 0x3d /* (1 byte) interrupt pin */
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/* ---
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offsets in PCI configuration space to the elements of header type 0x00
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--- */
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#define PCI_cardbus_cis 0x28 /* (4 bytes) CardBus CIS (Card Information Structure) pointer (see PCMCIA v2.10 Spec) */
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#define PCI_subsystem_vendor_id 0x2c /* (2 bytes) subsystem (add-in card) vendor id */
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#define PCI_subsystem_id 0x2e /* (2 bytes) subsystem (add-in card) id */
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#define PCI_rom_base 0x30 /* (4 bytes) expansion rom base address */
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#define PCI_capabilities_ptr 0x34 /* (1 byte) pointer to the start of the capabilities list */
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#define PCI_min_grant 0x3e /* (1 byte) burst period @ 33 Mhz */
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#define PCI_max_latency 0x3f /* (1 byte) how often PCI access needed */
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/* ---
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offsets in PCI configuration space to the elements of header type 0x01 (PCI-to-PCI bridge)
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--- */
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#define PCI_primary_bus 0x18 /* (1 byte) */
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#define PCI_secondary_bus 0x19 /* (1 byte) */
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#define PCI_subordinate_bus 0x1A /* (1 byte) */
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#define PCI_secondary_latency 0x1B /* (1 byte) latency of secondary bus */
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#define PCI_io_base 0x1C /* (1 byte) io base address register for 2ndry bus*/
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#define PCI_io_limit 0x1D /* (1 byte) */
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#define PCI_secondary_status 0x1E /* (2 bytes) */
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#define PCI_memory_base 0x20 /* (2 bytes) */
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#define PCI_memory_limit 0x22 /* (2 bytes) */
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#define PCI_prefetchable_memory_base 0x24 /* (2 bytes) */
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#define PCI_prefetchable_memory_limit 0x26 /* (2 bytes) */
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#define PCI_prefetchable_memory_base_upper32 0x28
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#define PCI_prefetchable_memory_limit_upper32 0x2C
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#define PCI_io_base_upper16 0x30 /* (2 bytes) */
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#define PCI_io_limit_upper16 0x32 /* (2 bytes) */
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#define PCI_sub_vendor_id_1 0x34 /* (2 bytes) */
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#define PCI_sub_device_id_1 0x36 /* (2 bytes) */
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#define PCI_bridge_rom_base 0x38
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#define PCI_bridge_control 0x3E /* (1 byte) */
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/* PCI type 2 header offsets */
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#define PCI_capabilities_ptr_2 0x14 /* (1 byte) */
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#define PCI_secondary_status_2 0x16 /* (2 bytes) */
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#define PCI_primary_bus_2 0x18 /* (1 byte) */
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#define PCI_secondary_bus_2 0x19 /* (1 byte) */
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#define PCI_subordinate_bus_2 0x1A /* (1 byte) */
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#define PCI_secondary_latency_2 0x1B /* (1 byte) latency of secondary bus */
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#define PCI_memory_base0_2 0x1C /* (4 bytes) */
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#define PCI_memory_limit0_2 0x20 /* (4 bytes) */
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#define PCI_memory_base1_2 0x24 /* (4 bytes) */
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#define PCI_memory_limit1_2 0x28 /* (4 bytes) */
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#define PCI_io_base0_2 0x2c /* (4 bytes) */
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#define PCI_io_limit0_2 0x30 /* (4 bytes) */
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#define PCI_io_base1_2 0x34 /* (4 bytes) */
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#define PCI_io_limit1_2 0x38 /* (4 bytes) */
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#define PCI_bridge_control_2 0x3E /* (1 byte) */
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#define PCI_sub_vendor_id_2 0x40 /* (2 bytes) */
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#define PCI_sub_device_id_2 0x42 /* (2 bytes) */
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#define PCI_card_interface_2 0x44 /* ?? */
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/* ---
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values for the class_base field in the common header
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--- */
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#define PCI_early 0x00 /* built before class codes defined */
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#define PCI_mass_storage 0x01 /* mass storage_controller */
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#define PCI_network 0x02 /* network controller */
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#define PCI_display 0x03 /* display controller */
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#define PCI_multimedia 0x04 /* multimedia device */
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#define PCI_memory 0x05 /* memory controller */
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#define PCI_bridge 0x06 /* bridge controller */
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#define PCI_simple_communications 0x07 /* simple communications controller */
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#define PCI_base_peripheral 0x08 /* base system peripherals */
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#define PCI_input 0x09 /* input devices */
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#define PCI_docking_station 0x0a /* docking stations */
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#define PCI_processor 0x0b /* processors */
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#define PCI_serial_bus 0x0c /* serial_bus_controller */
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#define PCI_undefined 0xFF /* not in any defined class */
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/* ---
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values for the class_sub field for class_base = 0x00 (built before
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class codes were defined)
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--- */
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#define PCI_early_not_vga 0x00 /* all except vga */
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#define PCI_early_vga 0x01 /* vga devices */
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/* ---
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values for the class_sub field for class_base = 0x01 (mass storage)
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--- */
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#define PCI_scsi 0x00 /* SCSI controller */
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#define PCI_ide 0x01 /* IDE controller */
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#define PCI_floppy 0x02 /* floppy disk controller */
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#define PCI_ipi 0x03 /* IPI bus controller */
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#define PCI_raid 0x04 /* RAID controller */
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#define PCI_mass_storage_other 0x80 /* other mass storage controller */
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/* ---
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values for the class_sub field for class_base = 0x02 (network)
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--- */
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#define PCI_ethernet 0x00 /* Ethernet controller */
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#define PCI_token_ring 0x01 /* Token Ring controller */
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#define PCI_fddi 0x02 /* FDDI controller */
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#define PCI_atm 0x03 /* ATM controller */
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#define PCI_isdn 0x04 /* ISDN controller */
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#define PCI_network_other 0x80 /* other network controller */
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/* ---
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values for the class_sub field for class_base = 0x03 (display)
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--- */
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#define PCI_vga 0x00 /* VGA controller */
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#define PCI_xga 0x01 /* XGA controller */
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#define PCI_3d 0x02 /* £d controller */
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#define PCI_display_other 0x80 /* other display controller */
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/* ---
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values for the class_sub field for class_base = 0x04 (multimedia device)
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--- */
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#define PCI_video 0x00 /* video */
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#define PCI_audio 0x01 /* audio */
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#define PCI_telephony 0x02 /* computer telephony device */
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#define PCI_multimedia_other 0x80 /* other multimedia device */
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/* ---
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values for the class_sub field for class_base = 0x05 (memory)
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--- */
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#define PCI_ram 0x00 /* RAM */
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#define PCI_flash 0x01 /* flash */
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#define PCI_memory_other 0x80 /* other memory controller */
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/* ---
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values for the class_sub field for class_base = 0x06 (bridge)
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--- */
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#define PCI_host 0x00 /* host bridge */
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#define PCI_isa 0x01 /* ISA bridge */
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#define PCI_eisa 0x02 /* EISA bridge */
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#define PCI_microchannel 0x03 /* MicroChannel bridge */
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#define PCI_pci 0x04 /* PCI-to-PCI bridge */
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#define PCI_pcmcia 0x05 /* PCMCIA bridge */
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#define PCI_nubus 0x06 /* NuBus bridge */
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#define PCI_cardbus 0x07 /* CardBus bridge */
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#define PCI_raceway 0x08 /* RACEway bridge */
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#define PCI_bridge_other 0x80 /* other bridge device */
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/* ---
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values for the class_sub field for class_base = 0x07 (simple
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communications controllers)
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--- */
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#define PCI_serial 0x00 /* serial port controller */
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#define PCI_parallel 0x01 /* parallel port */
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#define PCI_multiport_serial 0x02 /* multiport serial controller */
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#define PCI_modem 0x03 /* modem */
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#define PCI_simple_communications_other 0x80 /* other communications device */
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/* ---
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values of the class_api field for
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class_base = 0x07 (simple communications), and
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class_sub = 0x00 (serial port controller)
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--- */
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#define PCI_serial_xt 0x00 /* XT-compatible serial controller */
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#define PCI_serial_16450 0x01 /* 16450-compatible serial controller */
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#define PCI_serial_16550 0x02 /* 16550-compatible serial controller */
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/* ---
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values of the class_api field for
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class_base = 0x07 (simple communications), and
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class_sub = 0x01 (parallel port)
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--- */
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#define PCI_parallel_simple 0x00 /* simple (output-only) parallel port */
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#define PCI_parallel_bidirectional 0x01 /* bidirectional parallel port */
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#define PCI_parallel_ecp 0x02 /* ECP 1.x compliant parallel port */
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/* ---
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values for the class_sub field for class_base = 0x08 (generic
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system peripherals)
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--- */
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#define PCI_pic 0x00 /* periperal interrupt controller */
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#define PCI_dma 0x01 /* dma controller */
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#define PCI_timer 0x02 /* timers */
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#define PCI_rtc 0x03 /* real time clock */
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#define PCI_generic_hot_plug 0x04 /* generic PCI hot-plug controller */
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#define PCI_system_peripheral_other 0x80 /* other generic system peripheral */
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/* ---
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values of the class_api field for
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class_base = 0x08 (generic system peripherals)
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class_sub = 0x00 (peripheral interrupt controller)
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--- */
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#define PCI_pic_8259 0x00 /* generic 8259 */
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#define PCI_pic_isa 0x01 /* ISA pic */
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#define PCI_pic_eisa 0x02 /* EISA pic */
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/* ---
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values of the class_api field for
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class_base = 0x08 (generic system peripherals)
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class_sub = 0x01 (dma controller)
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--- */
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#define PCI_dma_8237 0x00 /* generic 8237 */
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#define PCI_dma_isa 0x01 /* ISA dma */
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#define PCI_dma_eisa 0x02 /* EISA dma */
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/* ---
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values of the class_api field for
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class_base = 0x08 (generic system peripherals)
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class_sub = 0x02 (timer)
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--- */
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#define PCI_timer_8254 0x00 /* generic 8254 */
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#define PCI_timer_isa 0x01 /* ISA timer */
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#define PCI_timer_eisa 0x02 /* EISA timers (2 timers) */
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/* ---
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values of the class_api field for
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class_base = 0x08 (generic system peripherals)
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class_sub = 0x03 (real time clock
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--- */
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#define PCI_rtc_generic 0x00 /* generic real time clock */
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#define PCI_rtc_isa 0x01 /* ISA real time clock */
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/* ---
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values for the class_sub field for class_base = 0x09 (input devices)
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--- */
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#define PCI_keyboard 0x00 /* keyboard controller */
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#define PCI_pen 0x01 /* pen */
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#define PCI_mouse 0x02 /* mouse controller */
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#define PCI_scanner 0x03 /* scanner controller */
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#define PCI_gameport 0x04 /* gameport controller */
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#define PCI_input_other 0x80 /* other input controller */
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/* ---
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values for the class_sub field for class_base = 0x0a (docking stations)
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--- */
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#define PCI_docking_generic 0x00 /* generic docking station */
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/* ---
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values for the class_sub field for class_base = 0x0b (processor)
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--- */
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#define PCI_386 0x00 /* 386 */
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#define PCI_486 0x01 /* 486 */
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#define PCI_pentium 0x02 /* Pentium */
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#define PCI_alpha 0x10 /* Alpha */
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#define PCI_PowerPC 0x20 /* PowerPC */
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#define PCI_mips 0x30 /* MIPS */
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#define PCI_coprocessor 0x40 /* co-processor */
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/* ---
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values for the class_sub field for class_base = 0x0c (serial bus
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controller)
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--- */
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#define PCI_firewire 0x00 /* FireWire (IEEE 1394) */
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#define PCI_access 0x01 /* ACCESS bus */
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#define PCI_ssa 0x02 /* SSA */
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#define PCI_usb 0x03 /* Universal Serial Bus */
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#define PCI_fibre_channel 0x04 /* Fibre channel */
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/* ---
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values of the class_api field for
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class_base = 0x0c ( serial bus controller )
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class_sub = 0x03 ( Universal Serial Bus )
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--- */
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#define PCI_usb_uhci 0x00 /* Universal Host Controller Interface */
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#define PCI_usb_ohci 0x10 /* Open Host Controller Interface */
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/* ---
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masks for command register bits
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--- */
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#define PCI_command_io 0x001 /* 1/0 i/o space en/disabled */
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#define PCI_command_memory 0x002 /* 1/0 memory space en/disabled */
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#define PCI_command_master 0x004 /* 1/0 pci master en/disabled */
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#define PCI_command_special 0x008 /* 1/0 pci special cycles en/disabled */
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#define PCI_command_mwi 0x010 /* 1/0 memory write & invalidate en/disabled */
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#define PCI_command_vga_snoop 0x020 /* 1/0 vga pallette snoop en/disabled */
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#define PCI_command_parity 0x040 /* 1/0 parity check en/disabled */
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#define PCI_command_address_step 0x080 /* 1/0 address stepping en/disabled */
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#define PCI_command_serr 0x100 /* 1/0 SERR# en/disabled */
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#define PCI_command_fastback 0x200 /* 1/0 fast back-to-back en/disabled */
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/* ---
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masks for status register bits
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--- */
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#define PCI_status_capabilities 0x0010 /* capabilities list */
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#define PCI_status_66_MHz_capable 0x0020 /* 66 Mhz capable */
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#define PCI_status_udf_supported 0x0040 /* user-definable-features (udf) supported */
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#define PCI_status_fastback 0x0080 /* fast back-to-back capable */
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#define PCI_status_parity_signalled 0x0100 /* parity error signalled */
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#define PCI_status_devsel 0x0600 /* devsel timing (see below) */
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#define PCI_status_target_abort_signalled 0x0800 /* signaled a target abort */
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#define PCI_status_target_abort_received 0x1000 /* received a target abort */
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#define PCI_status_master_abort_received 0x2000 /* received a master abort */
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#define PCI_status_serr_signalled 0x4000 /* signalled SERR# */
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#define PCI_status_parity_error_detected 0x8000 /* parity error detected */
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/* ---
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masks for devsel field in status register
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--- */
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#define PCI_status_devsel_fast 0x0000 /* fast */
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#define PCI_status_devsel_medium 0x0200 /* medium */
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#define PCI_status_devsel_slow 0x0400 /* slow */
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/* ---
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masks for header type register
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--- */
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#define PCI_header_type_mask 0x7F /* header type field */
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#define PCI_multifunction 0x80 /* multifunction device flag */
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/** types of PCI header */
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#define PCI_header_type_generic 0x00
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#define PCI_header_type_PCI_to_PCI_bridge 0x01
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#define PCI_header_type_cardbus 0x02
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/* ---
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masks for built in self test (bist) register bits
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--- */
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#define PCI_bist_code 0x0F /* self-test completion code, 0 = success */
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#define PCI_bist_start 0x40 /* 1 = start self-test */
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#define PCI_bist_capable 0x80 /* 1 = self-test capable */
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/** masks for flags in the various base address registers */
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#define PCI_address_space 0x01 /* 0 = memory space, 1 = i/o space */
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#define PCI_register_start 0x10
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#define PCI_register_end 0x24
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#define PCI_register_ppb_end 0x18
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#define PCI_register_pcb_end 0x14
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/** masks for flags in memory space base address registers */
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#define PCI_address_type_32 0x00 /* locate anywhere in 32 bit space */
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#define PCI_address_type_32_low 0x02 /* locate below 1 Meg */
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#define PCI_address_type_64 0x04 /* locate anywhere in 64 bit space */
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#define PCI_address_type 0x06 /* type (see below) */
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#define PCI_address_prefetchable 0x08 /* 1 if prefetchable (see PCI spec) */
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#define PCI_address_memory_32_mask 0xFFFFFFF0 /* mask to get 32bit memory space base address */
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/* ---
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masks for flags in i/o space base address registers
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--- */
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#define PCI_address_io_mask 0xFFFFFFFC /* mask to get i/o space base address */
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/* ---
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masks for flags in expansion rom base address registers
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--- */
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#define PCI_rom_enable 0x00000001 /* 1 = expansion rom decode enabled */
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#define PCI_rom_address_mask 0xFFFFF800 /* mask to get expansion rom addr */
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/** PCI interrupt pin values */
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#define PCI_pin_mask 0x07
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#define PCI_pin_none 0x00
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#define PCI_pin_a 0x01
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#define PCI_pin_b 0x02
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#define PCI_pin_c 0x03
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#define PCI_pin_d 0x04
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#define PCI_pin_max 0x04
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/** PCI Capability Codes */
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#define PCI_cap_id_reserved 0x00
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#define PCI_cap_id_pm 0x01 /* Power management */
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#define PCI_cap_id_agp 0x02 /* AGP */
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#define PCI_cap_id_vpd 0x03 /* Vital product data */
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#define PCI_cap_id_slotid 0x04 /* Slot ID */
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#define PCI_cap_id_msi 0x05 /* Message signalled interrupt ??? */
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#define PCI_cap_id_chswp 0x06 /* Compact PCI HotSwap */
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#define PCI_cap_id_pcix 0x07
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#define PCI_cap_id_ldt 0x08
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#define PCI_cap_id_vendspec 0x09
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#define PCI_cap_id_debugport 0x0a
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#define PCI_cap_id_cpci_rsrcctl 0x0b
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#define PCI_cap_id_hotplug 0x0c
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/** Power Management Control Status Register settings */
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#define PCI_pm_mask 0x03
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#define PCI_pm_ctrl 0x02
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#define PCI_pm_d1supp 0x0200
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#define PCI_pm_d2supp 0x0400
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#define PCI_pm_status 0x04
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#define PCI_pm_state_d0 0x00
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#define PCI_pm_state_d1 0x01
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#define PCI_pm_state_d2 0x02
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#define PCI_pm_state_d3 0x03
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#ifdef __cplusplus
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}
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#endif
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#endif /* _PCI_H */
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