519 lines
16 KiB
C
519 lines
16 KiB
C
/*
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* Copyright 1998-2001, VMware, Inc.
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* Distributed under the terms of the MIT License.
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*
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*/
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/*
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* svga_reg.h --
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*
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* SVGA hardware definitions
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*/
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#ifndef _SVGA_REG_H_
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#define _SVGA_REG_H_
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/*
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* Memory and port addresses and fundamental constants
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*/
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/*
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* Note-- MAX_WIDTH and MAX_HEIGHT are largely ignored by the code. This
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* isn't such a bad thing for forward compatibility. --Jeremy.
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*/
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#define SVGA_MAX_WIDTH 2360
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#define SVGA_MAX_HEIGHT 1770
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#define SVGA_MAX_BITS_PER_PIXEL 32
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#define SVGA_MAX_DEPTH 24
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#define SVGA_FB_MAX_SIZE \
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((((SVGA_MAX_WIDTH * SVGA_MAX_HEIGHT * \
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SVGA_MAX_BITS_PER_PIXEL / 8) >> PAGE_SHIFT) + 1) << PAGE_SHIFT)
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#define SVGA_MAX_PSEUDOCOLOR_DEPTH 8
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#define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
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#define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS)
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#define SVGA_MAGIC 0x900000UL
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#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
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/* Version 2 let the address of the frame buffer be unsigned on Win32 */
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#define SVGA_VERSION_2 2
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#define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2)
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/* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so
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PALETTE_BASE has moved */
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#define SVGA_VERSION_1 1
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#define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1)
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/* Version 0 is the initial version */
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#define SVGA_VERSION_0 0
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#define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0)
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/* Invalid SVGA_ID_ */
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#define SVGA_ID_INVALID 0xFFFFFFFF
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/* More backwards compatibility, old location of color map: */
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#define SVGA_OLD_PALETTE_BASE 17
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/* Base and Offset gets us headed the right way for PCI Base Addr Registers */
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#define SVGA_LEGACY_BASE_PORT 0x4560
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#define SVGA_INDEX_PORT 0x0
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#define SVGA_VALUE_PORT 0x1
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#define SVGA_BIOS_PORT 0x2
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#define SVGA_NUM_PORTS 0x3
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/* This port is deprecated, but retained because of old drivers. */
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#define SVGA_LEGACY_ACCEL_PORT 0x3
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/* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
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#define SVGA_CURSOR_ON_HIDE 0x0 /* Must be 0 to maintain backward compatibility */
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#define SVGA_CURSOR_ON_SHOW 0x1 /* Must be 1 to maintain backward compatibility */
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#define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 /* Remove the cursor from the framebuffer because we need to see what's under it */
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#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */
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/*
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* Registers
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*/
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enum {
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SVGA_REG_ID = 0,
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SVGA_REG_ENABLE = 1,
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SVGA_REG_WIDTH = 2,
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SVGA_REG_HEIGHT = 3,
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SVGA_REG_MAX_WIDTH = 4,
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SVGA_REG_MAX_HEIGHT = 5,
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SVGA_REG_DEPTH = 6,
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SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
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SVGA_REG_PSEUDOCOLOR = 8,
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SVGA_REG_RED_MASK = 9,
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SVGA_REG_GREEN_MASK = 10,
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SVGA_REG_BLUE_MASK = 11,
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SVGA_REG_BYTES_PER_LINE = 12,
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SVGA_REG_FB_START = 13,
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SVGA_REG_FB_OFFSET = 14,
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SVGA_REG_VRAM_SIZE = 15,
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SVGA_REG_FB_SIZE = 16,
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/* ID 0 implementation only had the above registers, then the palette */
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SVGA_REG_CAPABILITIES = 17,
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SVGA_REG_MEM_START = 18, /* Memory for command FIFO and bitmaps */
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SVGA_REG_MEM_SIZE = 19,
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SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
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SVGA_REG_SYNC = 21, /* Write to force synchronization */
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SVGA_REG_BUSY = 22, /* Read to check if sync is done */
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SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
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SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
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SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
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SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
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SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
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SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
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SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
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SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
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SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
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SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
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SVGA_REG_TOP = 33, /* Must be 1 more than the last register */
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SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
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/* Next 768 (== 256*3) registers exist for colormap */
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SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
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/* Base of scratch registers */
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/* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
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First 4 are reserved for VESA BIOS Extension; any remaining are for
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the use of the current SVGA driver. */
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};
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/*
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* Capabilities
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*/
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#define SVGA_CAP_NONE 0x00000
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#define SVGA_CAP_RECT_FILL 0x00001
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#define SVGA_CAP_RECT_COPY 0x00002
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#define SVGA_CAP_RECT_PAT_FILL 0x00004
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#define SVGA_CAP_LEGACY_OFFSCREEN 0x00008
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#define SVGA_CAP_RASTER_OP 0x00010
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#define SVGA_CAP_CURSOR 0x00020
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#define SVGA_CAP_CURSOR_BYPASS 0x00040
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#define SVGA_CAP_CURSOR_BYPASS_2 0x00080
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#define SVGA_CAP_8BIT_EMULATION 0x00100
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#define SVGA_CAP_ALPHA_CURSOR 0x00200
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#define SVGA_CAP_GLYPH 0x00400
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#define SVGA_CAP_GLYPH_CLIPPING 0x00800
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#define SVGA_CAP_OFFSCREEN_1 0x01000
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#define SVGA_CAP_ALPHA_BLEND 0x02000
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#define SVGA_CAP_3D 0x04000
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#define SVGA_CAP_EXTENDED_FIFO 0x08000
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#define SVGA_CAP_MULTIMON 0x10000
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#define SVGA_CAP_PITCHLOCK 0x20000
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/*
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* Raster op codes (same encoding as X) used by FIFO drivers.
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*/
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#define SVGA_ROP_CLEAR 0x00 /* 0 */
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#define SVGA_ROP_AND 0x01 /* src AND dst */
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#define SVGA_ROP_AND_REVERSE 0x02 /* src AND NOT dst */
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#define SVGA_ROP_COPY 0x03 /* src */
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#define SVGA_ROP_AND_INVERTED 0x04 /* NOT src AND dst */
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#define SVGA_ROP_NOOP 0x05 /* dst */
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#define SVGA_ROP_XOR 0x06 /* src XOR dst */
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#define SVGA_ROP_OR 0x07 /* src OR dst */
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#define SVGA_ROP_NOR 0x08 /* NOT src AND NOT dst */
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#define SVGA_ROP_EQUIV 0x09 /* NOT src XOR dst */
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#define SVGA_ROP_INVERT 0x0a /* NOT dst */
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#define SVGA_ROP_OR_REVERSE 0x0b /* src OR NOT dst */
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#define SVGA_ROP_COPY_INVERTED 0x0c /* NOT src */
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#define SVGA_ROP_OR_INVERTED 0x0d /* NOT src OR dst */
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#define SVGA_ROP_NAND 0x0e /* NOT src OR NOT dst */
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#define SVGA_ROP_SET 0x0f /* 1 */
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#define SVGA_ROP_UNSUPPORTED 0x10
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#define SVGA_NUM_SUPPORTED_ROPS 16
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#define SVGA_ROP_ALL (MASK(SVGA_NUM_SUPPORTED_ROPS))
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#define SVGA_IS_VALID_ROP(rop) (rop < SVGA_NUM_SUPPORTED_ROPS)
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/*
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* Ops
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* For each pixel, the four channels of the image are computed with:
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*
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* C = Ca * Fa + Cb * Fb
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*
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* where C, Ca, Cb are the values of the respective channels and Fa
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* and Fb come from the following table:
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*
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* BlendOp Fa Fb
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* ------------------------------------------
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* Clear 0 0
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* Src 1 0
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* Dst 0 1
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* Over 1 1-Aa
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* OverReverse 1-Ab 1
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* In Ab 0
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* InReverse 0 Aa
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* Out 1-Ab 0
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* OutReverse 0 1-Aa
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* Atop Ab 1-Aa
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* AtopReverse 1-Ab Aa
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* Xor 1-Ab 1-Aa
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* Add 1 1
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* Saturate min(1,(1-Ab)/Aa) 1
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*
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* Flags
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* You can use the following flags to achieve additional affects:
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*
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* Flag Effect
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* ------------------------------------------
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* ConstantSourceAlpha Ca = Ca * Param0
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* ConstantDestAlpha Cb = Cb * Param1
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*
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* Flag effects resolve before the op. For example
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* BlendOp == Add && Flags == ConstantSourceAlpha |
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* ConstantDestAlpha results in:
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*
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* C = (Ca * Param0) + (Cb * Param1)
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*/
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#define SVGA_BLENDOP_CLEAR 0
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#define SVGA_BLENDOP_SRC 1
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#define SVGA_BLENDOP_DST 2
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#define SVGA_BLENDOP_OVER 3
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#define SVGA_BLENDOP_OVER_REVERSE 4
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#define SVGA_BLENDOP_IN 5
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#define SVGA_BLENDOP_IN_REVERSE 6
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#define SVGA_BLENDOP_OUT 7
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#define SVGA_BLENDOP_OUT_REVERSE 8
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#define SVGA_BLENDOP_ATOP 9
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#define SVGA_BLENDOP_ATOP_REVERSE 10
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#define SVGA_BLENDOP_XOR 11
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#define SVGA_BLENDOP_ADD 12
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#define SVGA_BLENDOP_SATURATE 13
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#define SVGA_NUM_BLENDOPS 14
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#define SVGA_IS_VALID_BLENDOP(op) (op >= 0 && op < SVGA_NUM_BLENDOPS)
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#define SVGA_BLENDFLAG_CONSTANT_SOURCE_ALPHA 0x01
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#define SVGA_BLENDFLAG_CONSTANT_DEST_ALPHA 0x02
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#define SVGA_NUM_BLENDFLAGS 2
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#define SVGA_BLENDFLAG_ALL (MASK(SVGA_NUM_BLENDFLAGS))
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#define SVGA_IS_VALID_BLENDFLAG(flag) ((flag & ~SVGA_BLENDFLAG_ALL) == 0)
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/*
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* FIFO offsets (viewed as an array of 32-bit words)
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*/
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enum {
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/*
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* The original defined FIFO offsets
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*/
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SVGA_FIFO_MIN = 0,
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SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
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SVGA_FIFO_NEXT_CMD,
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SVGA_FIFO_STOP,
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/*
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* Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
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*/
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SVGA_FIFO_CAPABILITIES = 4,
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SVGA_FIFO_FLAGS,
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SVGA_FIFO_FENCE,
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SVGA_FIFO_3D_HWVERSION, /* Check SVGA3dHardwareVersion in svga3d_reg.h */
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SVGA_FIFO_PITCHLOCK,
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/*
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* Always keep this last. It's not an offset with semantic value, but
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* rather a convenient way to produce the value of fifo[SVGA_FIFO_NUM_REGS]
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*/
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SVGA_FIFO_NUM_REGS
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};
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/*
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* FIFO Capabilities
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*
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* Fence -- Fence register and command are supported
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* Accel Front -- Front buffer only commands are supported
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* Pitch Lock -- Pitch lock register is supported
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*/
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#define SVGA_FIFO_CAP_NONE 0
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#define SVGA_FIFO_CAP_FENCE (1<<0)
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#define SVGA_FIFO_CAP_ACCELFRONT (1<<1)
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#define SVGA_FIFO_CAP_PITCHLOCK (1<<2)
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/*
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* FIFO Flags
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*
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* Accel Front -- Driver should use front buffer only commands
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*/
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#define SVGA_FIFO_FLAG_NONE 0
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#define SVGA_FIFO_FLAG_ACCELFRONT (1<<0)
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/*
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* Drawing object ID's, in the range 0 to SVGA_MAX_ID
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*/
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#define SVGA_MAX_ID 499
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/*
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* Macros to compute variable length items (sizes in 32-bit words, except
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* for SVGA_GLYPH_SCANLINE_SIZE, which is in bytes).
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*/
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#define SVGA_BITMAP_SIZE(w,h) ((((w)+31) >> 5) * (h))
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#define SVGA_BITMAP_SCANLINE_SIZE(w) (( (w)+31 ) >> 5)
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#define SVGA_PIXMAP_SIZE(w,h,bpp) ((( ((w)*(bpp))+31 ) >> 5) * (h))
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#define SVGA_PIXMAP_SCANLINE_SIZE(w,bpp) (( ((w)*(bpp))+31 ) >> 5)
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#define SVGA_GLYPH_SIZE(w,h) ((((((w) + 7) >> 3) * (h)) + 3) >> 2)
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#define SVGA_GLYPH_SCANLINE_SIZE(w) (((w) + 7) >> 3)
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/*
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* Increment from one scanline to the next of a bitmap or pixmap
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*/
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#define SVGA_BITMAP_INCREMENT(w) ((( (w)+31 ) >> 5) * sizeof (uint32))
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#define SVGA_PIXMAP_INCREMENT(w,bpp) ((( ((w)*(bpp))+31 ) >> 5) * sizeof (uint32))
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/*
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* Transparent color for DRAW_GLYPH_CLIPPED
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*/
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#define SVGA_COLOR_TRANSPARENT (~0)
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/*
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* Commands in the command FIFO
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*/
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#define SVGA_CMD_INVALID_CMD 0
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/* FIFO layout:
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<nothing> (well, undefined) */
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#define SVGA_CMD_UPDATE 1
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/* FIFO layout:
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X, Y, Width, Height */
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#define SVGA_CMD_RECT_FILL 2
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/* FIFO layout:
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Color, X, Y, Width, Height */
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#define SVGA_CMD_RECT_COPY 3
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/* FIFO layout:
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Source X, Source Y, Dest X, Dest Y, Width, Height */
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#define SVGA_CMD_DEFINE_BITMAP 4
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/* FIFO layout:
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Pixmap ID, Width, Height, <scanlines> */
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#define SVGA_CMD_DEFINE_BITMAP_SCANLINE 5
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/* FIFO layout:
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Pixmap ID, Width, Height, Line #, scanline */
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#define SVGA_CMD_DEFINE_PIXMAP 6
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/* FIFO layout:
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Pixmap ID, Width, Height, Depth, <scanlines> */
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#define SVGA_CMD_DEFINE_PIXMAP_SCANLINE 7
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/* FIFO layout:
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Pixmap ID, Width, Height, Depth, Line #, scanline */
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#define SVGA_CMD_RECT_BITMAP_FILL 8
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/* FIFO layout:
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Bitmap ID, X, Y, Width, Height, Foreground, Background */
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#define SVGA_CMD_RECT_PIXMAP_FILL 9
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/* FIFO layout:
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Pixmap ID, X, Y, Width, Height */
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#define SVGA_CMD_RECT_BITMAP_COPY 10
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/* FIFO layout:
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Bitmap ID, Source X, Source Y, Dest X, Dest Y,
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Width, Height, Foreground, Background */
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#define SVGA_CMD_RECT_PIXMAP_COPY 11
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/* FIFO layout:
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Pixmap ID, Source X, Source Y, Dest X, Dest Y, Width, Height */
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#define SVGA_CMD_FREE_OBJECT 12
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/* FIFO layout:
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Object (pixmap, bitmap, ...) ID */
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#define SVGA_CMD_RECT_ROP_FILL 13
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/* FIFO layout:
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Color, X, Y, Width, Height, ROP */
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#define SVGA_CMD_RECT_ROP_COPY 14
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/* FIFO layout:
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Source X, Source Y, Dest X, Dest Y, Width, Height, ROP */
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#define SVGA_CMD_RECT_ROP_BITMAP_FILL 15
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/* FIFO layout:
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ID, X, Y, Width, Height, Foreground, Background, ROP */
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#define SVGA_CMD_RECT_ROP_PIXMAP_FILL 16
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/* FIFO layout:
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ID, X, Y, Width, Height, ROP */
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#define SVGA_CMD_RECT_ROP_BITMAP_COPY 17
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/* FIFO layout:
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ID, Source X, Source Y,
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Dest X, Dest Y, Width, Height, Foreground, Background, ROP */
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#define SVGA_CMD_RECT_ROP_PIXMAP_COPY 18
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/* FIFO layout:
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ID, Source X, Source Y, Dest X, Dest Y, Width, Height, ROP */
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#define SVGA_CMD_DEFINE_CURSOR 19
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/* FIFO layout:
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ID, Hotspot X, Hotspot Y, Width, Height,
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Depth for AND mask, Depth for XOR mask,
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<scanlines for AND mask>, <scanlines for XOR mask> */
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#define SVGA_CMD_DISPLAY_CURSOR 20
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/* FIFO layout:
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ID, On/Off (1 or 0) */
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#define SVGA_CMD_MOVE_CURSOR 21
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/* FIFO layout:
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X, Y */
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#define SVGA_CMD_DEFINE_ALPHA_CURSOR 22
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/* FIFO layout:
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ID, Hotspot X, Hotspot Y, Width, Height,
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<scanlines> */
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#define SVGA_CMD_DRAW_GLYPH 23
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/* FIFO layout:
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X, Y, W, H, FGCOLOR, <stencil buffer> */
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#define SVGA_CMD_DRAW_GLYPH_CLIPPED 24
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/* FIFO layout:
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X, Y, W, H, FGCOLOR, BGCOLOR, <cliprect>, <stencil buffer>
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Transparent color expands are done by setting BGCOLOR to ~0 */
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#define SVGA_CMD_UPDATE_VERBOSE 25
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/* FIFO layout:
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X, Y, Width, Height, Reason */
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#define SVGA_CMD_SURFACE_FILL 26
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/* FIFO layout:
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color, dstSurfaceOffset, x, y, w, h, rop */
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#define SVGA_CMD_SURFACE_COPY 27
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/* FIFO layout:
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srcSurfaceOffset, dstSurfaceOffset, srcX, srcY,
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destX, destY, w, h, rop */
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#define SVGA_CMD_SURFACE_ALPHA_BLEND 28
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/* FIFO layout:
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srcSurfaceOffset, dstSurfaceOffset, srcX, srcY,
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destX, destY, w, h, op (SVGA_BLENDOP*), flags (SVGA_BLENDFLAGS*),
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param1, param2 */
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#define SVGA_CMD_FRONT_ROP_FILL 29
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/* FIFO layout:
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Color, X, Y, Width, Height, ROP */
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#define SVGA_CMD_FENCE 30
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/* FIFO layout:
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Fence value */
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#define SVGA_CMD_MAX 31
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#define SVGA_CMD_MAX_ARGS 64
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/*
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* Location and size of SVGA frame buffer and the FIFO.
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*/
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#define SVGA_VRAM_MAX_SIZE (16 * 1024 * 1024)
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#define SVGA_VRAM_SIZE_WS (16 * 1024 * 1024) // 16 MB
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#define SVGA_MEM_SIZE_WS (2 * 1024 * 1024) // 2 MB
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#define SVGA_VRAM_SIZE_SERVER (4 * 1024 * 1024) // 4 MB
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#define SVGA_MEM_SIZE_SERVER (256 * 1024) // 256 KB
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#if /* defined(VMX86_WGS) || */ defined(VMX86_SERVER)
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#define SVGA_VRAM_SIZE SVGA_VRAM_SIZE_SERVER
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#define SVGA_MEM_SIZE SVGA_MEM_SIZE_SERVER
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#else
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#define SVGA_VRAM_SIZE SVGA_VRAM_SIZE_WS
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#define SVGA_MEM_SIZE SVGA_MEM_SIZE_WS
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#endif
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/*
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* SVGA_FB_START is the default starting address of the SVGA frame
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* buffer in the guest's physical address space.
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* SVGA_FB_START_BIGMEM is the starting address of the SVGA frame
|
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* buffer for VMs that have a large amount of physical memory.
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|
*
|
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* The address of SVGA_FB_START is set to 2GB - (SVGA_FB_MAX_SIZE + SVGA_MEM_SIZE),
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* thus the SVGA frame buffer sits at [SVGA_FB_START .. 2GB-1] in the
|
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* physical address space. Our older SVGA drivers for NT treat the
|
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* address of the frame buffer as a signed integer. For backwards
|
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* compatibility, we keep the default location of the frame buffer
|
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* at under 2GB in the address space. This restricts VMs to have "only"
|
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* up to ~2031MB (i.e., up to SVGA_FB_START) of physical memory.
|
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*
|
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* For VMs that want more memory than the ~2031MB, we place the SVGA
|
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* frame buffer at SVGA_FB_START_BIGMEM. This allows VMs to have up
|
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* to 3584MB, at least as far as the SVGA frame buffer is concerned
|
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* (note that there may be other issues that limit the VM memory
|
|
* size). PCI devices use high memory addresses, so we have to put
|
|
* SVGA_FB_START_BIGMEM low enough so that it doesn't overlap with any
|
|
* of these devices. Placing SVGA_FB_START_BIGMEM at 0xE0000000
|
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* should leave plenty of room for the PCI devices.
|
|
*
|
|
* NOTE: All of that is only true for the 0710 chipset. As of the 0405
|
|
* chipset, the framebuffer start is determined solely based on the value
|
|
* the guest BIOS or OS programs into the PCI base address registers.
|
|
*/
|
|
#define SVGA_FB_LEGACY_START 0x7EFC0000
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|
#define SVGA_FB_LEGACY_START_BIGMEM 0xE0000000
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|
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#endif
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