10a83ac31f
the fact that I couldn't find ptesync in an otherwise more complete documentation I downloaded yesterday made me suspicious. * arch_cpu_global_TLB_invalidate() uses tlbia now. The instruction is optional, but so is tlbie (how I understood it is that both exist, when the architecture implementation has a TLB). And the former loop looked just scary. * Implemented arch_cpu_user_TLB_invalidate(). It does just the same as arch_cpu_global_TLB_invalidate(). * Some changes with respect to synchronization required on page table and segment register updates. * Some more minor renaming. Pulled a new function remove_page_table_entry() out of unmap_tmap(). * In arch_vm_translation_map_init_post_area() we do now remap the page table into the kernel address space, if it was without before. The page table might actually be a good application for BAT, though. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15773 a95241bf-73f2-0310-859d-f6bbb57e9c96 |
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.. | ||
app | ||
debug | ||
disk_scanner | ||
drivers | ||
graphics | ||
input | ||
interface | ||
kernel | ||
libroot | ||
media | ||
midi | ||
net | ||
opengl/GL/internal | ||
runtime_loader | ||
screen_saver | ||
servers/app | ||
shared | ||
storage | ||
syslog_daemon | ||
textencoding | ||
tracker | ||
translation |