8841d8bcd1
* Headers updated * PLL errata workarounds * Radeon asic type overhaul (consolidated) * Device IDs Updated. * support for X-series devices with legacy bios type * minor tidy ups / compiler warnings (casts) git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@20271 a95241bf-73f2-0310-859d-f6bbb57e9c96
195 lines
9.4 KiB
C
195 lines
9.4 KiB
C
/*
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Copyright (c) 2002, Thomas Kurschel
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Part of Radeon driver
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2D registers
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*/
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#ifndef _2D_REGS_H
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#define _2D_REGS_H
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#define RADEON_DP_BRUSH_BKGD_CLR 0x1478
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#define RADEON_DP_BRUSH_FRGD_CLR 0x147c
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#define RADEON_DP_CNTL 0x16c0
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# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)
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# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)
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#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
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# define RADEON_DST_Y_MAJOR (1 << 2)
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# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
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# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
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#define RADEON_DP_DATATYPE 0x16c4
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# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)
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#define RADEON_DP_GUI_MASTER_CNTL 0x146c
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# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
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# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
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# define RADEON_GMC_SRC_CLIPPING (1 << 2)
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# define RADEON_GMC_DST_CLIPPING (1 << 3)
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# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)
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# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)
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# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)
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# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)
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# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)
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# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)
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# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)
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# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)
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# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)
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# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)
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# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)
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# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
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# define RADEON_GMC_BRUSH_NONE (15 << 4)
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# define RADEON_GMC_DST_8BPP_CI (2 << 8)
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# define RADEON_GMC_DST_15BPP (3 << 8)
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# define RADEON_GMC_DST_16BPP (4 << 8)
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# define RADEON_GMC_DST_24BPP (5 << 8)
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# define RADEON_GMC_DST_32BPP (6 << 8)
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# define RADEON_GMC_DST_8BPP_RGB (7 << 8)
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# define RADEON_GMC_DST_Y8 (8 << 8)
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# define RADEON_GMC_DST_RGB8 (9 << 8)
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# define RADEON_GMC_DST_VYUY (11 << 8)
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# define RADEON_GMC_DST_YVYU (12 << 8)
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# define RADEON_GMC_DST_AYUV444 (14 << 8)
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# define RADEON_GMC_DST_ARGB4444 (15 << 8)
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# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)
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# define RADEON_GMC_DST_DATATYPE_SHIFT 8
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# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)
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# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
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# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
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# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
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# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)
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# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)
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# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)
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# define RADEON_GMC_CONVERSION_TEMP (1 << 15)
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# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)
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# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)
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# define RADEON_GMC_ROP3_MASK (0xff << 16)
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# define RADEON_DP_SRC_SOURCE_MASK (7 << 24)
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# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
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# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
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# define RADEON_GMC_3D_FCN_EN (1 << 27)
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# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
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# define RADEON_GMC_AUX_CLIP_DIS (1 << 29)
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# define RADEON_GMC_WR_MSK_DIS (1 << 30)
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# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)
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# define RADEON_ROP3_ZERO 0x00000000
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# define RADEON_ROP3_DSa 0x00880000
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# define RADEON_ROP3_SDna 0x00440000
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# define RADEON_ROP3_S 0x00cc0000
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# define RADEON_ROP3_DSna 0x00220000
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# define RADEON_ROP3_D 0x00aa0000
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# define RADEON_ROP3_DSx 0x00660000
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# define RADEON_ROP3_DSo 0x00ee0000
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# define RADEON_ROP3_DSon 0x00110000
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# define RADEON_ROP3_DSxn 0x00990000
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# define RADEON_ROP3_Dn 0x00550000
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# define RADEON_ROP3_SDno 0x00dd0000
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# define RADEON_ROP3_Sn 0x00330000
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# define RADEON_ROP3_DSno 0x00bb0000
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# define RADEON_ROP3_DSan 0x00770000
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# define RADEON_ROP3_ONE 0x00ff0000
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# define RADEON_ROP3_DPa 0x00a00000
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# define RADEON_ROP3_PDna 0x00500000
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# define RADEON_ROP3_P 0x00f00000
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# define RADEON_ROP3_DPna 0x000a0000
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# define RADEON_ROP3_D 0x00aa0000
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# define RADEON_ROP3_DPx 0x005a0000
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# define RADEON_ROP3_DPo 0x00fa0000
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# define RADEON_ROP3_DPon 0x00050000
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# define RADEON_ROP3_PDxn 0x00a50000
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# define RADEON_ROP3_PDno 0x00f50000
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# define RADEON_ROP3_Pn 0x000f0000
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# define RADEON_ROP3_DPno 0x00af0000
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# define RADEON_ROP3_DPan 0x005f0000
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#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84
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#define RADEON_DP_MIX 0x16c8
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#define RADEON_DP_SRC_BKGD_CLR 0x15dc
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#define RADEON_DP_SRC_FRGD_CLR 0x15d8
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#define RADEON_DP_WRITE_MASK 0x16cc
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#define RADEON_BRUSH_SCALE 0x1470
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#define RADEON_BRUSH_Y_X 0x1474
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#define RADEON_BRUSH_DATA0 0x1480
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#define RADEON_BRUSH_DATA1 0x1484
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#define RADEON_BRUSH_DATA2 0x1488
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#define RADEON_BRUSH_DATA3 0x148c
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#define RADEON_BRUSH_DATA4 0x1490
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#define RADEON_BRUSH_DATA5 0x1494
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#define RADEON_BRUSH_DATA6 0x1498
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#define RADEON_BRUSH_DATA7 0x149c
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#define RADEON_BRUSH_DATA8 0x14a0
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#define RADEON_BRUSH_DATA9 0x14a4
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#define RADEON_BRUSH_DATA10 0x14a8
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#define RADEON_BRUSH_DATA11 0x14ac
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#define RADEON_BRUSH_DATA12 0x14b0
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#define RADEON_BRUSH_DATA13 0x14b4
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#define RADEON_BRUSH_DATA14 0x14b8
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#define RADEON_BRUSH_DATA15 0x14bc
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#define RADEON_BRUSH_DATA16 0x14c0
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#define RADEON_BRUSH_DATA17 0x14c4
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#define RADEON_BRUSH_DATA18 0x14c8
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#define RADEON_BRUSH_DATA19 0x14cc
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#define RADEON_BRUSH_DATA20 0x14d0
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#define RADEON_BRUSH_DATA21 0x14d4
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#define RADEON_BRUSH_DATA22 0x14d8
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#define RADEON_BRUSH_DATA23 0x14dc
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#define RADEON_BRUSH_DATA24 0x14e0
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#define RADEON_BRUSH_DATA25 0x14e4
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#define RADEON_BRUSH_DATA26 0x14e8
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#define RADEON_BRUSH_DATA27 0x14ec
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#define RADEON_BRUSH_DATA28 0x14f0
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#define RADEON_BRUSH_DATA29 0x14f4
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#define RADEON_BRUSH_DATA30 0x14f8
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#define RADEON_BRUSH_DATA31 0x14fc
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#define RADEON_BRUSH_DATA32 0x1500
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#define RADEON_BRUSH_DATA33 0x1504
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#define RADEON_BRUSH_DATA34 0x1508
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#define RADEON_BRUSH_DATA35 0x150c
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#define RADEON_BRUSH_DATA36 0x1510
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#define RADEON_BRUSH_DATA37 0x1514
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#define RADEON_BRUSH_DATA38 0x1518
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#define RADEON_BRUSH_DATA39 0x151c
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#define RADEON_BRUSH_DATA40 0x1520
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#define RADEON_BRUSH_DATA41 0x1524
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#define RADEON_BRUSH_DATA42 0x1528
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#define RADEON_BRUSH_DATA43 0x152c
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#define RADEON_BRUSH_DATA44 0x1530
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#define RADEON_BRUSH_DATA45 0x1534
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#define RADEON_BRUSH_DATA46 0x1538
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#define RADEON_BRUSH_DATA47 0x153c
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#define RADEON_BRUSH_DATA48 0x1540
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#define RADEON_BRUSH_DATA49 0x1544
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#define RADEON_BRUSH_DATA50 0x1548
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#define RADEON_BRUSH_DATA51 0x154c
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#define RADEON_BRUSH_DATA52 0x1550
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#define RADEON_BRUSH_DATA53 0x1554
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#define RADEON_BRUSH_DATA54 0x1558
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#define RADEON_BRUSH_DATA55 0x155c
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#define RADEON_BRUSH_DATA56 0x1560
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#define RADEON_BRUSH_DATA57 0x1564
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#define RADEON_BRUSH_DATA58 0x1568
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#define RADEON_BRUSH_DATA59 0x156c
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#define RADEON_BRUSH_DATA60 0x1570
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#define RADEON_BRUSH_DATA61 0x1574
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#define RADEON_BRUSH_DATA62 0x1578
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#define RADEON_BRUSH_DATA63 0x157c
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#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
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# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
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# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
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#define RADEON_DST_LINE_START 0x1600
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#define RADEON_DST_LINE_END 0x1604
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#define RADEON_DST_LINE_PATCOUNT 0x1608
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# define RADEON_BRES_CNTL_SHIFT 8
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#define RADEON_DEFAULT_OFFSET 0x16e0
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#define RADEON_DEFAULT_PITCH 0x16e4
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#define RADEON_SRC_PITCH_OFFSET 0x1428
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#define RADEON_DST_PITCH_OFFSET 0x142c
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#endif
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