2613175e19
* add boot item support to radeon hd driver * add edid storage to shared info * add pull of active monitor VESA EDID to radeon hd driver (until AtomBios complete) * EDID pulled in driver now passed to create_display_modes * move registers to external stock xorg radeon hd register headers (lic. allows it) git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41411 a95241bf-73f2-0310-859d-f6bbb57e9c96
505 lines
29 KiB
C
505 lines
29 KiB
C
/*
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* RadeonHD R6xx, R7xx Register documentation
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*
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* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
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* Copyright (C) 2008-2009 Matthias Hopf
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _R600_REG_R6xx_H_
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#define _R600_REG_R6xx_H_
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/*
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* Registers for R6xx chips that are not documented yet
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*/
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enum {
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MM_INDEX = 0x0000,
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MM_DATA = 0x0004,
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SRBM_STATUS = 0x0e50,
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RLC_RQ_PENDING_bit = 1 << 3,
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RCU_RQ_PENDING_bit = 1 << 4,
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GRBM_RQ_PENDING_bit = 1 << 5,
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HI_RQ_PENDING_bit = 1 << 6,
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IO_EXTERN_SIGNAL_bit = 1 << 7,
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VMC_BUSY_bit = 1 << 8,
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MCB_BUSY_bit = 1 << 9,
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MCDZ_BUSY_bit = 1 << 10,
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MCDY_BUSY_bit = 1 << 11,
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MCDX_BUSY_bit = 1 << 12,
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MCDW_BUSY_bit = 1 << 13,
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SEM_BUSY_bit = 1 << 14,
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SRBM_STATUS__RLC_BUSY_bit = 1 << 15,
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PDMA_BUSY_bit = 1 << 16,
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IH_BUSY_bit = 1 << 17,
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CSC_BUSY_bit = 1 << 20,
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CMC7_BUSY_bit = 1 << 21,
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CMC6_BUSY_bit = 1 << 22,
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CMC5_BUSY_bit = 1 << 23,
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CMC4_BUSY_bit = 1 << 24,
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CMC3_BUSY_bit = 1 << 25,
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CMC2_BUSY_bit = 1 << 26,
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CMC1_BUSY_bit = 1 << 27,
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CMC0_BUSY_bit = 1 << 28,
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BIF_BUSY_bit = 1 << 29,
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IDCT_BUSY_bit = 1 << 30,
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SRBM_READ_ERROR = 0x0e98,
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READ_ADDRESS_mask = 0xffff << 2,
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READ_ADDRESS_shift = 2,
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READ_REQUESTER_HI_bit = 1 << 24,
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READ_REQUESTER_GRBM_bit = 1 << 25,
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READ_REQUESTER_RCU_bit = 1 << 26,
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READ_REQUESTER_RLC_bit = 1 << 27,
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READ_ERROR_bit = 1 << 31,
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SRBM_INT_STATUS = 0x0ea4,
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RDERR_INT_STAT_bit = 1 << 0,
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GFX_CNTX_SWITCH_INT_STAT_bit = 1 << 1,
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SRBM_INT_ACK = 0x0ea8,
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RDERR_INT_ACK_bit = 1 << 0,
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GFX_CNTX_SWITCH_INT_ACK_bit = 1 << 1,
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/* R6XX_MC_VM_FB_LOCATION = 0x2180, */
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VENDOR_DEVICE_ID = 0x4000,
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HDP_MEM_COHERENCY_FLUSH_CNTL = 0x5480,
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/* D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110, */
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/* D1GRPH_PITCH = 0x6120, */
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/* D1GRPH_Y_END = 0x6138, */
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GRBM_STATUS = 0x8010,
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R600_CMDFIFO_AVAIL_mask = 0x1f << 0,
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R700_CMDFIFO_AVAIL_mask = 0xf << 0,
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CMDFIFO_AVAIL_shift = 0,
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SRBM_RQ_PENDING_bit = 1 << 5,
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CP_RQ_PENDING_bit = 1 << 6,
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CF_RQ_PENDING_bit = 1 << 7,
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PF_RQ_PENDING_bit = 1 << 8,
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GRBM_EE_BUSY_bit = 1 << 10,
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GRBM_STATUS__VC_BUSY_bit = 1 << 11,
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DB03_CLEAN_bit = 1 << 12,
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CB03_CLEAN_bit = 1 << 13,
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VGT_BUSY_NO_DMA_bit = 1 << 16,
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GRBM_STATUS__VGT_BUSY_bit = 1 << 17,
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TA03_BUSY_bit = 1 << 18,
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GRBM_STATUS__TC_BUSY_bit = 1 << 19,
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SX_BUSY_bit = 1 << 20,
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SH_BUSY_bit = 1 << 21,
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SPI03_BUSY_bit = 1 << 22,
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SMX_BUSY_bit = 1 << 23,
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SC_BUSY_bit = 1 << 24,
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PA_BUSY_bit = 1 << 25,
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DB03_BUSY_bit = 1 << 26,
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CR_BUSY_bit = 1 << 27,
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CP_COHERENCY_BUSY_bit = 1 << 28,
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GRBM_STATUS__CP_BUSY_bit = 1 << 29,
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CB03_BUSY_bit = 1 << 30,
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GUI_ACTIVE_bit = 1 << 31,
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GRBM_STATUS2 = 0x8014,
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CR_CLEAN_bit = 1 << 0,
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SMX_CLEAN_bit = 1 << 1,
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SPI0_BUSY_bit = 1 << 8,
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SPI1_BUSY_bit = 1 << 9,
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SPI2_BUSY_bit = 1 << 10,
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SPI3_BUSY_bit = 1 << 11,
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TA0_BUSY_bit = 1 << 12,
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TA1_BUSY_bit = 1 << 13,
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TA2_BUSY_bit = 1 << 14,
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TA3_BUSY_bit = 1 << 15,
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DB0_BUSY_bit = 1 << 16,
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DB1_BUSY_bit = 1 << 17,
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DB2_BUSY_bit = 1 << 18,
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DB3_BUSY_bit = 1 << 19,
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CB0_BUSY_bit = 1 << 20,
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CB1_BUSY_bit = 1 << 21,
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CB2_BUSY_bit = 1 << 22,
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CB3_BUSY_bit = 1 << 23,
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GRBM_SOFT_RESET = 0x8020,
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SOFT_RESET_CP_bit = 1 << 0,
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SOFT_RESET_CB_bit = 1 << 1,
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SOFT_RESET_CR_bit = 1 << 2,
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SOFT_RESET_DB_bit = 1 << 3,
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SOFT_RESET_PA_bit = 1 << 5,
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SOFT_RESET_SC_bit = 1 << 6,
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SOFT_RESET_SMX_bit = 1 << 7,
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SOFT_RESET_SPI_bit = 1 << 8,
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SOFT_RESET_SH_bit = 1 << 9,
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SOFT_RESET_SX_bit = 1 << 10,
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SOFT_RESET_TC_bit = 1 << 11,
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SOFT_RESET_TA_bit = 1 << 12,
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SOFT_RESET_VC_bit = 1 << 13,
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SOFT_RESET_VGT_bit = 1 << 14,
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SOFT_RESET_GRBM_GCA_bit = 1 << 15,
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WAIT_UNTIL = 0x8040,
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WAIT_CP_DMA_IDLE_bit = 1 << 8,
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WAIT_CMDFIFO_bit = 1 << 10,
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WAIT_2D_IDLE_bit = 1 << 14,
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WAIT_3D_IDLE_bit = 1 << 15,
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WAIT_2D_IDLECLEAN_bit = 1 << 16,
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WAIT_3D_IDLECLEAN_bit = 1 << 17,
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WAIT_EXTERN_SIG_bit = 1 << 19,
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CMDFIFO_ENTRIES_mask = 0x1f << 20,
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CMDFIFO_ENTRIES_shift = 20,
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GRBM_READ_ERROR = 0x8058,
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/* READ_ADDRESS_mask = 0xffff << 2, */
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/* READ_ADDRESS_shift = 2, */
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READ_REQUESTER_SRBM_bit = 1 << 28,
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READ_REQUESTER_CP_bit = 1 << 29,
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READ_REQUESTER_WU_POLL_bit = 1 << 30,
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/* READ_ERROR_bit = 1 << 31, */
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SCRATCH_REG0 = 0x8500,
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SCRATCH_REG1 = 0x8504,
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SCRATCH_REG2 = 0x8508,
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SCRATCH_REG3 = 0x850c,
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SCRATCH_REG4 = 0x8510,
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SCRATCH_REG5 = 0x8514,
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SCRATCH_REG6 = 0x8518,
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SCRATCH_REG7 = 0x851c,
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SCRATCH_UMSK = 0x8540,
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SCRATCH_ADDR = 0x8544,
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CP_COHER_CNTL = 0x85f0,
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DEST_BASE_0_ENA_bit = 1 << 0,
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DEST_BASE_1_ENA_bit = 1 << 1,
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SO0_DEST_BASE_ENA_bit = 1 << 2,
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SO1_DEST_BASE_ENA_bit = 1 << 3,
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SO2_DEST_BASE_ENA_bit = 1 << 4,
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SO3_DEST_BASE_ENA_bit = 1 << 5,
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CB0_DEST_BASE_ENA_bit = 1 << 6,
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CB1_DEST_BASE_ENA_bit = 1 << 7,
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CB2_DEST_BASE_ENA_bit = 1 << 8,
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CB3_DEST_BASE_ENA_bit = 1 << 9,
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CB4_DEST_BASE_ENA_bit = 1 << 10,
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CB5_DEST_BASE_ENA_bit = 1 << 11,
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CB6_DEST_BASE_ENA_bit = 1 << 12,
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CB7_DEST_BASE_ENA_bit = 1 << 13,
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DB_DEST_BASE_ENA_bit = 1 << 14,
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CR_DEST_BASE_ENA_bit = 1 << 15,
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TC_ACTION_ENA_bit = 1 << 23,
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VC_ACTION_ENA_bit = 1 << 24,
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CB_ACTION_ENA_bit = 1 << 25,
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DB_ACTION_ENA_bit = 1 << 26,
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SH_ACTION_ENA_bit = 1 << 27,
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SMX_ACTION_ENA_bit = 1 << 28,
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CR0_ACTION_ENA_bit = 1 << 29,
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CR1_ACTION_ENA_bit = 1 << 30,
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CR2_ACTION_ENA_bit = 1 << 31,
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CP_COHER_SIZE = 0x85f4,
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CP_COHER_BASE = 0x85f8,
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CP_COHER_STATUS = 0x85fc,
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MATCHING_GFX_CNTX_mask = 0xff << 0,
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MATCHING_GFX_CNTX_shift = 0,
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MATCHING_CR_CNTX_mask = 0xffff << 8,
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MATCHING_CR_CNTX_shift = 8,
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STATUS_bit = 1 << 31,
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CP_STALLED_STAT1 = 0x8674,
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RBIU_TO_DMA_NOT_RDY_TO_RCV_bit = 1 << 0,
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RBIU_TO_IBS_NOT_RDY_TO_RCV_bit = 1 << 1,
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RBIU_TO_SEM_NOT_RDY_TO_RCV_bit = 1 << 2,
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RBIU_TO_2DREGS_NOT_RDY_TO_RCV_bit = 1 << 3,
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RBIU_TO_MEMWR_NOT_RDY_TO_RCV_bit = 1 << 4,
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RBIU_TO_MEMRD_NOT_RDY_TO_RCV_bit = 1 << 5,
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RBIU_TO_EOPD_NOT_RDY_TO_RCV_bit = 1 << 6,
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RBIU_TO_RECT_NOT_RDY_TO_RCV_bit = 1 << 7,
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RBIU_TO_STRMO_NOT_RDY_TO_RCV_bit = 1 << 8,
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RBIU_TO_PSTAT_NOT_RDY_TO_RCV_bit = 1 << 9,
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MIU_WAITING_ON_RDREQ_FREE_bit = 1 << 16,
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MIU_WAITING_ON_WRREQ_FREE_bit = 1 << 17,
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MIU_NEEDS_AVAIL_WRREQ_PHASE_bit = 1 << 18,
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RCIU_WAITING_ON_GRBM_FREE_bit = 1 << 24,
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RCIU_WAITING_ON_VGT_FREE_bit = 1 << 25,
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RCIU_STALLED_ON_ME_READ_bit = 1 << 26,
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RCIU_STALLED_ON_DMA_READ_bit = 1 << 27,
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RCIU_HALTED_BY_REG_VIOLATION_bit = 1 << 28,
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CP_STALLED_STAT2 = 0x8678,
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PFP_TO_CSF_NOT_RDY_TO_RCV_bit = 1 << 0,
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PFP_TO_MEQ_NOT_RDY_TO_RCV_bit = 1 << 1,
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PFP_TO_VGT_NOT_RDY_TO_RCV_bit = 1 << 2,
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PFP_HALTED_BY_INSTR_VIOLATION_bit = 1 << 3,
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MULTIPASS_IB_PENDING_IN_PFP_bit = 1 << 4,
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ME_BRUSH_WC_NOT_RDY_TO_RCV_bit = 1 << 8,
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ME_STALLED_ON_BRUSH_LOGIC_bit = 1 << 9,
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CR_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 10,
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GFX_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 11,
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ME_RCIU_NOT_RDY_TO_RCV_bit = 1 << 12,
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ME_TO_CONST_NOT_RDY_TO_RCV_bit = 1 << 13,
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ME_WAITING_DATA_FROM_PFP_bit = 1 << 14,
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ME_WAITING_ON_PARTIAL_FLUSH_bit = 1 << 15,
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RECT_FIFO_NEEDS_CR_RECT_DONE_bit = 1 << 16,
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RECT_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 17,
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EOPD_FIFO_NEEDS_SC_EOP_DONE_bit = 1 << 18,
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EOPD_FIFO_NEEDS_SMX_EOP_DONE_bit = 1 << 19,
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EOPD_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 20,
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EOPD_FIFO_NEEDS_SIGNAL_SEM_bit = 1 << 21,
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SO_NUMPRIM_FIFO_NEEDS_SOADDR_bit = 1 << 22,
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SO_NUMPRIM_FIFO_NEEDS_NUMPRIM_bit = 1 << 23,
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PIPE_STATS_FIFO_NEEDS_SAMPLE_bit = 1 << 24,
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SURF_SYNC_NEEDS_IDLE_CNTXS_bit = 1 << 30,
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SURF_SYNC_NEEDS_ALL_CLEAN_bit = 1 << 31,
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CP_BUSY_STAT = 0x867c,
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REG_BUS_FIFO_BUSY_bit = 1 << 0,
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RING_FETCHING_DATA_bit = 1 << 1,
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INDR1_FETCHING_DATA_bit = 1 << 2,
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INDR2_FETCHING_DATA_bit = 1 << 3,
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STATE_FETCHING_DATA_bit = 1 << 4,
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PRED_FETCHING_DATA_bit = 1 << 5,
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COHER_CNTR_NEQ_ZERO_bit = 1 << 6,
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PFP_PARSING_PACKETS_bit = 1 << 7,
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ME_PARSING_PACKETS_bit = 1 << 8,
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RCIU_PFP_BUSY_bit = 1 << 9,
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RCIU_ME_BUSY_bit = 1 << 10,
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OUTSTANDING_READ_TAGS_bit = 1 << 11,
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SEM_CMDFIFO_NOT_EMPTY_bit = 1 << 12,
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SEM_FAILED_AND_HOLDING_bit = 1 << 13,
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SEM_POLLING_FOR_PASS_bit = 1 << 14,
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_3D_BUSY_bit = 1 << 15,
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_2D_BUSY_bit = 1 << 16,
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CP_STAT = 0x8680,
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CSF_RING_BUSY_bit = 1 << 0,
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CSF_WPTR_POLL_BUSY_bit = 1 << 1,
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CSF_INDIRECT1_BUSY_bit = 1 << 2,
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CSF_INDIRECT2_BUSY_bit = 1 << 3,
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CSF_STATE_BUSY_bit = 1 << 4,
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CSF_PREDICATE_BUSY_bit = 1 << 5,
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CSF_BUSY_bit = 1 << 6,
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MIU_RDREQ_BUSY_bit = 1 << 7,
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MIU_WRREQ_BUSY_bit = 1 << 8,
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ROQ_RING_BUSY_bit = 1 << 9,
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ROQ_INDIRECT1_BUSY_bit = 1 << 10,
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ROQ_INDIRECT2_BUSY_bit = 1 << 11,
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ROQ_STATE_BUSY_bit = 1 << 12,
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ROQ_PREDICATE_BUSY_bit = 1 << 13,
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ROQ_ALIGN_BUSY_bit = 1 << 14,
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PFP_BUSY_bit = 1 << 15,
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MEQ_BUSY_bit = 1 << 16,
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ME_BUSY_bit = 1 << 17,
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QUERY_BUSY_bit = 1 << 18,
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SEMAPHORE_BUSY_bit = 1 << 19,
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INTERRUPT_BUSY_bit = 1 << 20,
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SURFACE_SYNC_BUSY_bit = 1 << 21,
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DMA_BUSY_bit = 1 << 22,
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RCIU_BUSY_bit = 1 << 23,
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CP_STAT__CP_BUSY_bit = 1 << 31,
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CP_ME_CNTL = 0x86d8,
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ME_STATMUX_mask = 0xff << 0,
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ME_STATMUX_shift = 0,
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ME_HALT_bit = 1 << 28,
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CP_ME_STATUS = 0x86dc,
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CP_RB_RPTR = 0x8700,
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RB_RPTR_mask = 0xfffff << 0,
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RB_RPTR_shift = 0,
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CP_RB_WPTR_DELAY = 0x8704,
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PRE_WRITE_TIMER_mask = 0xfffffff << 0,
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PRE_WRITE_TIMER_shift = 0,
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PRE_WRITE_LIMIT_mask = 0x0f << 28,
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PRE_WRITE_LIMIT_shift = 28,
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CP_ROQ_RB_STAT = 0x8780,
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ROQ_RPTR_PRIMARY_mask = 0x3ff << 0,
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ROQ_RPTR_PRIMARY_shift = 0,
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ROQ_WPTR_PRIMARY_mask = 0x3ff << 16,
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ROQ_WPTR_PRIMARY_shift = 16,
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CP_ROQ_IB1_STAT = 0x8784,
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ROQ_RPTR_INDIRECT1_mask = 0x3ff << 0,
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ROQ_RPTR_INDIRECT1_shift = 0,
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ROQ_WPTR_INDIRECT1_mask = 0x3ff << 16,
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ROQ_WPTR_INDIRECT1_shift = 16,
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CP_ROQ_IB2_STAT = 0x8788,
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ROQ_RPTR_INDIRECT2_mask = 0x3ff << 0,
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ROQ_RPTR_INDIRECT2_shift = 0,
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ROQ_WPTR_INDIRECT2_mask = 0x3ff << 16,
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ROQ_WPTR_INDIRECT2_shift = 16,
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CP_MEQ_STAT = 0x8794,
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MEQ_RPTR_mask = 0x3ff << 0,
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MEQ_RPTR_shift = 0,
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MEQ_WPTR_mask = 0x3ff << 16,
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MEQ_WPTR_shift = 16,
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CC_GC_SHADER_PIPE_CONFIG = 0x8950,
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INACTIVE_QD_PIPES_mask = 0xff << 8,
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INACTIVE_QD_PIPES_shift = 8,
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R6XX_MAX_QD_PIPES = 8,
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INACTIVE_SIMDS_mask = 0xff << 16,
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INACTIVE_SIMDS_shift = 16,
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R6XX_MAX_SIMDS = 8,
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GC_USER_SHADER_PIPE_CONFIG = 0x8954,
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VC_ENHANCE = 0x9714,
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DB_DEBUG = 0x9830,
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PREZ_MUST_WAIT_FOR_POSTZ_DONE = 1 << 31,
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DB_WATERMARKS = 0x00009838,
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DEPTH_FREE_mask = 0x1f << 0,
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DEPTH_FREE_shift = 0,
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DEPTH_FLUSH_mask = 0x3f << 5,
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DEPTH_FLUSH_shift = 5,
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FORCE_SUMMARIZE_mask = 0x0f << 11,
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FORCE_SUMMARIZE_shift = 11,
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DEPTH_PENDING_FREE_mask = 0x1f << 15,
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DEPTH_PENDING_FREE_shift = 15,
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DEPTH_CACHELINE_FREE_mask = 0x1f << 20,
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DEPTH_CACHELINE_FREE_shift = 20,
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EARLY_Z_PANIC_DISABLE_bit = 1 << 25,
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LATE_Z_PANIC_DISABLE_bit = 1 << 26,
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RE_Z_PANIC_DISABLE_bit = 1 << 27,
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DB_EXTRA_DEBUG_mask = 0x0f << 28,
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DB_EXTRA_DEBUG_shift = 28,
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CP_RB_BASE = 0xc100,
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CP_RB_CNTL = 0xc104,
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RB_BUFSZ_mask = 0x3f << 0,
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CP_RB_WPTR = 0xc114,
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RB_WPTR_mask = 0xfffff << 0,
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RB_WPTR_shift = 0,
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CP_RB_RPTR_WR = 0xc108,
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RB_RPTR_WR_mask = 0xfffff << 0,
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RB_RPTR_WR_shift = 0,
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CP_INT_STATUS = 0xc128,
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DISABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 0,
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ENABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 1,
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SEM_SIGNAL_INT_STAT_bit = 1 << 18,
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CNTX_BUSY_INT_STAT_bit = 1 << 19,
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CNTX_EMPTY_INT_STAT_bit = 1 << 20,
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WAITMEM_SEM_INT_STAT_bit = 1 << 21,
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PRIV_INSTR_INT_STAT_bit = 1 << 22,
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PRIV_REG_INT_STAT_bit = 1 << 23,
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OPCODE_ERROR_INT_STAT_bit = 1 << 24,
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SCRATCH_INT_STAT_bit = 1 << 25,
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TIME_STAMP_INT_STAT_bit = 1 << 26,
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RESERVED_BIT_ERROR_INT_STAT_bit = 1 << 27,
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DMA_INT_STAT_bit = 1 << 28,
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IB2_INT_STAT_bit = 1 << 29,
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IB1_INT_STAT_bit = 1 << 30,
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RB_INT_STAT_bit = 1 << 31,
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/* SX_ALPHA_TEST_CONTROL = 0x00028410, */
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ALPHA_FUNC__REF_NEVER = 0,
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ALPHA_FUNC__REF_ALWAYS = 7,
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/* DB_SHADER_CONTROL = 0x0002880c, */
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Z_ORDER__EARLY_Z_THEN_LATE_Z = 2,
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/* PA_SU_SC_MODE_CNTL = 0x00028814, */
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/* POLY_MODE_mask = 0x03 << 3, */
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POLY_MODE__TRIANGLES = 0, POLY_MODE__DUAL_MODE,
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/* POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, */
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POLYMODE_PTYPE__POINTS = 0, POLYMODE_PTYPE__LINES, POLYMODE_PTYPE__TRIANGLES,
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PA_SC_AA_SAMPLE_LOCS_8S_WD1_M = 0x00028c20,
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DB_SRESULTS_COMPARE_STATE0 = 0x00028d28, /* See autoregs: DB_SRESULTS_COMPARE_STATE1 */
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/* DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c, */
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DB_ALPHA_TO_MASK = 0x00028d44,
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ALPHA_TO_MASK_ENABLE = 1 << 0,
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ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8,
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ALPHA_TO_MASK_OFFSET0_shift = 8,
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ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 8,
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ALPHA_TO_MASK_OFFSET1_shift = 10,
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ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 8,
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ALPHA_TO_MASK_OFFSET2_shift = 12,
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ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 8,
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ALPHA_TO_MASK_OFFSET3_shift = 14,
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/* SQ_VTX_CONSTANT_WORD2_0 = 0x00038008, */
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/* SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, */
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FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2,
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FMT_16=5, FMT_16_FLOAT, FMT_8_8,
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FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4,
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FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16,
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FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8,
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FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10,
|
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FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2,
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FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16,
|
|
FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT,
|
|
FMT_1 = 37, FMT_GB_GR=39,
|
|
FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP,
|
|
FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32,
|
|
FMT_32_32_32_FLOAT=48,
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|
|
|
/* High level register file lengths */
|
|
SQ_ALU_CONSTANT = SQ_ALU_CONSTANT0_0, /* 256 PS, 256 VS */
|
|
SQ_ALU_CONSTANT_ps_num = 256,
|
|
SQ_ALU_CONSTANT_vs_num = 256,
|
|
SQ_ALU_CONSTANT_all_num = 512,
|
|
SQ_ALU_CONSTANT_offset = 16,
|
|
SQ_ALU_CONSTANT_ps = 0,
|
|
SQ_ALU_CONSTANT_vs = SQ_ALU_CONSTANT_ps + SQ_ALU_CONSTANT_ps_num,
|
|
SQ_TEX_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */
|
|
SQ_TEX_RESOURCE_ps_num = 160,
|
|
SQ_TEX_RESOURCE_vs_num = 160,
|
|
SQ_TEX_RESOURCE_fs_num = 16,
|
|
SQ_TEX_RESOURCE_gs_num = 160,
|
|
SQ_TEX_RESOURCE_all_num = 496,
|
|
SQ_TEX_RESOURCE_offset = 28,
|
|
SQ_TEX_RESOURCE_ps = 0,
|
|
SQ_TEX_RESOURCE_vs = SQ_TEX_RESOURCE_ps + SQ_TEX_RESOURCE_ps_num,
|
|
SQ_TEX_RESOURCE_fs = SQ_TEX_RESOURCE_vs + SQ_TEX_RESOURCE_vs_num,
|
|
SQ_TEX_RESOURCE_gs = SQ_TEX_RESOURCE_fs + SQ_TEX_RESOURCE_fs_num,
|
|
SQ_VTX_RESOURCE = SQ_VTX_CONSTANT_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */
|
|
SQ_VTX_RESOURCE_ps_num = 160,
|
|
SQ_VTX_RESOURCE_vs_num = 160,
|
|
SQ_VTX_RESOURCE_fs_num = 16,
|
|
SQ_VTX_RESOURCE_gs_num = 160,
|
|
SQ_VTX_RESOURCE_all_num = 496,
|
|
SQ_VTX_RESOURCE_offset = 28,
|
|
SQ_VTX_RESOURCE_ps = 0,
|
|
SQ_VTX_RESOURCE_vs = SQ_VTX_RESOURCE_ps + SQ_VTX_RESOURCE_ps_num,
|
|
SQ_VTX_RESOURCE_fs = SQ_VTX_RESOURCE_vs + SQ_VTX_RESOURCE_vs_num,
|
|
SQ_VTX_RESOURCE_gs = SQ_VTX_RESOURCE_fs + SQ_VTX_RESOURCE_fs_num,
|
|
SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, /* 18 per PS, VS, GS */
|
|
SQ_TEX_SAMPLER_WORD_ps_num = 18,
|
|
SQ_TEX_SAMPLER_WORD_vs_num = 18,
|
|
SQ_TEX_SAMPLER_WORD_gs_num = 18,
|
|
SQ_TEX_SAMPLER_WORD_all_num = 54,
|
|
SQ_TEX_SAMPLER_WORD_offset = 12,
|
|
SQ_TEX_SAMPLER_WORD_ps = 0,
|
|
SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num,
|
|
SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num,
|
|
SQ_LOOP_CONST = SQ_LOOP_CONST_0, /* 32 per PS, VS, GS */
|
|
SQ_LOOP_CONST_ps_num = 32,
|
|
SQ_LOOP_CONST_vs_num = 32,
|
|
SQ_LOOP_CONST_gs_num = 32,
|
|
SQ_LOOP_CONST_all_num = 96,
|
|
SQ_LOOP_CONST_offset = 4,
|
|
SQ_LOOP_CONST_ps = 0,
|
|
SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num,
|
|
SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num,
|
|
SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits per PS, VS, GS */
|
|
SQ_BOOL_CONST_ps_num = 1,
|
|
SQ_BOOL_CONST_vs_num = 1,
|
|
SQ_BOOL_CONST_gs_num = 1,
|
|
SQ_BOOL_CONST_all_num = 3,
|
|
SQ_BOOL_CONST_offset = 4,
|
|
SQ_BOOL_CONST_ps = 0,
|
|
SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num,
|
|
SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num
|
|
};
|
|
|
|
|
|
#endif
|