48566405f6
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@17455 a95241bf-73f2-0310-859d-f6bbb57e9c96
740 lines
20 KiB
C
740 lines
20 KiB
C
/*
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Copyright 1999, Be Incorporated. All Rights Reserved.
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This file may be used under the terms of the Be Sample Code License.
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Other authors:
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Mark Watson,
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Apsed,
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Rudolf Cornelissen 11/2002-5/2006
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*/
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#define MODULE_BIT 0x00200000
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#include "acc_std.h"
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/*
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Enable/Disable interrupts. Just a wrapper around the
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ioctl() to the kernel driver.
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*/
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static void interrupt_enable(bool flag)
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{
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status_t result;
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gx00_set_bool_state sbs;
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if (si->ps.int_assigned)
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{
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/* set the magic number so the driver knows we're for real */
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sbs.magic = GX00_PRIVATE_DATA_MAGIC;
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sbs.do_it = flag;
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/* contact driver and get a pointer to the registers and shared data */
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result = ioctl(fd, GX00_RUN_INTERRUPTS, &sbs, sizeof(sbs));
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}
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}
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/* First validate the mode, then call lots of bit banging stuff to set the mode(s)! */
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status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
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{
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/* BOUNDS WARNING:
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* It's impossible to deviate whatever small amount in a display_mode if the lower
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* and upper limits are the same!
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* Besides:
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* BeOS (tested R5.0.3PE) is failing BWindowScreen::SetFrameBuffer() if PROPOSEMODE
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* returns B_BAD_VALUE!
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* Which means PROPOSEMODE should not return that on anything except on
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* deviations for:
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* display_mode.virtual_width;
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* display_mode.virtual_height;
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* display_mode.timing.h_display;
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* display_mode.timing.v_display;
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* So:
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* We don't use bounds here by making sure bounds and target are the same struct!
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* (See the call to PROPOSE_DISPLAY_MODE below) */
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display_mode /*bounds,*/ target;
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uint8 colour_depth1 = 32;
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status_t result;
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uint32 startadd,startadd_right;
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/* Adjust mode to valid one and fail if invalid */
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target /*= bounds*/ = *mode_to_set;
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/* show the mode bits */
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LOG(1, ("SETMODE: (ENTER) initial modeflags: $%08x\n", target.flags));
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LOG(1, ("SETMODE: requested target pixelclock %dkHz\n", target.timing.pixel_clock));
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LOG(1, ("SETMODE: requested virtual_width %d, virtual_height %d\n",
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target.virtual_width, target.virtual_height));
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/* See BOUNDS WARNING above... */
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if (PROPOSE_DISPLAY_MODE(&target, &target, &target) == B_ERROR) return B_ERROR;
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/* overlay engine, cursor and MOVE_DISPLAY need to know the status even when
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* in singlehead mode */
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si->switched_crtcs = false;
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/* disable interrupts using the kernel driver */
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interrupt_enable(false);
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/* then turn off screen(s) */
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gx00_crtc_dpms(false, false, false);
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if (si->ps.secondary_head)
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{
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g400_crtc2_dpms(false, false, false);
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}
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else
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{
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/* on singlehead cards with TVout program the MAVEN as well */
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if (si->ps.tvout) gx00_maven_dpms(false, false, false);
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}
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/*where in framebuffer the screen is (should this be dependant on previous MOVEDISPLAY?)*/
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startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;
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/* calculate and set new mode bytes_per_row */
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gx00_general_validate_pic_size (&target, &si->fbc.bytes_per_row, &si->acc_mode);
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/*Perform the very long mode switch!*/
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if (target.flags & DUALHEAD_BITS) /*if some dualhead mode*/
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{
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uint8 colour_depth2 = colour_depth1;
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/* init display mode for secondary head */
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display_mode target2 = target;
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LOG(1,("SETMODE: setting DUALHEAD mode\n"));
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/* set the pixel clock PLL(s) */
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LOG(8,("SETMODE: target clock %dkHz\n",target.timing.pixel_clock));
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if (gx00_dac_set_pix_pll(target) == B_ERROR)
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LOG(8,("SETMODE: error setting pixel clock (internal DAC)\n"));
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/* we do not need to set the pixelclock here for a head that's in TVout mode */
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if (!(target2.flags & TV_BITS))
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{
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LOG(8,("SETMODE: target2 clock %dkHz\n",target2.timing.pixel_clock));
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if (gx00_maven_set_vid_pll(target2) == B_ERROR)
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LOG(8,("SETMODE: error setting pixel clock (MAVEN)\n"));
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}
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/*set the colour depth for CRTC1 and the DAC */
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switch(target.space)
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{
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case B_RGB16_LITTLE:
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colour_depth1 = 16;
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gx00_dac_mode(BPP16, 1.0);
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gx00_crtc_depth(BPP16);
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break;
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case B_RGB32_LITTLE:
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colour_depth1 = 32;
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gx00_dac_mode(BPP32, 1.0);
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gx00_crtc_depth(BPP32);
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break;
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}
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/*set the colour depth for CRTC2 and the MAVEN */
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switch(target2.space)
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{
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case B_RGB16_LITTLE:
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colour_depth2 = 16;
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gx00_maven_mode(BPP16, 1.0);
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g400_crtc2_depth(BPP16);
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break;
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case B_RGB32_LITTLE:
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colour_depth2 = 32;
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gx00_maven_mode(BPP32DIR, 1.0);
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g400_crtc2_depth(BPP32DIR);
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break;
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}
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/* check if we are doing interlaced TVout mode */
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si->interlaced_tv_mode = false;
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if ((target2.flags & TV_BITS) && (si->ps.card_type >= G450))
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si->interlaced_tv_mode = true;
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/*set the display(s) pitches*/
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gx00_crtc_set_display_pitch ();
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//fixme: seperate for real dualhead modes:
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//we need a secondary si->fbc!
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g400_crtc2_set_display_pitch ();
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/*work out where the "right" screen starts*/
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startadd_right=startadd+(target.timing.h_display * (colour_depth1 >> 3));
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/* calculate needed MAVEN-CRTC delay: formula valid for straight-through CRTC's */
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si->crtc_delay = 44;
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if (colour_depth2 == 16) si->crtc_delay += 0;
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/* set the outputs */
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switch (si->ps.card_type)
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{
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case G400:
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case G400MAX:
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/* setup vertical timing adjust for crtc connected to the MAVEN:
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* assuming connected straight through. */
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/* (extra "blanking" line for MAVEN hardware design fault) */
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target2.timing.v_display++;
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switch (target.flags & DUALHEAD_BITS)
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{
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case DUALHEAD_ON:
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case DUALHEAD_CLONE:
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gx00_general_dac_select(DS_CRTC1DAC_CRTC2MAVEN);
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si->switched_crtcs = false;
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break;
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case DUALHEAD_SWITCH:
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if (i2c_sec_tv_adapter() == B_OK)
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{
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/* Don't switch CRTC's because MAVEN YUV is impossible then,
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* and primary head output will be limited to 135Mhz pixelclock. */
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LOG(4,("SETMODE: secondary TV-adapter detected, switching buffers\n"));
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gx00_general_dac_select(DS_CRTC1DAC_CRTC2MAVEN);
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si->switched_crtcs = true;
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}
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else
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{
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/* This limits the pixelclocks on both heads to 135Mhz,
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* but you can use overlay on the other output now. */
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LOG(4,("SETMODE: no secondary TV-adapter detected, switching CRTCs\n"));
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gx00_general_dac_select(DS_CRTC1MAVEN_CRTC2DAC);
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si->switched_crtcs = false;
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/* re-calculate MAVEN-CRTC delay: formula valid for crossed CRTC's */
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si->crtc_delay = 17;
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if (colour_depth1 == 16) si->crtc_delay += 4;
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/* re-setup vertical timing adjust for crtc connected to the MAVEN:
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* cross connected. */
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/* (extra "blanking" line for MAVEN hardware design fault) */
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target.timing.v_display++;
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target2.timing.v_display--;
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}
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break;
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}
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break;
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case G450:
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case G550:
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if (!si->ps.primary_dvi)
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/* output connector use is always 'straight-through' */
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//fixme: re-evaluate when DVI is setup...
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{
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switch (target.flags & DUALHEAD_BITS)
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{
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case DUALHEAD_ON:
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case DUALHEAD_CLONE:
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gx00_general_dac_select(DS_CRTC1CON1_CRTC2CON2);
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si->switched_crtcs = false;
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break;
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case DUALHEAD_SWITCH:
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if (i2c_sec_tv_adapter() == B_OK)
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{
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/* Don't switch CRTC's because MAVEN YUV and TVout is impossible then,
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* and primary head output will be limited to 235Mhz pixelclock. */
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LOG(4,("SETMODE: secondary TV-adapter detected, switching buffers\n"));
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gx00_general_dac_select(DS_CRTC1CON1_CRTC2CON2);
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si->switched_crtcs = true;
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}
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else
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{
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/* This limits the pixelclocks on both heads to 235Mhz,
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* but you can use overlay on the other output now. */
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LOG(4,("SETMODE: no secondary TV-adapter detected, switching CRTCs\n"));
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gx00_general_dac_select(DS_CRTC1CON2_CRTC2CON1);
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si->switched_crtcs = false;
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}
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break;
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}
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}
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else
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/* output connector use is cross-linked if no TV cable connected! */
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//fixme: re-evaluate when DVI is setup...
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{
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switch (target.flags & DUALHEAD_BITS)
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{
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case DUALHEAD_ON:
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case DUALHEAD_CLONE:
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if (i2c_sec_tv_adapter() == B_OK)
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{
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gx00_general_dac_select(DS_CRTC1CON1_CRTC2CON2);
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si->switched_crtcs = false;
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}
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else
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{
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/* This limits the pixelclocks on both heads to 235Mhz,
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* but you can use overlay on the other output now. */
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gx00_general_dac_select(DS_CRTC1CON2_CRTC2CON1);
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si->switched_crtcs = false;
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}
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break;
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case DUALHEAD_SWITCH:
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if (i2c_sec_tv_adapter() == B_OK)
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{
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/* Don't switch CRTC's because MAVEN YUV and TVout is impossible then,
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* and primary head output will be limited to 235Mhz pixelclock. */
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LOG(4,("SETMODE: secondary TV-adapter detected, switching buffers\n"));
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gx00_general_dac_select(DS_CRTC1CON1_CRTC2CON2);
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si->switched_crtcs = true;
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}
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else
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{
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LOG(4,("SETMODE: no secondary TV-adapter detected, switching CRTCs\n"));
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gx00_general_dac_select(DS_CRTC1CON1_CRTC2CON2);
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si->switched_crtcs = false;
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}
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break;
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}
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}
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break;
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default:
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break;
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}
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if (si->switched_crtcs)
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{
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uint32 temp = startadd;
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startadd = startadd_right;
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startadd_right = temp;
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}
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/*Tell card what memory to display*/
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switch (target.flags & DUALHEAD_BITS)
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{
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case DUALHEAD_ON:
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case DUALHEAD_SWITCH:
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gx00_crtc_set_display_start(startadd,colour_depth1);
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g400_crtc2_set_display_start(startadd_right,colour_depth2);
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break;
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case DUALHEAD_CLONE:
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gx00_crtc_set_display_start(startadd,colour_depth1);
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g400_crtc2_set_display_start(startadd,colour_depth2);
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break;
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}
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/* set the timing */
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gx00_crtc_set_timing(target);
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/* we do not need to setup CRTC2 here for a head that's in TVout mode */
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if (!(target2.flags & TV_BITS)) result = g400_crtc2_set_timing(target2);
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/* TVout support: setup CRTC2 and it's pixelclock */
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if (si->ps.tvout && (target2.flags & TV_BITS)) maventv_init(target2);
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}
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else /* single head mode */
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{
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status_t status;
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int colour_mode = BPP32;
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switch(target.space)
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{
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case B_CMAP8:
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colour_depth1 = 8;
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colour_mode = BPP8;
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break;
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case B_RGB15_LITTLE:
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colour_depth1 = 16;
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colour_mode = BPP15;
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break;
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case B_RGB16_LITTLE:
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colour_depth1 = 16;
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colour_mode = BPP16;
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break;
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case B_RGB32_LITTLE:
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colour_depth1 = 32;
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colour_mode = BPP32;
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break;
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default:
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LOG(8,("SETMODE: Invalid singlehead colour depth 0x%08x\n", target.space));
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return B_ERROR;
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}
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/* set the pixel clock PLL */
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if (si->ps.card_type >= G100)
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//fixme: how about when TVout is enabled???
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status = gx00_dac_set_pix_pll(target);
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else
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{
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status = mil2_dac_set_pix_pll((target.timing.pixel_clock)/1000.0, colour_depth1);
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}
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if (status==B_ERROR)
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LOG(8,("CRTC: error setting pixel clock (internal DAC)\n"));
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/* set the colour depth for CRTC1 and the DAC */
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gx00_dac_mode(colour_mode,1.0);
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gx00_crtc_depth(colour_mode);
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/* if we do TVout mode, its non-interlaced (as we are on <= G400MAX for sure) */
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si->interlaced_tv_mode = false;
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/* set the display pitch */
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gx00_crtc_set_display_pitch();
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/* tell the card what memory to display */
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gx00_crtc_set_display_start(startadd,colour_depth1);
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/* enable primary analog output */
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switch (si->ps.card_type)
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{
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case G100:
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case G200:
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case G400:
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case G400MAX:
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if (!si->ps.secondary_head && si->ps.tvout && (target.flags & TV_BITS))
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gx00_general_dac_select(DS_CRTC1MAVEN);
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else
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gx00_general_dac_select(DS_CRTC1DAC);
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break;
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case G450:
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case G550:
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gx00_general_dac_select(DS_CRTC1CON1_CRTC2CON2);
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gx50_general_output_select();
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break;
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default:
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break;
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}
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/* set the timing */
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if (!si->ps.secondary_head && si->ps.tvout && (target.flags & TV_BITS))
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{
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/* calculate MAVEN-CRTC delay: only used during TVout */
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si->crtc_delay = 17;
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if (colour_depth1 == 16) si->crtc_delay += 4;
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/* setup CRTC1 and it's pixelclock for TVout */
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maventv_init(target);
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}
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else
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{
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gx00_maven_shutoff();
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gx00_crtc_set_timing(target);
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}
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}
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/* update driver's mode store */
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si->dm = target;
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/* set up acceleration for this mode */
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gx00_acc_init();
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/* restore screen(s) output state(s) */
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SET_DPMS_MODE(si->dpms_flags);
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/* clear line at bottom of screen if dualhead mode:
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* MAVEN hardware design fault 'fix'.
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* Note:
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* Not applicable for singlehead cards with a MAVEN, since it's only used
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* for TVout there. */
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if ((target.flags & DUALHEAD_BITS) && (si->ps.card_type <= G400MAX))
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gx00_maven_clrline();
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LOG(1,("SETMODE: booted since %f mS\n", system_time()/1000.0));
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/* enable interrupts using the kernel driver */
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interrupt_enable(true);
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/* optimize memory-access if needed */
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gx00_crtc_mem_priority(colour_depth1);
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/* Tune RAM CAS-latency if needed. Must be done *here*! */
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mga_set_cas_latency();
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return B_OK;
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}
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/*
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Set which pixel of the virtual frame buffer will show up in the
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top left corner of the display device. Used for page-flipping
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games and virtual desktops.
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*/
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status_t MOVE_DISPLAY(uint16 h_display_start, uint16 v_display_start) {
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uint8 colour_depth;
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uint32 startadd,startadd_right;
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LOG(4,("MOVE_DISPLAY: h %d, v %d\n", h_display_start, v_display_start));
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/* G400 CRTC1 handles multiples of 8 for 8bit, 4 for 16bit, 2 for 32 bit
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G400 CRTC2 handles multiples of 32 for 16-bit and 16 for 32-bit - must stoop to this in dualhead
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*/
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/* reset lower bits, don't return an error! */
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if (si->dm.flags & DUALHEAD_BITS)
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{
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switch(si->dm.space)
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{
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case B_RGB16_LITTLE:
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colour_depth=16;
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h_display_start &= ~0x1f;
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break;
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case B_RGB32_LITTLE:
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colour_depth=32;
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h_display_start &= ~0x0f;
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break;
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default:
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LOG(8,("SET:Invalid DH colour depth 0x%08x, should never happen\n", si->dm.space));
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return B_ERROR;
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}
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}
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else
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{
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switch(si->dm.space)
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{
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case B_CMAP8:
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colour_depth=8;
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h_display_start &= ~0x07;
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break;
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case B_RGB15_LITTLE: case B_RGB16_LITTLE:
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colour_depth=16;
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h_display_start &= ~0x03;
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break;
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case B_RGB32_LITTLE:
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colour_depth=32;
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h_display_start &= ~0x01;
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break;
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default:
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return B_ERROR;
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}
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}
|
|
|
|
/* do not run past end of display */
|
|
switch (si->dm.flags & DUALHEAD_BITS)
|
|
{
|
|
case DUALHEAD_ON:
|
|
case DUALHEAD_SWITCH:
|
|
if (((si->dm.timing.h_display * 2) + h_display_start) > si->dm.virtual_width)
|
|
return B_ERROR;
|
|
break;
|
|
default:
|
|
if ((si->dm.timing.h_display + h_display_start) > si->dm.virtual_width)
|
|
return B_ERROR;
|
|
break;
|
|
}
|
|
if ((si->dm.timing.v_display + v_display_start) > si->dm.virtual_height)
|
|
return B_ERROR;
|
|
|
|
/* everybody remember where we parked... */
|
|
si->dm.h_display_start = h_display_start;
|
|
si->dm.v_display_start = v_display_start;
|
|
|
|
/* actually set the registers */
|
|
//fixme: seperate both heads: we need a secondary si->fbc!
|
|
startadd = v_display_start * si->fbc.bytes_per_row;
|
|
startadd += h_display_start * (colour_depth >> 3);
|
|
startadd += (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;
|
|
startadd_right = startadd + si->dm.timing.h_display * (colour_depth >> 3);
|
|
|
|
/* account for switched CRTC's */
|
|
if (si->switched_crtcs)
|
|
{
|
|
uint32 temp = startadd;
|
|
startadd = startadd_right;
|
|
startadd_right = temp;
|
|
}
|
|
|
|
interrupt_enable(false);
|
|
|
|
switch (si->dm.flags&DUALHEAD_BITS)
|
|
{
|
|
case DUALHEAD_ON:
|
|
case DUALHEAD_SWITCH:
|
|
gx00_crtc_set_display_start(startadd,colour_depth);
|
|
g400_crtc2_set_display_start(startadd_right,colour_depth);
|
|
break;
|
|
case DUALHEAD_OFF:
|
|
gx00_crtc_set_display_start(startadd,colour_depth);
|
|
break;
|
|
case DUALHEAD_CLONE:
|
|
gx00_crtc_set_display_start(startadd,colour_depth);
|
|
g400_crtc2_set_display_start(startadd,colour_depth);
|
|
break;
|
|
}
|
|
|
|
interrupt_enable(true);
|
|
return B_OK;
|
|
}
|
|
|
|
/*
|
|
Set the indexed color palette.
|
|
*/
|
|
void SET_INDEXED_COLORS(uint count, uint8 first, uint8 *color_data, uint32 flags) {
|
|
int i;
|
|
uint8 *r,*g,*b;
|
|
|
|
/* Protect gamma correction when not in CMAP8 */
|
|
if (si->dm.space != B_CMAP8) return;
|
|
|
|
r=si->color_data;
|
|
g=r+256;
|
|
b=g+256;
|
|
|
|
i=first;
|
|
while (count--)
|
|
{
|
|
r[i]=*color_data++;
|
|
g[i]=*color_data++;
|
|
b[i]=*color_data++;
|
|
i++;
|
|
}
|
|
gx00_dac_palette(r,g,b);
|
|
}
|
|
|
|
/* Put the display into one of the Display Power Management modes. */
|
|
status_t SET_DPMS_MODE(uint32 dpms_flags)
|
|
{
|
|
interrupt_enable(false);
|
|
|
|
LOG(4,("SET_DPMS_MODE: 0x%08x\n", dpms_flags));
|
|
|
|
/* note current DPMS state for our reference */
|
|
si->dpms_flags = dpms_flags;
|
|
|
|
if (si->dm.flags & DUALHEAD_BITS) /* dualhead */
|
|
{
|
|
switch(dpms_flags)
|
|
{
|
|
case B_DPMS_ON: /* H: on, V: on */
|
|
gx00_crtc_dpms(true, true, true);
|
|
if (si->ps.secondary_head) g400_crtc2_dpms(true, true, true);
|
|
break;
|
|
case B_DPMS_STAND_BY:
|
|
if (si->settings.greensync)
|
|
{
|
|
/* blank screen, but keep sync running */
|
|
gx00_crtc_dpms(false, true, true);
|
|
}
|
|
else
|
|
{
|
|
gx00_crtc_dpms(false, false, true);
|
|
}
|
|
if (si->ps.secondary_head)
|
|
{
|
|
if ((si->dm.flags & TV_BITS) && (si->ps.card_type > G400MAX))
|
|
{
|
|
/* keep display enabled in TVout modes for G450 and G550! */
|
|
g400_crtc2_dpms(true, false, true);
|
|
}
|
|
else
|
|
{
|
|
g400_crtc2_dpms(false, false, true);
|
|
}
|
|
}
|
|
break;
|
|
case B_DPMS_SUSPEND:
|
|
if (si->settings.greensync)
|
|
{
|
|
/* blank screen, but keep sync running */
|
|
gx00_crtc_dpms(false, true, true);
|
|
}
|
|
else
|
|
{
|
|
gx00_crtc_dpms(false, true, false);
|
|
}
|
|
if (si->ps.secondary_head)
|
|
{
|
|
if ((si->dm.flags & TV_BITS) && (si->ps.card_type > G400MAX))
|
|
{
|
|
/* keep display enabled in TVout modes for G450 and G550! */
|
|
g400_crtc2_dpms(true, true, false);
|
|
}
|
|
else
|
|
{
|
|
g400_crtc2_dpms(false, true, false);
|
|
}
|
|
}
|
|
break;
|
|
case B_DPMS_OFF: /* H: off, V: off, display off */
|
|
if (si->settings.greensync)
|
|
{
|
|
/* blank screen, but keep sync running */
|
|
gx00_crtc_dpms(false, true, true);
|
|
}
|
|
else
|
|
{
|
|
gx00_crtc_dpms(false, false, false);
|
|
}
|
|
if (si->ps.secondary_head)
|
|
{
|
|
if ((si->dm.flags & TV_BITS) && (si->ps.card_type > G400MAX))
|
|
{
|
|
/* keep display enabled in TVout modes for G450 and G550! */
|
|
g400_crtc2_dpms(true, false, false);
|
|
}
|
|
else
|
|
{
|
|
g400_crtc2_dpms(false, false, false);
|
|
}
|
|
}
|
|
break;
|
|
default:
|
|
LOG(8,("SET: Invalid DPMS settings (DH) 0x%08x\n", dpms_flags));
|
|
interrupt_enable(true);
|
|
return B_ERROR;
|
|
}
|
|
}
|
|
else /* singlehead */
|
|
{
|
|
switch(dpms_flags)
|
|
{
|
|
case B_DPMS_ON: /* H: on, V: on */
|
|
gx00_crtc_dpms(true, true, true);
|
|
/* on singlehead cards with TVout program the MAVEN as well */
|
|
if (si->dm.flags & TV_BITS) gx00_maven_dpms(true, true, true);
|
|
break;
|
|
case B_DPMS_STAND_BY:
|
|
if (si->settings.greensync)
|
|
{
|
|
/* blank screen, but keep sync running */
|
|
gx00_crtc_dpms(false, true, true);
|
|
}
|
|
else
|
|
{
|
|
gx00_crtc_dpms(false, false, true);
|
|
}
|
|
/* on singlehead cards with TVout program the MAVEN as well */
|
|
if (si->dm.flags & TV_BITS) gx00_maven_dpms(false, false, true);
|
|
break;
|
|
case B_DPMS_SUSPEND:
|
|
if (si->settings.greensync)
|
|
{
|
|
/* blank screen, but keep sync running */
|
|
gx00_crtc_dpms(false, true, true);
|
|
}
|
|
else
|
|
{
|
|
gx00_crtc_dpms(false, true, false);
|
|
}
|
|
/* on singlehead cards with TVout program the MAVEN as well */
|
|
if (si->dm.flags & TV_BITS) gx00_maven_dpms(false, true, false);
|
|
break;
|
|
case B_DPMS_OFF: /* H: off, V: off, display off */
|
|
if (si->settings.greensync)
|
|
{
|
|
/* blank screen, but keep sync running */
|
|
gx00_crtc_dpms(false, true, true);
|
|
}
|
|
else
|
|
{
|
|
gx00_crtc_dpms(false, false, false);
|
|
}
|
|
/* on singlehead cards with TVout program the MAVEN as well */
|
|
if (si->dm.flags & TV_BITS) gx00_maven_dpms(false, false, false);
|
|
break;
|
|
default:
|
|
LOG(8,("SET: Invalid DPMS settings (SH) 0x%08x\n", dpms_flags));
|
|
interrupt_enable(true);
|
|
return B_ERROR;
|
|
}
|
|
}
|
|
interrupt_enable(true);
|
|
return B_OK;
|
|
}
|
|
|
|
/* Report device DPMS capabilities. */
|
|
uint32 DPMS_CAPABILITIES(void)
|
|
{
|
|
if (si->settings.greensync)
|
|
/* we can blank the screen on CRTC1, G400 CRTC2 does not support intermediate
|
|
* modes anyway. */
|
|
//fixme: G450/G550 support full DPMS on CRTC2...
|
|
return B_DPMS_ON | B_DPMS_OFF;
|
|
else
|
|
/* normally CRTC1 supports full DPMS (and on G450/G550 CRTC2 also).. */
|
|
return B_DPMS_ON | B_DPMS_STAND_BY | B_DPMS_SUSPEND | B_DPMS_OFF;
|
|
}
|
|
|
|
/* Return the current DPMS mode. */
|
|
uint32 DPMS_MODE(void)
|
|
{
|
|
return si->dpms_flags;
|
|
}
|