025d4eed52
There were a large number if incorrect, duplicated, misplaced registers that were leading to bugs in the code. This is my first shot at cleaning them up. Luckly as we are using AtomBIOS the number of registers we need to know about is shrinking. * remove registers left over from register banging days * r770 is less then r710, r720 in the drm sources. Fix in code. * enable newer radeons for testing git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42930 a95241bf-73f2-0310-859d-f6bbb57e9c96
371 lines
9.7 KiB
C
371 lines
9.7 KiB
C
/*
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* Copyright 2006-2011, Haiku, Inc. All Rights Reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Axel Dörfler, axeld@pinc-software.de
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* Alexander von Gluck IV, kallisti5@unixzen.com
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*/
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#ifndef RADEON_HD_H
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#define RADEON_HD_H
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#include "lock.h"
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#include "radeon_reg.h"
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#include "avivo.h"
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#include "r500_reg.h"
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#include "r600_reg.h"
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#include "r700_reg.h"
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#include "r800_reg.h"
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#include <Accelerant.h>
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#include <Drivers.h>
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#include <edid.h>
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#include <PCI.h>
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#define VENDOR_ID_ATI 0x1002
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// Card models
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#define RADEON_R520 0x0520 // Fudo
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#define RADEON_R580 0x0580 // Rodin
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#define RADEON_R600 0x0600 // Pele
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#define RADEON_R700 0x0700 // Wekiva
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#define RADEON_R1000 0x1000 // Evergreen
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#define RADEON_R2000 0x2000 // Northern Islands
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#define RADEON_R3000 0x3000 // Southern Islands
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#define RADEON_R4000 0x4000 // Not yet known / used
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// Card chipset flags
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#define CHIP_STD (1 << 0) // Standard chipset
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#define CHIP_IGP (1 << 1) // IGP chipset
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#define CHIP_MOBILE (1 << 2) // Mobile chipset
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#define CHIP_DISCREET (1 << 3) // Discreet chipset
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#define CHIP_APU (1 << 4) // APU chipset
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#define DEVICE_NAME "radeon_hd"
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#define RADEON_ACCELERANT_NAME "radeon_hd.accelerant"
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// Used to collect EDID from boot loader
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#define EDID_BOOT_INFO "vesa_edid/v1"
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#define MODES_BOOT_INFO "vesa_modes/v1"
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#define RHD_POWER_ON 0
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#define RHD_POWER_RESET 1 /* off temporarily */
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#define RHD_POWER_SHUTDOWN 2 /* long term shutdown */
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#define RHD_POWER_UNKNOWN 3 /* initial state */
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struct ring_buffer {
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struct lock lock;
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uint32 register_base;
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uint32 offset;
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uint32 size;
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uint32 position;
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uint32 space_left;
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uint8* base;
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};
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struct overlay_registers;
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struct radeon_shared_info {
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uint32 device_index; // accelerant index
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uint32 device_id; // device pciid
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area_id mode_list_area; // area containing display mode list
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uint32 mode_count;
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bool has_rom; // was rom mapped?
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area_id rom_area; // area of mapped rom
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uint32 rom_phys; // rom base location
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uint32 rom_size; // rom size
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uint8* rom; // cloned, memory mapped PCI ROM
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display_mode current_mode;
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uint32 bytes_per_row;
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uint32 bits_per_pixel;
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uint32 dpms_mode;
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area_id registers_area; // area of memory mapped registers
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uint8* status_page;
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addr_t physical_status_page;
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uint32 graphics_memory_size;
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uint8* frame_buffer; // virtual memory mapped FB
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area_id frame_buffer_area; // area of memory mapped FB
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addr_t frame_buffer_phys; // card PCI BAR address of FB
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uint32 frame_buffer_size; // FB size mapped
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bool has_edid;
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edid1_info edid_info;
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struct lock accelerant_lock;
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struct lock engine_lock;
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ring_buffer primary_ring_buffer;
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int32 overlay_channel_used;
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bool overlay_active;
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uint32 overlay_token;
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addr_t physical_overlay_registers;
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uint32 overlay_offset;
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bool hardware_cursor_enabled;
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sem_id vblank_sem;
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uint8* cursor_memory;
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addr_t physical_cursor_memory;
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uint32 cursor_buffer_offset;
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uint32 cursor_format;
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bool cursor_visible;
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uint16 cursor_hot_x;
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uint16 cursor_hot_y;
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uint16 device_chipset;
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uint32 chipsetFlags;
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uint8 dceMajor;
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uint8 dceMinor;
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char device_identifier[32];
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};
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//----------------- ioctl() interface ----------------
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// magic code for ioctls
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#define RADEON_PRIVATE_DATA_MAGIC 'rdhd'
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// list ioctls
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enum {
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RADEON_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1,
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RADEON_GET_DEVICE_NAME,
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RADEON_ALLOCATE_GRAPHICS_MEMORY,
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RADEON_FREE_GRAPHICS_MEMORY
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};
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// retrieve the area_id of the kernel/accelerant shared info
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struct radeon_get_private_data {
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uint32 magic; // magic number
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area_id shared_info_area;
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};
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// allocate graphics memory
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struct radeon_allocate_graphics_memory {
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uint32 magic;
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uint32 size;
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uint32 alignment;
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uint32 flags;
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uint32 buffer_base;
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};
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// free graphics memory
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struct radeon_free_graphics_memory {
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uint32 magic;
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uint32 buffer_base;
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};
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// registers
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#define R6XX_CONFIG_APER_SIZE 0x5430 // r600>
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#define OLD_CONFIG_APER_SIZE 0x0108 // <r600
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#define CONFIG_MEMSIZE 0x5428 // r600>
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// PCI bridge memory management
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// overlay
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#define RADEON_OVERLAY_UPDATE 0x30000
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#define RADEON_OVERLAY_TEST 0x30004
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#define RADEON_OVERLAY_STATUS 0x30008
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#define RADEON_OVERLAY_EXTENDED_STATUS 0x3000c
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#define RADEON_OVERLAY_GAMMA_5 0x30010
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#define RADEON_OVERLAY_GAMMA_4 0x30014
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#define RADEON_OVERLAY_GAMMA_3 0x30018
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#define RADEON_OVERLAY_GAMMA_2 0x3001c
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#define RADEON_OVERLAY_GAMMA_1 0x30020
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#define RADEON_OVERLAY_GAMMA_0 0x30024
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struct overlay_scale {
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uint32 _reserved0 : 3;
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uint32 horizontal_scale_fraction : 12;
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uint32 _reserved1 : 1;
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uint32 horizontal_downscale_factor : 3;
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uint32 _reserved2 : 1;
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uint32 vertical_scale_fraction : 12;
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};
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#define OVERLAY_FORMAT_RGB15 0x2
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#define OVERLAY_FORMAT_RGB16 0x3
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#define OVERLAY_FORMAT_RGB32 0x1
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#define OVERLAY_FORMAT_YCbCr422 0x8
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#define OVERLAY_FORMAT_YCbCr411 0x9
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#define OVERLAY_FORMAT_YCbCr420 0xc
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#define OVERLAY_MIRROR_NORMAL 0x0
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#define OVERLAY_MIRROR_HORIZONTAL 0x1
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#define OVERLAY_MIRROR_VERTICAL 0x2
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// The real overlay registers are written to using an update buffer
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struct overlay_registers {
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uint32 buffer_rgb0;
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uint32 buffer_rgb1;
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uint32 buffer_u0;
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uint32 buffer_v0;
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uint32 buffer_u1;
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uint32 buffer_v1;
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// (0x18) OSTRIDE - overlay stride
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uint16 stride_rgb;
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uint16 stride_uv;
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// (0x1c) YRGB_VPH - Y/RGB vertical phase
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uint16 vertical_phase0_rgb;
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uint16 vertical_phase1_rgb;
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// (0x20) UV_VPH - UV vertical phase
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uint16 vertical_phase0_uv;
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uint16 vertical_phase1_uv;
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// (0x24) HORZ_PH - horizontal phase
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uint16 horizontal_phase_rgb;
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uint16 horizontal_phase_uv;
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// (0x28) INIT_PHS - initial phase shift
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uint32 initial_vertical_phase0_shift_rgb0 : 4;
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uint32 initial_vertical_phase1_shift_rgb0 : 4;
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uint32 initial_horizontal_phase_shift_rgb0 : 4;
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uint32 initial_vertical_phase0_shift_uv : 4;
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uint32 initial_vertical_phase1_shift_uv : 4;
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uint32 initial_horizontal_phase_shift_uv : 4;
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uint32 _reserved0 : 8;
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// (0x2c) DWINPOS - destination window position
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uint16 window_left;
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uint16 window_top;
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// (0x30) DWINSZ - destination window size
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uint16 window_width;
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uint16 window_height;
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// (0x34) SWIDTH - source width
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uint16 source_width_rgb;
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uint16 source_width_uv;
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// (0x38) SWITDHSW - source width in 8 byte steps
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uint16 source_bytes_per_row_rgb;
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uint16 source_bytes_per_row_uv;
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uint16 source_height_rgb;
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uint16 source_height_uv;
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overlay_scale scale_rgb;
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overlay_scale scale_uv;
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// (0x48) OCLRC0 - overlay color correction 0
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uint32 brightness_correction : 8; // signed, -128 to 127
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uint32 _reserved1 : 10;
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uint32 contrast_correction : 9; // fixed point: 3.6 bits
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uint32 _reserved2 : 5;
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// (0x4c) OCLRC1 - overlay color correction 1
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uint32 saturation_cos_correction : 10; // fixed point: 3.7 bits
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uint32 _reserved3 : 6;
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uint32 saturation_sin_correction : 11; // signed fixed point: 3.7 bits
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uint32 _reserved4 : 5;
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// (0x50) DCLRKV - destination color key value
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uint32 color_key_blue : 8;
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uint32 color_key_green : 8;
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uint32 color_key_red : 8;
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uint32 _reserved5 : 8;
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// (0x54) DCLRKM - destination color key mask
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uint32 color_key_mask_blue : 8;
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uint32 color_key_mask_green : 8;
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uint32 color_key_mask_red : 8;
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uint32 _reserved6 : 7;
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uint32 color_key_enabled : 1;
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// (0x58) SCHRKVH - source chroma key high value
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uint32 source_chroma_key_high_red : 8;
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uint32 source_chroma_key_high_blue : 8;
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uint32 source_chroma_key_high_green : 8;
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uint32 _reserved7 : 8;
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// (0x5c) SCHRKVL - source chroma key low value
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uint32 source_chroma_key_low_red : 8;
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uint32 source_chroma_key_low_blue : 8;
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uint32 source_chroma_key_low_green : 8;
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uint32 _reserved8 : 8;
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// (0x60) SCHRKEN - source chroma key enable
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uint32 _reserved9 : 24;
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uint32 source_chroma_key_red_enabled : 1;
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uint32 source_chroma_key_blue_enabled : 1;
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uint32 source_chroma_key_green_enabled : 1;
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uint32 _reserved10 : 5;
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// (0x64) OCONFIG - overlay configuration
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uint32 _reserved11 : 3;
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uint32 color_control_output_mode : 1;
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uint32 yuv_to_rgb_bypass : 1;
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uint32 _reserved12 : 11;
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uint32 gamma2_enabled : 1;
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uint32 _reserved13 : 1;
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uint32 select_pipe : 1;
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uint32 slot_time : 8;
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uint32 _reserved14 : 5;
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// (0x68) OCOMD - overlay command
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uint32 overlay_enabled : 1;
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uint32 active_field : 1;
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uint32 active_buffer : 2;
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uint32 test_mode : 1;
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uint32 buffer_field_mode : 1;
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uint32 _reserved15 : 1;
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uint32 tv_flip_field_enabled : 1;
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uint32 _reserved16 : 1;
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uint32 tv_flip_field_parity : 1;
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uint32 source_format : 4;
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uint32 ycbcr422_order : 2;
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uint32 _reserved18 : 1;
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uint32 mirroring_mode : 2;
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uint32 _reserved19 : 13;
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uint32 _reserved20;
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uint32 start_0y;
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uint32 start_1y;
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uint32 start_0u;
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uint32 start_0v;
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uint32 start_1u;
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uint32 start_1v;
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uint32 _reserved21[6];
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#if 0
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// (0x70) AWINPOS - alpha blend window position
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uint32 awinpos;
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// (0x74) AWINSZ - alpha blend window size
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uint32 awinsz;
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uint32 _reserved21[10];
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#endif
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// (0xa0) FASTHSCALE - fast horizontal downscale (strangely enough,
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// the next two registers switch the usual Y/RGB vs. UV order)
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uint16 horizontal_scale_uv;
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uint16 horizontal_scale_rgb;
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// (0xa4) UVSCALEV - vertical downscale
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uint16 vertical_scale_uv;
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uint16 vertical_scale_rgb;
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uint32 _reserved22[86];
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// (0x200) polyphase filter coefficients
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uint16 vertical_coefficients_rgb[128];
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uint16 horizontal_coefficients_rgb[128];
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uint32 _reserved23[64];
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// (0x500)
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uint16 vertical_coefficients_uv[128];
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uint16 horizontal_coefficients_uv[128];
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};
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struct hardware_status {
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uint32 interrupt_status_register;
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uint32 _reserved0[3];
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void* primary_ring_head_storage;
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uint32 _reserved1[3];
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void* secondary_ring_0_head_storage;
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void* secondary_ring_1_head_storage;
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uint32 _reserved2[2];
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void* binning_head_storage;
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uint32 _reserved3[3];
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uint32 store[1008];
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};
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#endif /* RADEON_HD_H */
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