7649 lines
677 KiB
C
7649 lines
677 KiB
C
/*
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* DCE_11_0 Register documentation
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*
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* Copyright (C) 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef DCE_11_0_D_H
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#define DCE_11_0_D_H
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#define CAR_mmPIPE0_PG_CONFIG 0x2c0
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#define CAR_mmPIPE0_PG_ENABLE 0x2c1
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#define CAR_mmPIPE0_PG_STATUS 0x2c2
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#define CAR_mmPIPE1_PG_CONFIG 0x2c3
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#define CAR_mmPIPE1_PG_ENABLE 0x2c4
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#define CAR_mmPIPE1_PG_STATUS 0x2c5
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#define CAR_mmPIPE2_PG_CONFIG 0x2c6
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#define CAR_mmPIPE2_PG_ENABLE 0x2c7
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#define CAR_mmPIPE2_PG_STATUS 0x2c8
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#define CAR_mmDCFEV0_PG_CONFIG 0x2db
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#define CAR_mmDCFEV0_PG_ENABLE 0x2dc
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#define CAR_mmDCFEV0_PG_STATUS 0x2dd
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#define CAR_mmDCPG_INTERRUPT_STATUS 0x2de
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#define CAR_mmDCPG_INTERRUPT_CONTROL 0x2df
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#define CAR_mmDC_IP_REQUEST_CNTL 0x2d2
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#define CAR_mmDC_PGFSM_CONFIG_REG 0x2d3
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#define CAR_mmDC_PGFSM_WRITE_REG 0x2d4
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#define CAR_mmDC_PGCNTL_STATUS_REG 0x2d5
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#define CAR_mmDCPG_TEST_DEBUG_INDEX 0x2d6
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#define CAR_mmDCPG_TEST_DEBUG_DATA 0x2d7
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#define CAR_mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628
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#define CAR_mmBL1_PWM_USER_LEVEL 0x1629
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#define CAR_mmBL1_PWM_TARGET_ABM_LEVEL 0x162a
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#define CAR_mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b
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#define CAR_mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c
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#define CAR_mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d
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#define CAR_mmBL1_PWM_ABM_CNTL 0x162e
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#define CAR_mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f
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#define CAR_mmBL1_PWM_GRP2_REG_LOCK 0x1630
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#define CAR_mmDC_ABM1_CNTL 0x1638
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#define CAR_mmDC_ABM1_IPCSC_COEFF_SEL 0x1639
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#define CAR_mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a
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#define CAR_mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b
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#define CAR_mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c
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#define CAR_mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d
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#define CAR_mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e
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#define CAR_mmDC_ABM1_ACE_THRES_12 0x163f
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#define CAR_mmDC_ABM1_ACE_THRES_34 0x1640
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#define CAR_mmDC_ABM1_ACE_CNTL_MISC 0x1641
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#define CAR_mmDC_ABM1_DEBUG_MISC 0x1649
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#define CAR_mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a
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#define CAR_mmDC_ABM1_HG_MISC_CTRL 0x164b
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#define CAR_mmDC_ABM1_LS_SUM_OF_LUMA 0x164c
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#define CAR_mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d
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#define CAR_mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e
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#define CAR_mmDC_ABM1_LS_PIXEL_COUNT 0x164f
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#define CAR_mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650
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#define CAR_mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651
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#define CAR_mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652
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#define CAR_mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653
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#define CAR_mmDC_ABM1_HG_SAMPLE_RATE 0x1654
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#define CAR_mmDC_ABM1_LS_SAMPLE_RATE 0x1655
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#define CAR_mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656
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#define CAR_mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657
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#define CAR_mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658
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#define CAR_mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659
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#define CAR_mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a
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#define CAR_mmDC_ABM1_HG_RESULT_1 0x165b
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#define CAR_mmDC_ABM1_HG_RESULT_2 0x165c
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#define CAR_mmDC_ABM1_HG_RESULT_3 0x165d
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#define CAR_mmDC_ABM1_HG_RESULT_4 0x165e
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#define CAR_mmDC_ABM1_HG_RESULT_5 0x165f
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#define CAR_mmDC_ABM1_HG_RESULT_6 0x1660
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#define CAR_mmDC_ABM1_HG_RESULT_7 0x1661
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#define CAR_mmDC_ABM1_HG_RESULT_8 0x1662
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#define CAR_mmDC_ABM1_HG_RESULT_9 0x1663
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#define CAR_mmDC_ABM1_HG_RESULT_10 0x1664
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#define CAR_mmDC_ABM1_HG_RESULT_11 0x1665
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#define CAR_mmDC_ABM1_HG_RESULT_12 0x1666
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#define CAR_mmDC_ABM1_HG_RESULT_13 0x1667
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#define CAR_mmDC_ABM1_HG_RESULT_14 0x1668
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#define CAR_mmDC_ABM1_HG_RESULT_15 0x1669
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#define CAR_mmDC_ABM1_HG_RESULT_16 0x166a
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#define CAR_mmDC_ABM1_HG_RESULT_17 0x166b
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#define CAR_mmDC_ABM1_HG_RESULT_18 0x166c
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#define CAR_mmDC_ABM1_HG_RESULT_19 0x166d
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#define CAR_mmDC_ABM1_HG_RESULT_20 0x166e
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#define CAR_mmDC_ABM1_HG_RESULT_21 0x166f
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#define CAR_mmDC_ABM1_HG_RESULT_22 0x1670
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#define CAR_mmDC_ABM1_HG_RESULT_23 0x1671
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#define CAR_mmDC_ABM1_HG_RESULT_24 0x1672
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#define CAR_mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b
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#define CAR_mmDC_ABM1_BL_MASTER_LOCK 0x169c
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#define CAR_mmABM_TEST_DEBUG_INDEX 0x169e
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#define CAR_mmABM_TEST_DEBUG_DATA 0x169f
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#define CAR_mmCRTC_H_BLANK_EARLY_NUM 0x1b7d
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#define CAR_mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7d
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#define CAR_mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1d7d
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#define CAR_mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x1f7d
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#define CAR_mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x417d
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#define CAR_mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x437d
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#define CAR_mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x457d
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#define CAR_mmCRTC_H_TOTAL 0x1b80
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#define CAR_mmCRTC0_CRTC_H_TOTAL 0x1b80
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#define CAR_mmCRTC1_CRTC_H_TOTAL 0x1d80
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#define CAR_mmCRTC2_CRTC_H_TOTAL 0x1f80
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#define CAR_mmCRTC3_CRTC_H_TOTAL 0x4180
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#define CAR_mmCRTC4_CRTC_H_TOTAL 0x4380
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#define CAR_mmCRTC5_CRTC_H_TOTAL 0x4580
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#define CAR_mmCRTC_H_BLANK_START_END 0x1b81
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#define CAR_mmCRTC0_CRTC_H_BLANK_START_END 0x1b81
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#define CAR_mmCRTC1_CRTC_H_BLANK_START_END 0x1d81
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#define CAR_mmCRTC2_CRTC_H_BLANK_START_END 0x1f81
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#define CAR_mmCRTC3_CRTC_H_BLANK_START_END 0x4181
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#define CAR_mmCRTC4_CRTC_H_BLANK_START_END 0x4381
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#define CAR_mmCRTC5_CRTC_H_BLANK_START_END 0x4581
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#define CAR_mmCRTC_H_SYNC_A 0x1b82
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#define CAR_mmCRTC0_CRTC_H_SYNC_A 0x1b82
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#define CAR_mmCRTC1_CRTC_H_SYNC_A 0x1d82
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#define CAR_mmCRTC2_CRTC_H_SYNC_A 0x1f82
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#define CAR_mmCRTC3_CRTC_H_SYNC_A 0x4182
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#define CAR_mmCRTC4_CRTC_H_SYNC_A 0x4382
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#define CAR_mmCRTC5_CRTC_H_SYNC_A 0x4582
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#define CAR_mmCRTC_H_SYNC_A_CNTL 0x1b83
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#define CAR_mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1b83
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#define CAR_mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1d83
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#define CAR_mmCRTC2_CRTC_H_SYNC_A_CNTL 0x1f83
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#define CAR_mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4183
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#define CAR_mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4383
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#define CAR_mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4583
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#define CAR_mmCRTC_H_SYNC_B 0x1b84
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#define CAR_mmCRTC0_CRTC_H_SYNC_B 0x1b84
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#define CAR_mmCRTC1_CRTC_H_SYNC_B 0x1d84
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#define CAR_mmCRTC2_CRTC_H_SYNC_B 0x1f84
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#define CAR_mmCRTC3_CRTC_H_SYNC_B 0x4184
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#define CAR_mmCRTC4_CRTC_H_SYNC_B 0x4384
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#define CAR_mmCRTC5_CRTC_H_SYNC_B 0x4584
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#define CAR_mmCRTC_H_SYNC_B_CNTL 0x1b85
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#define CAR_mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1b85
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#define CAR_mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1d85
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#define CAR_mmCRTC2_CRTC_H_SYNC_B_CNTL 0x1f85
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#define CAR_mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4185
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#define CAR_mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4385
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#define CAR_mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4585
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#define CAR_mmCRTC_VBI_END 0x1b86
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#define CAR_mmCRTC0_CRTC_VBI_END 0x1b86
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#define CAR_mmCRTC1_CRTC_VBI_END 0x1d86
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#define CAR_mmCRTC2_CRTC_VBI_END 0x1f86
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#define CAR_mmCRTC3_CRTC_VBI_END 0x4186
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#define CAR_mmCRTC4_CRTC_VBI_END 0x4386
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#define CAR_mmCRTC5_CRTC_VBI_END 0x4586
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#define CAR_mmCRTC_V_TOTAL 0x1b87
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#define CAR_mmCRTC0_CRTC_V_TOTAL 0x1b87
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#define CAR_mmCRTC1_CRTC_V_TOTAL 0x1d87
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#define CAR_mmCRTC2_CRTC_V_TOTAL 0x1f87
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#define CAR_mmCRTC3_CRTC_V_TOTAL 0x4187
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#define CAR_mmCRTC4_CRTC_V_TOTAL 0x4387
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#define CAR_mmCRTC5_CRTC_V_TOTAL 0x4587
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#define CAR_mmCRTC_V_TOTAL_MIN 0x1b88
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#define CAR_mmCRTC0_CRTC_V_TOTAL_MIN 0x1b88
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#define CAR_mmCRTC1_CRTC_V_TOTAL_MIN 0x1d88
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#define CAR_mmCRTC2_CRTC_V_TOTAL_MIN 0x1f88
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#define CAR_mmCRTC3_CRTC_V_TOTAL_MIN 0x4188
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#define CAR_mmCRTC4_CRTC_V_TOTAL_MIN 0x4388
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#define CAR_mmCRTC5_CRTC_V_TOTAL_MIN 0x4588
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#define CAR_mmCRTC_V_TOTAL_MAX 0x1b89
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#define CAR_mmCRTC0_CRTC_V_TOTAL_MAX 0x1b89
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#define CAR_mmCRTC1_CRTC_V_TOTAL_MAX 0x1d89
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#define CAR_mmCRTC2_CRTC_V_TOTAL_MAX 0x1f89
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#define CAR_mmCRTC3_CRTC_V_TOTAL_MAX 0x4189
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#define CAR_mmCRTC4_CRTC_V_TOTAL_MAX 0x4389
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#define CAR_mmCRTC5_CRTC_V_TOTAL_MAX 0x4589
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#define CAR_mmCRTC_V_TOTAL_CONTROL 0x1b8a
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#define CAR_mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1b8a
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#define CAR_mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1d8a
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#define CAR_mmCRTC2_CRTC_V_TOTAL_CONTROL 0x1f8a
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#define CAR_mmCRTC3_CRTC_V_TOTAL_CONTROL 0x418a
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#define CAR_mmCRTC4_CRTC_V_TOTAL_CONTROL 0x438a
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#define CAR_mmCRTC5_CRTC_V_TOTAL_CONTROL 0x458a
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#define CAR_mmCRTC_V_TOTAL_INT_STATUS 0x1b8b
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#define CAR_mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1b8b
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#define CAR_mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1d8b
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#define CAR_mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x1f8b
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#define CAR_mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x418b
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#define CAR_mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x438b
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#define CAR_mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x458b
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#define CAR_mmCRTC_VSYNC_NOM_INT_STATUS 0x1b8c
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#define CAR_mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1b8c
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#define CAR_mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1d8c
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#define CAR_mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x1f8c
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#define CAR_mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x418c
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#define CAR_mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x438c
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#define CAR_mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x458c
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#define CAR_mmCRTC_V_BLANK_START_END 0x1b8d
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#define CAR_mmCRTC0_CRTC_V_BLANK_START_END 0x1b8d
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#define CAR_mmCRTC1_CRTC_V_BLANK_START_END 0x1d8d
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#define CAR_mmCRTC2_CRTC_V_BLANK_START_END 0x1f8d
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#define CAR_mmCRTC3_CRTC_V_BLANK_START_END 0x418d
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#define CAR_mmCRTC4_CRTC_V_BLANK_START_END 0x438d
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#define CAR_mmCRTC5_CRTC_V_BLANK_START_END 0x458d
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#define CAR_mmCRTC_V_SYNC_A 0x1b8e
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#define CAR_mmCRTC0_CRTC_V_SYNC_A 0x1b8e
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#define CAR_mmCRTC1_CRTC_V_SYNC_A 0x1d8e
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#define CAR_mmCRTC2_CRTC_V_SYNC_A 0x1f8e
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#define CAR_mmCRTC3_CRTC_V_SYNC_A 0x418e
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#define CAR_mmCRTC4_CRTC_V_SYNC_A 0x438e
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#define CAR_mmCRTC5_CRTC_V_SYNC_A 0x458e
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#define CAR_mmCRTC_V_SYNC_A_CNTL 0x1b8f
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#define CAR_mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1b8f
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#define CAR_mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1d8f
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#define CAR_mmCRTC2_CRTC_V_SYNC_A_CNTL 0x1f8f
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#define CAR_mmCRTC3_CRTC_V_SYNC_A_CNTL 0x418f
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#define CAR_mmCRTC4_CRTC_V_SYNC_A_CNTL 0x438f
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#define CAR_mmCRTC5_CRTC_V_SYNC_A_CNTL 0x458f
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#define CAR_mmCRTC_V_SYNC_B 0x1b90
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#define CAR_mmCRTC0_CRTC_V_SYNC_B 0x1b90
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#define CAR_mmCRTC1_CRTC_V_SYNC_B 0x1d90
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#define CAR_mmCRTC2_CRTC_V_SYNC_B 0x1f90
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#define CAR_mmCRTC3_CRTC_V_SYNC_B 0x4190
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#define CAR_mmCRTC4_CRTC_V_SYNC_B 0x4390
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#define CAR_mmCRTC5_CRTC_V_SYNC_B 0x4590
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#define CAR_mmCRTC_V_SYNC_B_CNTL 0x1b91
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#define CAR_mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1b91
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#define CAR_mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1d91
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#define CAR_mmCRTC2_CRTC_V_SYNC_B_CNTL 0x1f91
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#define CAR_mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4191
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#define CAR_mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4391
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#define CAR_mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4591
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#define CAR_mmCRTC_DTMTEST_CNTL 0x1b92
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#define CAR_mmCRTC0_CRTC_DTMTEST_CNTL 0x1b92
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#define CAR_mmCRTC1_CRTC_DTMTEST_CNTL 0x1d92
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#define CAR_mmCRTC2_CRTC_DTMTEST_CNTL 0x1f92
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#define CAR_mmCRTC3_CRTC_DTMTEST_CNTL 0x4192
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#define CAR_mmCRTC4_CRTC_DTMTEST_CNTL 0x4392
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#define CAR_mmCRTC5_CRTC_DTMTEST_CNTL 0x4592
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#define CAR_mmCRTC_DTMTEST_STATUS_POSITION 0x1b93
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#define CAR_mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1b93
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#define CAR_mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1d93
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#define CAR_mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x1f93
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#define CAR_mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4193
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#define CAR_mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4393
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#define CAR_mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4593
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#define CAR_mmCRTC_TRIGA_CNTL 0x1b94
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#define CAR_mmCRTC0_CRTC_TRIGA_CNTL 0x1b94
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#define CAR_mmCRTC1_CRTC_TRIGA_CNTL 0x1d94
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#define CAR_mmCRTC2_CRTC_TRIGA_CNTL 0x1f94
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#define CAR_mmCRTC3_CRTC_TRIGA_CNTL 0x4194
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#define CAR_mmCRTC4_CRTC_TRIGA_CNTL 0x4394
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#define CAR_mmCRTC5_CRTC_TRIGA_CNTL 0x4594
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#define CAR_mmCRTC_TRIGA_MANUAL_TRIG 0x1b95
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#define CAR_mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1b95
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#define CAR_mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1d95
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#define CAR_mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x1f95
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#define CAR_mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4195
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#define CAR_mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4395
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#define CAR_mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4595
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#define CAR_mmCRTC_TRIGB_CNTL 0x1b96
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#define CAR_mmCRTC0_CRTC_TRIGB_CNTL 0x1b96
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#define CAR_mmCRTC1_CRTC_TRIGB_CNTL 0x1d96
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#define CAR_mmCRTC2_CRTC_TRIGB_CNTL 0x1f96
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#define CAR_mmCRTC3_CRTC_TRIGB_CNTL 0x4196
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#define CAR_mmCRTC4_CRTC_TRIGB_CNTL 0x4396
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#define CAR_mmCRTC5_CRTC_TRIGB_CNTL 0x4596
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#define CAR_mmCRTC_TRIGB_MANUAL_TRIG 0x1b97
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#define CAR_mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1b97
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#define CAR_mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1d97
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#define CAR_mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x1f97
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#define CAR_mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4197
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#define CAR_mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4397
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#define CAR_mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4597
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#define CAR_mmCRTC_FORCE_COUNT_NOW_CNTL 0x1b98
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#define CAR_mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1b98
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#define CAR_mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1d98
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#define CAR_mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x1f98
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#define CAR_mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4198
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#define CAR_mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4398
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#define CAR_mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4598
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#define CAR_mmCRTC_FLOW_CONTROL 0x1b99
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#define CAR_mmCRTC0_CRTC_FLOW_CONTROL 0x1b99
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#define CAR_mmCRTC1_CRTC_FLOW_CONTROL 0x1d99
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#define CAR_mmCRTC2_CRTC_FLOW_CONTROL 0x1f99
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#define CAR_mmCRTC3_CRTC_FLOW_CONTROL 0x4199
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#define CAR_mmCRTC4_CRTC_FLOW_CONTROL 0x4399
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#define CAR_mmCRTC5_CRTC_FLOW_CONTROL 0x4599
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#define CAR_mmCRTC_STEREO_FORCE_NEXT_EYE 0x1b9a
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#define CAR_mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1b9a
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#define CAR_mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1d9a
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#define CAR_mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x1f9a
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#define CAR_mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x419a
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#define CAR_mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x439a
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#define CAR_mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x459a
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#define CAR_mmCRTC_AVSYNC_COUNTER 0x1b9b
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#define CAR_mmCRTC0_CRTC_AVSYNC_COUNTER 0x1b9b
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#define CAR_mmCRTC1_CRTC_AVSYNC_COUNTER 0x1d9b
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#define CAR_mmCRTC2_CRTC_AVSYNC_COUNTER 0x1f9b
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#define CAR_mmCRTC3_CRTC_AVSYNC_COUNTER 0x419b
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#define CAR_mmCRTC4_CRTC_AVSYNC_COUNTER 0x439b
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#define CAR_mmCRTC5_CRTC_AVSYNC_COUNTER 0x459b
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#define CAR_mmCRTC_CONTROL 0x1b9c
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#define CAR_mmCRTC0_CRTC_CONTROL 0x1b9c
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#define CAR_mmCRTC1_CRTC_CONTROL 0x1d9c
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#define CAR_mmCRTC2_CRTC_CONTROL 0x1f9c
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#define CAR_mmCRTC3_CRTC_CONTROL 0x419c
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#define CAR_mmCRTC4_CRTC_CONTROL 0x439c
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#define CAR_mmCRTC5_CRTC_CONTROL 0x459c
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#define CAR_mmCRTC_BLANK_CONTROL 0x1b9d
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#define CAR_mmCRTC0_CRTC_BLANK_CONTROL 0x1b9d
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#define CAR_mmCRTC1_CRTC_BLANK_CONTROL 0x1d9d
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#define CAR_mmCRTC2_CRTC_BLANK_CONTROL 0x1f9d
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#define CAR_mmCRTC3_CRTC_BLANK_CONTROL 0x419d
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#define CAR_mmCRTC4_CRTC_BLANK_CONTROL 0x439d
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#define CAR_mmCRTC5_CRTC_BLANK_CONTROL 0x459d
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#define CAR_mmCRTC_INTERLACE_CONTROL 0x1b9e
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#define CAR_mmCRTC0_CRTC_INTERLACE_CONTROL 0x1b9e
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#define CAR_mmCRTC1_CRTC_INTERLACE_CONTROL 0x1d9e
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#define CAR_mmCRTC2_CRTC_INTERLACE_CONTROL 0x1f9e
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#define CAR_mmCRTC3_CRTC_INTERLACE_CONTROL 0x419e
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#define CAR_mmCRTC4_CRTC_INTERLACE_CONTROL 0x439e
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#define CAR_mmCRTC5_CRTC_INTERLACE_CONTROL 0x459e
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#define CAR_mmCRTC_INTERLACE_STATUS 0x1b9f
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#define CAR_mmCRTC0_CRTC_INTERLACE_STATUS 0x1b9f
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#define CAR_mmCRTC1_CRTC_INTERLACE_STATUS 0x1d9f
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#define CAR_mmCRTC2_CRTC_INTERLACE_STATUS 0x1f9f
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#define CAR_mmCRTC3_CRTC_INTERLACE_STATUS 0x419f
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#define CAR_mmCRTC4_CRTC_INTERLACE_STATUS 0x439f
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#define CAR_mmCRTC5_CRTC_INTERLACE_STATUS 0x459f
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#define CAR_mmCRTC_FIELD_INDICATION_CONTROL 0x1ba0
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#define CAR_mmCRTC0_CRTC_FIELD_INDICATION_CONTROL 0x1ba0
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#define CAR_mmCRTC1_CRTC_FIELD_INDICATION_CONTROL 0x1da0
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#define CAR_mmCRTC2_CRTC_FIELD_INDICATION_CONTROL 0x1fa0
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#define CAR_mmCRTC3_CRTC_FIELD_INDICATION_CONTROL 0x41a0
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#define CAR_mmCRTC4_CRTC_FIELD_INDICATION_CONTROL 0x43a0
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#define CAR_mmCRTC5_CRTC_FIELD_INDICATION_CONTROL 0x45a0
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#define CAR_mmCRTC_PIXEL_DATA_READBACK0 0x1ba1
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#define CAR_mmCRTC0_CRTC_PIXEL_DATA_READBACK0 0x1ba1
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#define CAR_mmCRTC1_CRTC_PIXEL_DATA_READBACK0 0x1da1
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#define CAR_mmCRTC2_CRTC_PIXEL_DATA_READBACK0 0x1fa1
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#define CAR_mmCRTC3_CRTC_PIXEL_DATA_READBACK0 0x41a1
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#define CAR_mmCRTC4_CRTC_PIXEL_DATA_READBACK0 0x43a1
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#define CAR_mmCRTC5_CRTC_PIXEL_DATA_READBACK0 0x45a1
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#define CAR_mmCRTC_PIXEL_DATA_READBACK1 0x1ba2
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#define CAR_mmCRTC0_CRTC_PIXEL_DATA_READBACK1 0x1ba2
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#define CAR_mmCRTC1_CRTC_PIXEL_DATA_READBACK1 0x1da2
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#define CAR_mmCRTC2_CRTC_PIXEL_DATA_READBACK1 0x1fa2
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#define CAR_mmCRTC3_CRTC_PIXEL_DATA_READBACK1 0x41a2
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#define CAR_mmCRTC4_CRTC_PIXEL_DATA_READBACK1 0x43a2
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#define CAR_mmCRTC5_CRTC_PIXEL_DATA_READBACK1 0x45a2
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#define CAR_mmCRTC_STATUS 0x1ba3
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#define CAR_mmCRTC0_CRTC_STATUS 0x1ba3
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#define CAR_mmCRTC1_CRTC_STATUS 0x1da3
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#define CAR_mmCRTC2_CRTC_STATUS 0x1fa3
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#define CAR_mmCRTC3_CRTC_STATUS 0x41a3
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#define CAR_mmCRTC4_CRTC_STATUS 0x43a3
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#define CAR_mmCRTC5_CRTC_STATUS 0x45a3
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#define CAR_mmCRTC_STATUS_POSITION 0x1ba4
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#define CAR_mmCRTC0_CRTC_STATUS_POSITION 0x1ba4
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#define CAR_mmCRTC1_CRTC_STATUS_POSITION 0x1da4
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#define CAR_mmCRTC2_CRTC_STATUS_POSITION 0x1fa4
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#define CAR_mmCRTC3_CRTC_STATUS_POSITION 0x41a4
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#define CAR_mmCRTC4_CRTC_STATUS_POSITION 0x43a4
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#define CAR_mmCRTC5_CRTC_STATUS_POSITION 0x45a4
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#define CAR_mmCRTC_NOM_VERT_POSITION 0x1ba5
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#define CAR_mmCRTC0_CRTC_NOM_VERT_POSITION 0x1ba5
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#define CAR_mmCRTC1_CRTC_NOM_VERT_POSITION 0x1da5
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#define CAR_mmCRTC2_CRTC_NOM_VERT_POSITION 0x1fa5
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#define CAR_mmCRTC3_CRTC_NOM_VERT_POSITION 0x41a5
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#define CAR_mmCRTC4_CRTC_NOM_VERT_POSITION 0x43a5
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#define CAR_mmCRTC5_CRTC_NOM_VERT_POSITION 0x45a5
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#define CAR_mmCRTC_STATUS_FRAME_COUNT 0x1ba6
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#define CAR_mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1ba6
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#define CAR_mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1da6
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#define CAR_mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x1fa6
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#define CAR_mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x41a6
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#define CAR_mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x43a6
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#define CAR_mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x45a6
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#define CAR_mmCRTC_STATUS_VF_COUNT 0x1ba7
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#define CAR_mmCRTC0_CRTC_STATUS_VF_COUNT 0x1ba7
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#define CAR_mmCRTC1_CRTC_STATUS_VF_COUNT 0x1da7
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#define CAR_mmCRTC2_CRTC_STATUS_VF_COUNT 0x1fa7
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#define CAR_mmCRTC3_CRTC_STATUS_VF_COUNT 0x41a7
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#define CAR_mmCRTC4_CRTC_STATUS_VF_COUNT 0x43a7
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#define CAR_mmCRTC5_CRTC_STATUS_VF_COUNT 0x45a7
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#define CAR_mmCRTC_STATUS_HV_COUNT 0x1ba8
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#define CAR_mmCRTC0_CRTC_STATUS_HV_COUNT 0x1ba8
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#define CAR_mmCRTC1_CRTC_STATUS_HV_COUNT 0x1da8
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#define CAR_mmCRTC2_CRTC_STATUS_HV_COUNT 0x1fa8
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#define CAR_mmCRTC3_CRTC_STATUS_HV_COUNT 0x41a8
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#define CAR_mmCRTC4_CRTC_STATUS_HV_COUNT 0x43a8
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#define CAR_mmCRTC5_CRTC_STATUS_HV_COUNT 0x45a8
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#define CAR_mmCRTC_COUNT_CONTROL 0x1ba9
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#define CAR_mmCRTC0_CRTC_COUNT_CONTROL 0x1ba9
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#define CAR_mmCRTC1_CRTC_COUNT_CONTROL 0x1da9
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#define CAR_mmCRTC2_CRTC_COUNT_CONTROL 0x1fa9
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#define CAR_mmCRTC3_CRTC_COUNT_CONTROL 0x41a9
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#define CAR_mmCRTC4_CRTC_COUNT_CONTROL 0x43a9
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#define CAR_mmCRTC5_CRTC_COUNT_CONTROL 0x45a9
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#define CAR_mmCRTC_COUNT_RESET 0x1baa
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#define CAR_mmCRTC0_CRTC_COUNT_RESET 0x1baa
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#define CAR_mmCRTC1_CRTC_COUNT_RESET 0x1daa
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#define CAR_mmCRTC2_CRTC_COUNT_RESET 0x1faa
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#define CAR_mmCRTC3_CRTC_COUNT_RESET 0x41aa
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#define CAR_mmCRTC4_CRTC_COUNT_RESET 0x43aa
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#define CAR_mmCRTC5_CRTC_COUNT_RESET 0x45aa
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#define CAR_mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab
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#define CAR_mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bab
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#define CAR_mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dab
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#define CAR_mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1fab
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#define CAR_mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41ab
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#define CAR_mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x43ab
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#define CAR_mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x45ab
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#define CAR_mmCRTC_VERT_SYNC_CONTROL 0x1bac
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#define CAR_mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1bac
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#define CAR_mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1dac
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#define CAR_mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x1fac
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#define CAR_mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x41ac
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#define CAR_mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x43ac
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#define CAR_mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x45ac
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#define CAR_mmCRTC_STEREO_STATUS 0x1bad
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#define CAR_mmCRTC0_CRTC_STEREO_STATUS 0x1bad
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#define CAR_mmCRTC1_CRTC_STEREO_STATUS 0x1dad
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#define CAR_mmCRTC2_CRTC_STEREO_STATUS 0x1fad
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#define CAR_mmCRTC3_CRTC_STEREO_STATUS 0x41ad
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#define CAR_mmCRTC4_CRTC_STEREO_STATUS 0x43ad
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#define CAR_mmCRTC5_CRTC_STEREO_STATUS 0x45ad
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#define CAR_mmCRTC_STEREO_CONTROL 0x1bae
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#define CAR_mmCRTC0_CRTC_STEREO_CONTROL 0x1bae
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#define CAR_mmCRTC1_CRTC_STEREO_CONTROL 0x1dae
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#define CAR_mmCRTC2_CRTC_STEREO_CONTROL 0x1fae
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#define CAR_mmCRTC3_CRTC_STEREO_CONTROL 0x41ae
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#define CAR_mmCRTC4_CRTC_STEREO_CONTROL 0x43ae
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#define CAR_mmCRTC5_CRTC_STEREO_CONTROL 0x45ae
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#define CAR_mmCRTC_SNAPSHOT_STATUS 0x1baf
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#define CAR_mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1baf
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#define CAR_mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1daf
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#define CAR_mmCRTC2_CRTC_SNAPSHOT_STATUS 0x1faf
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#define CAR_mmCRTC3_CRTC_SNAPSHOT_STATUS 0x41af
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#define CAR_mmCRTC4_CRTC_SNAPSHOT_STATUS 0x43af
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#define CAR_mmCRTC5_CRTC_SNAPSHOT_STATUS 0x45af
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#define CAR_mmCRTC_SNAPSHOT_CONTROL 0x1bb0
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#define CAR_mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1bb0
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#define CAR_mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1db0
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#define CAR_mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x1fb0
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#define CAR_mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x41b0
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#define CAR_mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x43b0
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#define CAR_mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x45b0
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#define CAR_mmCRTC_SNAPSHOT_POSITION 0x1bb1
|
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#define CAR_mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1bb1
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#define CAR_mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1db1
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#define CAR_mmCRTC2_CRTC_SNAPSHOT_POSITION 0x1fb1
|
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#define CAR_mmCRTC3_CRTC_SNAPSHOT_POSITION 0x41b1
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#define CAR_mmCRTC4_CRTC_SNAPSHOT_POSITION 0x43b1
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#define CAR_mmCRTC5_CRTC_SNAPSHOT_POSITION 0x45b1
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#define CAR_mmCRTC_SNAPSHOT_FRAME 0x1bb2
|
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#define CAR_mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1bb2
|
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#define CAR_mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1db2
|
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#define CAR_mmCRTC2_CRTC_SNAPSHOT_FRAME 0x1fb2
|
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#define CAR_mmCRTC3_CRTC_SNAPSHOT_FRAME 0x41b2
|
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#define CAR_mmCRTC4_CRTC_SNAPSHOT_FRAME 0x43b2
|
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#define CAR_mmCRTC5_CRTC_SNAPSHOT_FRAME 0x45b2
|
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#define CAR_mmCRTC_START_LINE_CONTROL 0x1bb3
|
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#define CAR_mmCRTC0_CRTC_START_LINE_CONTROL 0x1bb3
|
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#define CAR_mmCRTC1_CRTC_START_LINE_CONTROL 0x1db3
|
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#define CAR_mmCRTC2_CRTC_START_LINE_CONTROL 0x1fb3
|
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#define CAR_mmCRTC3_CRTC_START_LINE_CONTROL 0x41b3
|
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#define CAR_mmCRTC4_CRTC_START_LINE_CONTROL 0x43b3
|
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#define CAR_mmCRTC5_CRTC_START_LINE_CONTROL 0x45b3
|
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#define CAR_mmCRTC_INTERRUPT_CONTROL 0x1bb4
|
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#define CAR_mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1bb4
|
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#define CAR_mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1db4
|
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#define CAR_mmCRTC2_CRTC_INTERRUPT_CONTROL 0x1fb4
|
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#define CAR_mmCRTC3_CRTC_INTERRUPT_CONTROL 0x41b4
|
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#define CAR_mmCRTC4_CRTC_INTERRUPT_CONTROL 0x43b4
|
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#define CAR_mmCRTC5_CRTC_INTERRUPT_CONTROL 0x45b4
|
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#define CAR_mmCRTC_UPDATE_LOCK 0x1bb5
|
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#define CAR_mmCRTC0_CRTC_UPDATE_LOCK 0x1bb5
|
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#define CAR_mmCRTC1_CRTC_UPDATE_LOCK 0x1db5
|
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#define CAR_mmCRTC2_CRTC_UPDATE_LOCK 0x1fb5
|
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#define CAR_mmCRTC3_CRTC_UPDATE_LOCK 0x41b5
|
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#define CAR_mmCRTC4_CRTC_UPDATE_LOCK 0x43b5
|
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#define CAR_mmCRTC5_CRTC_UPDATE_LOCK 0x45b5
|
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#define CAR_mmCRTC_DOUBLE_BUFFER_CONTROL 0x1bb6
|
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#define CAR_mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1bb6
|
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#define CAR_mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1db6
|
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#define CAR_mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x1fb6
|
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#define CAR_mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x41b6
|
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#define CAR_mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x43b6
|
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#define CAR_mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x45b6
|
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#define CAR_mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7
|
|
#define CAR_mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1bb7
|
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#define CAR_mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1db7
|
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#define CAR_mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1fb7
|
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#define CAR_mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41b7
|
|
#define CAR_mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x43b7
|
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#define CAR_mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x45b7
|
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#define CAR_mmCRTC_TEST_PATTERN_CONTROL 0x1bba
|
|
#define CAR_mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1bba
|
|
#define CAR_mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1dba
|
|
#define CAR_mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x1fba
|
|
#define CAR_mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x41ba
|
|
#define CAR_mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x43ba
|
|
#define CAR_mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x45ba
|
|
#define CAR_mmCRTC_TEST_PATTERN_PARAMETERS 0x1bbb
|
|
#define CAR_mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1bbb
|
|
#define CAR_mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1dbb
|
|
#define CAR_mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x1fbb
|
|
#define CAR_mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x41bb
|
|
#define CAR_mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x43bb
|
|
#define CAR_mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x45bb
|
|
#define CAR_mmCRTC_TEST_PATTERN_COLOR 0x1bbc
|
|
#define CAR_mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1bbc
|
|
#define CAR_mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1dbc
|
|
#define CAR_mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x1fbc
|
|
#define CAR_mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x41bc
|
|
#define CAR_mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x43bc
|
|
#define CAR_mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x45bc
|
|
#define CAR_mmCRTC_MASTER_UPDATE_LOCK 0x1bbd
|
|
#define CAR_mmCRTC0_CRTC_MASTER_UPDATE_LOCK 0x1bbd
|
|
#define CAR_mmCRTC1_CRTC_MASTER_UPDATE_LOCK 0x1dbd
|
|
#define CAR_mmCRTC2_CRTC_MASTER_UPDATE_LOCK 0x1fbd
|
|
#define CAR_mmCRTC3_CRTC_MASTER_UPDATE_LOCK 0x41bd
|
|
#define CAR_mmCRTC4_CRTC_MASTER_UPDATE_LOCK 0x43bd
|
|
#define CAR_mmCRTC5_CRTC_MASTER_UPDATE_LOCK 0x45bd
|
|
#define CAR_mmCRTC_MASTER_UPDATE_MODE 0x1bbe
|
|
#define CAR_mmCRTC0_CRTC_MASTER_UPDATE_MODE 0x1bbe
|
|
#define CAR_mmCRTC1_CRTC_MASTER_UPDATE_MODE 0x1dbe
|
|
#define CAR_mmCRTC2_CRTC_MASTER_UPDATE_MODE 0x1fbe
|
|
#define CAR_mmCRTC3_CRTC_MASTER_UPDATE_MODE 0x41be
|
|
#define CAR_mmCRTC4_CRTC_MASTER_UPDATE_MODE 0x43be
|
|
#define CAR_mmCRTC5_CRTC_MASTER_UPDATE_MODE 0x45be
|
|
#define CAR_mmCRTC_MVP_INBAND_CNTL_INSERT 0x1bbf
|
|
#define CAR_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1bbf
|
|
#define CAR_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1dbf
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#define CAR_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x1fbf
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#define CAR_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x41bf
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#define CAR_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x43bf
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#define CAR_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x45bf
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#define CAR_mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0
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#define CAR_mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1bc0
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#define CAR_mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1dc0
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#define CAR_mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1fc0
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#define CAR_mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41c0
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#define CAR_mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x43c0
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#define CAR_mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x45c0
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#define CAR_mmCRTC_MVP_STATUS 0x1bc1
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#define CAR_mmCRTC0_CRTC_MVP_STATUS 0x1bc1
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#define CAR_mmCRTC1_CRTC_MVP_STATUS 0x1dc1
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#define CAR_mmCRTC2_CRTC_MVP_STATUS 0x1fc1
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#define CAR_mmCRTC3_CRTC_MVP_STATUS 0x41c1
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#define CAR_mmCRTC4_CRTC_MVP_STATUS 0x43c1
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#define CAR_mmCRTC5_CRTC_MVP_STATUS 0x45c1
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#define CAR_mmCRTC_MASTER_EN 0x1bc2
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#define CAR_mmCRTC0_CRTC_MASTER_EN 0x1bc2
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#define CAR_mmCRTC1_CRTC_MASTER_EN 0x1dc2
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#define CAR_mmCRTC2_CRTC_MASTER_EN 0x1fc2
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#define CAR_mmCRTC3_CRTC_MASTER_EN 0x41c2
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#define CAR_mmCRTC4_CRTC_MASTER_EN 0x43c2
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#define CAR_mmCRTC5_CRTC_MASTER_EN 0x45c2
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#define CAR_mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3
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#define CAR_mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1bc3
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#define CAR_mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1dc3
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#define CAR_mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x1fc3
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#define CAR_mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x41c3
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#define CAR_mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x43c3
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#define CAR_mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x45c3
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#define CAR_mmCRTC_V_UPDATE_INT_STATUS 0x1bc4
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#define CAR_mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1bc4
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#define CAR_mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1dc4
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#define CAR_mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x1fc4
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#define CAR_mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x41c4
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#define CAR_mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x43c4
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#define CAR_mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x45c4
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#define CAR_mmCRTC_OVERSCAN_COLOR 0x1bc8
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#define CAR_mmCRTC0_CRTC_OVERSCAN_COLOR 0x1bc8
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#define CAR_mmCRTC1_CRTC_OVERSCAN_COLOR 0x1dc8
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#define CAR_mmCRTC2_CRTC_OVERSCAN_COLOR 0x1fc8
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#define CAR_mmCRTC3_CRTC_OVERSCAN_COLOR 0x41c8
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#define CAR_mmCRTC4_CRTC_OVERSCAN_COLOR 0x43c8
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#define CAR_mmCRTC5_CRTC_OVERSCAN_COLOR 0x45c8
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#define CAR_mmCRTC_OVERSCAN_COLOR_EXT 0x1bc9
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#define CAR_mmCRTC0_CRTC_OVERSCAN_COLOR_EXT 0x1bc9
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#define CAR_mmCRTC1_CRTC_OVERSCAN_COLOR_EXT 0x1dc9
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#define CAR_mmCRTC2_CRTC_OVERSCAN_COLOR_EXT 0x1fc9
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#define CAR_mmCRTC3_CRTC_OVERSCAN_COLOR_EXT 0x41c9
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#define CAR_mmCRTC4_CRTC_OVERSCAN_COLOR_EXT 0x43c9
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#define CAR_mmCRTC5_CRTC_OVERSCAN_COLOR_EXT 0x45c9
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#define CAR_mmCRTC_BLANK_DATA_COLOR 0x1bca
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#define CAR_mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1bca
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#define CAR_mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1dca
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#define CAR_mmCRTC2_CRTC_BLANK_DATA_COLOR 0x1fca
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#define CAR_mmCRTC3_CRTC_BLANK_DATA_COLOR 0x41ca
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#define CAR_mmCRTC4_CRTC_BLANK_DATA_COLOR 0x43ca
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#define CAR_mmCRTC5_CRTC_BLANK_DATA_COLOR 0x45ca
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#define CAR_mmCRTC_BLANK_DATA_COLOR_EXT 0x1bcb
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#define CAR_mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT 0x1bcb
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#define CAR_mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT 0x1dcb
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#define CAR_mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT 0x1fcb
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#define CAR_mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT 0x41cb
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#define CAR_mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT 0x43cb
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#define CAR_mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT 0x45cb
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#define CAR_mmCRTC_BLACK_COLOR 0x1bcc
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#define CAR_mmCRTC0_CRTC_BLACK_COLOR 0x1bcc
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#define CAR_mmCRTC1_CRTC_BLACK_COLOR 0x1dcc
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#define CAR_mmCRTC2_CRTC_BLACK_COLOR 0x1fcc
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#define CAR_mmCRTC3_CRTC_BLACK_COLOR 0x41cc
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#define CAR_mmCRTC4_CRTC_BLACK_COLOR 0x43cc
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#define CAR_mmCRTC5_CRTC_BLACK_COLOR 0x45cc
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#define CAR_mmCRTC_BLACK_COLOR_EXT 0x1bcd
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#define CAR_mmCRTC0_CRTC_BLACK_COLOR_EXT 0x1bcd
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#define CAR_mmCRTC1_CRTC_BLACK_COLOR_EXT 0x1dcd
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#define CAR_mmCRTC2_CRTC_BLACK_COLOR_EXT 0x1fcd
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#define CAR_mmCRTC3_CRTC_BLACK_COLOR_EXT 0x41cd
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#define CAR_mmCRTC4_CRTC_BLACK_COLOR_EXT 0x43cd
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#define CAR_mmCRTC5_CRTC_BLACK_COLOR_EXT 0x45cd
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#define CAR_mmCRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce
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#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1bce
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#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1dce
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#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION 0x1fce
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#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION 0x41ce
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#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION 0x43ce
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#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION 0x45ce
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#define CAR_mmCRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf
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#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1bcf
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#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1dcf
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#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x1fcf
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#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x41cf
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#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x43cf
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#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL 0x45cf
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#define CAR_mmCRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0
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#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1bd0
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#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1dd0
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#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION 0x1fd0
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#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION 0x41d0
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#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION 0x43d0
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#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION 0x45d0
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#define CAR_mmCRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1
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#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1bd1
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#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1dd1
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#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x1fd1
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#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x41d1
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#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x43d1
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#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL 0x45d1
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#define CAR_mmCRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2
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#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1bd2
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#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1dd2
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#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION 0x1fd2
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#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION 0x41d2
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#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION 0x43d2
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#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION 0x45d2
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#define CAR_mmCRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3
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#define CAR_mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1bd3
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#define CAR_mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1dd3
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#define CAR_mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x1fd3
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#define CAR_mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x41d3
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#define CAR_mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x43d3
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#define CAR_mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL 0x45d3
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#define CAR_mmCRTC_CRC_CNTL 0x1bd4
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#define CAR_mmCRTC0_CRTC_CRC_CNTL 0x1bd4
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#define CAR_mmCRTC1_CRTC_CRC_CNTL 0x1dd4
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#define CAR_mmCRTC2_CRTC_CRC_CNTL 0x1fd4
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#define CAR_mmCRTC3_CRTC_CRC_CNTL 0x41d4
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#define CAR_mmCRTC4_CRTC_CRC_CNTL 0x43d4
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#define CAR_mmCRTC5_CRTC_CRC_CNTL 0x45d4
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#define CAR_mmCRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5
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#define CAR_mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL 0x1bd5
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#define CAR_mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL 0x1dd5
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#define CAR_mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL 0x1fd5
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#define CAR_mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL 0x41d5
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#define CAR_mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL 0x43d5
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#define CAR_mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL 0x45d5
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#define CAR_mmCRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6
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#define CAR_mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1bd6
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#define CAR_mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1dd6
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#define CAR_mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL 0x1fd6
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#define CAR_mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL 0x41d6
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#define CAR_mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL 0x43d6
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#define CAR_mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL 0x45d6
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#define CAR_mmCRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7
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#define CAR_mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL 0x1bd7
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#define CAR_mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL 0x1dd7
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#define CAR_mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL 0x1fd7
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#define CAR_mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL 0x41d7
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#define CAR_mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL 0x43d7
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#define CAR_mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL 0x45d7
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#define CAR_mmCRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8
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#define CAR_mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1bd8
|
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#define CAR_mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1dd8
|
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#define CAR_mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL 0x1fd8
|
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#define CAR_mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL 0x41d8
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#define CAR_mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL 0x43d8
|
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#define CAR_mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL 0x45d8
|
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#define CAR_mmCRTC_CRC0_DATA_RG 0x1bd9
|
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#define CAR_mmCRTC0_CRTC_CRC0_DATA_RG 0x1bd9
|
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#define CAR_mmCRTC1_CRTC_CRC0_DATA_RG 0x1dd9
|
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#define CAR_mmCRTC2_CRTC_CRC0_DATA_RG 0x1fd9
|
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#define CAR_mmCRTC3_CRTC_CRC0_DATA_RG 0x41d9
|
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#define CAR_mmCRTC4_CRTC_CRC0_DATA_RG 0x43d9
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#define CAR_mmCRTC5_CRTC_CRC0_DATA_RG 0x45d9
|
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#define CAR_mmCRTC_CRC0_DATA_B 0x1bda
|
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#define CAR_mmCRTC0_CRTC_CRC0_DATA_B 0x1bda
|
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#define CAR_mmCRTC1_CRTC_CRC0_DATA_B 0x1dda
|
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#define CAR_mmCRTC2_CRTC_CRC0_DATA_B 0x1fda
|
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#define CAR_mmCRTC3_CRTC_CRC0_DATA_B 0x41da
|
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#define CAR_mmCRTC4_CRTC_CRC0_DATA_B 0x43da
|
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#define CAR_mmCRTC5_CRTC_CRC0_DATA_B 0x45da
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#define CAR_mmCRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb
|
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#define CAR_mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL 0x1bdb
|
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#define CAR_mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL 0x1ddb
|
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#define CAR_mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL 0x1fdb
|
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#define CAR_mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL 0x41db
|
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#define CAR_mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL 0x43db
|
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#define CAR_mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL 0x45db
|
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#define CAR_mmCRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc
|
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#define CAR_mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1bdc
|
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#define CAR_mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1ddc
|
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#define CAR_mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL 0x1fdc
|
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#define CAR_mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL 0x41dc
|
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#define CAR_mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL 0x43dc
|
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#define CAR_mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL 0x45dc
|
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#define CAR_mmCRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd
|
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#define CAR_mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL 0x1bdd
|
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#define CAR_mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL 0x1ddd
|
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#define CAR_mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL 0x1fdd
|
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#define CAR_mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL 0x41dd
|
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#define CAR_mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL 0x43dd
|
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#define CAR_mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL 0x45dd
|
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#define CAR_mmCRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde
|
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#define CAR_mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1bde
|
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#define CAR_mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1dde
|
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#define CAR_mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL 0x1fde
|
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#define CAR_mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL 0x41de
|
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#define CAR_mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL 0x43de
|
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#define CAR_mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL 0x45de
|
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#define CAR_mmCRTC_CRC1_DATA_RG 0x1bdf
|
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#define CAR_mmCRTC0_CRTC_CRC1_DATA_RG 0x1bdf
|
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#define CAR_mmCRTC1_CRTC_CRC1_DATA_RG 0x1ddf
|
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#define CAR_mmCRTC2_CRTC_CRC1_DATA_RG 0x1fdf
|
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#define CAR_mmCRTC3_CRTC_CRC1_DATA_RG 0x41df
|
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#define CAR_mmCRTC4_CRTC_CRC1_DATA_RG 0x43df
|
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#define CAR_mmCRTC5_CRTC_CRC1_DATA_RG 0x45df
|
|
#define CAR_mmCRTC_CRC1_DATA_B 0x1be0
|
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#define CAR_mmCRTC0_CRTC_CRC1_DATA_B 0x1be0
|
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#define CAR_mmCRTC1_CRTC_CRC1_DATA_B 0x1de0
|
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#define CAR_mmCRTC2_CRTC_CRC1_DATA_B 0x1fe0
|
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#define CAR_mmCRTC3_CRTC_CRC1_DATA_B 0x41e0
|
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#define CAR_mmCRTC4_CRTC_CRC1_DATA_B 0x43e0
|
|
#define CAR_mmCRTC5_CRTC_CRC1_DATA_B 0x45e0
|
|
#define CAR_mmCRTC_STATIC_SCREEN_CONTROL 0x1be7
|
|
#define CAR_mmCRTC0_CRTC_STATIC_SCREEN_CONTROL 0x1be7
|
|
#define CAR_mmCRTC1_CRTC_STATIC_SCREEN_CONTROL 0x1de7
|
|
#define CAR_mmCRTC2_CRTC_STATIC_SCREEN_CONTROL 0x1fe7
|
|
#define CAR_mmCRTC3_CRTC_STATIC_SCREEN_CONTROL 0x41e7
|
|
#define CAR_mmCRTC4_CRTC_STATIC_SCREEN_CONTROL 0x43e7
|
|
#define CAR_mmCRTC5_CRTC_STATIC_SCREEN_CONTROL 0x45e7
|
|
#define CAR_mmCRTC_3D_STRUCTURE_CONTROL 0x1b78
|
|
#define CAR_mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1b78
|
|
#define CAR_mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1d78
|
|
#define CAR_mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x1f78
|
|
#define CAR_mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4178
|
|
#define CAR_mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4378
|
|
#define CAR_mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4578
|
|
#define CAR_mmCRTC_GSL_VSYNC_GAP 0x1b79
|
|
#define CAR_mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1b79
|
|
#define CAR_mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1d79
|
|
#define CAR_mmCRTC2_CRTC_GSL_VSYNC_GAP 0x1f79
|
|
#define CAR_mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4179
|
|
#define CAR_mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4379
|
|
#define CAR_mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4579
|
|
#define CAR_mmCRTC_GSL_WINDOW 0x1b7a
|
|
#define CAR_mmCRTC0_CRTC_GSL_WINDOW 0x1b7a
|
|
#define CAR_mmCRTC1_CRTC_GSL_WINDOW 0x1d7a
|
|
#define CAR_mmCRTC2_CRTC_GSL_WINDOW 0x1f7a
|
|
#define CAR_mmCRTC3_CRTC_GSL_WINDOW 0x417a
|
|
#define CAR_mmCRTC4_CRTC_GSL_WINDOW 0x437a
|
|
#define CAR_mmCRTC5_CRTC_GSL_WINDOW 0x457a
|
|
#define CAR_mmCRTC_GSL_CONTROL 0x1b7b
|
|
#define CAR_mmCRTC0_CRTC_GSL_CONTROL 0x1b7b
|
|
#define CAR_mmCRTC1_CRTC_GSL_CONTROL 0x1d7b
|
|
#define CAR_mmCRTC2_CRTC_GSL_CONTROL 0x1f7b
|
|
#define CAR_mmCRTC3_CRTC_GSL_CONTROL 0x417b
|
|
#define CAR_mmCRTC4_CRTC_GSL_CONTROL 0x437b
|
|
#define CAR_mmCRTC5_CRTC_GSL_CONTROL 0x457b
|
|
#define CAR_mmCRTC_TEST_DEBUG_INDEX 0x1bc6
|
|
#define CAR_mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1bc6
|
|
#define CAR_mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1dc6
|
|
#define CAR_mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x1fc6
|
|
#define CAR_mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x41c6
|
|
#define CAR_mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x43c6
|
|
#define CAR_mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x45c6
|
|
#define CAR_mmCRTC_TEST_DEBUG_DATA 0x1bc7
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#define CAR_mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1bc7
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#define CAR_mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1dc7
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#define CAR_mmCRTC2_CRTC_TEST_DEBUG_DATA 0x1fc7
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#define CAR_mmCRTC3_CRTC_TEST_DEBUG_DATA 0x41c7
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#define CAR_mmCRTC4_CRTC_TEST_DEBUG_DATA 0x43c7
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#define CAR_mmCRTC5_CRTC_TEST_DEBUG_DATA 0x45c7
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#define CAR_mmDAC_ENABLE 0x16aa
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#define CAR_mmDAC_SOURCE_SELECT 0x16ab
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#define CAR_mmDAC_CRC_EN 0x16ac
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#define CAR_mmDAC_CRC_CONTROL 0x16ad
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#define CAR_mmDAC_CRC_SIG_RGB_MASK 0x16ae
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#define CAR_mmDAC_CRC_SIG_CONTROL_MASK 0x16af
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#define CAR_mmDAC_CRC_SIG_RGB 0x16b0
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#define CAR_mmDAC_CRC_SIG_CONTROL 0x16b1
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#define CAR_mmDAC_SYNC_TRISTATE_CONTROL 0x16b2
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#define CAR_mmDAC_STEREOSYNC_SELECT 0x16b3
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#define CAR_mmDAC_AUTODETECT_CONTROL 0x16b4
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#define CAR_mmDAC_AUTODETECT_CONTROL2 0x16b5
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#define CAR_mmDAC_AUTODETECT_CONTROL3 0x16b6
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#define CAR_mmDAC_AUTODETECT_STATUS 0x16b7
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#define CAR_mmDAC_AUTODETECT_INT_CONTROL 0x16b8
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#define CAR_mmDAC_FORCE_OUTPUT_CNTL 0x16b9
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#define CAR_mmDAC_FORCE_DATA 0x16ba
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#define CAR_mmDAC_POWERDOWN 0x16bb
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#define CAR_mmDAC_CONTROL 0x16bc
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#define CAR_mmDAC_COMPARATOR_ENABLE 0x16bd
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#define CAR_mmDAC_COMPARATOR_OUTPUT 0x16be
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#define CAR_mmDAC_PWR_CNTL 0x16bf
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#define CAR_mmDAC_DFT_CONFIG 0x16c0
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#define CAR_mmDAC_FIFO_STATUS 0x16c1
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#define CAR_mmDAC_TEST_DEBUG_INDEX 0x16c2
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#define CAR_mmDAC_TEST_DEBUG_DATA 0x16c3
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#define CAR_mmPERFCOUNTER_CNTL 0x170
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#define CAR_mmDC_PERFMON0_PERFCOUNTER_CNTL 0x170
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#define CAR_mmDC_PERFMON1_PERFCOUNTER_CNTL 0x364
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#define CAR_mmDC_PERFMON2_PERFCOUNTER_CNTL 0x18c8
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#define CAR_mmDC_PERFMON3_PERFCOUNTER_CNTL 0x1b24
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#define CAR_mmDC_PERFMON4_PERFCOUNTER_CNTL 0x1d24
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#define CAR_mmDC_PERFMON5_PERFCOUNTER_CNTL 0x1f24
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#define CAR_mmDC_PERFMON6_PERFCOUNTER_CNTL 0x4124
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#define CAR_mmDC_PERFMON7_PERFCOUNTER_CNTL 0x4324
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#define CAR_mmDC_PERFMON8_PERFCOUNTER_CNTL 0x4524
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#define CAR_mmDC_PERFMON9_PERFCOUNTER_CNTL 0x4724
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#define CAR_mmDC_PERFMON10_PERFCOUNTER_CNTL 0x59a0
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#define CAR_mmDC_PERFMON11_PERFCOUNTER_CNTL 0x5f68
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#define CAR_mmPERFCOUNTER_STATE 0x171
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#define CAR_mmDC_PERFMON0_PERFCOUNTER_STATE 0x171
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#define CAR_mmDC_PERFMON1_PERFCOUNTER_STATE 0x365
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#define CAR_mmDC_PERFMON2_PERFCOUNTER_STATE 0x18c9
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#define CAR_mmDC_PERFMON3_PERFCOUNTER_STATE 0x1b25
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#define CAR_mmDC_PERFMON4_PERFCOUNTER_STATE 0x1d25
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#define CAR_mmDC_PERFMON5_PERFCOUNTER_STATE 0x1f25
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#define CAR_mmDC_PERFMON6_PERFCOUNTER_STATE 0x4125
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#define CAR_mmDC_PERFMON7_PERFCOUNTER_STATE 0x4325
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#define CAR_mmDC_PERFMON8_PERFCOUNTER_STATE 0x4525
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#define CAR_mmDC_PERFMON9_PERFCOUNTER_STATE 0x4725
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#define CAR_mmDC_PERFMON10_PERFCOUNTER_STATE 0x59a1
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#define CAR_mmDC_PERFMON11_PERFCOUNTER_STATE 0x5f69
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#define CAR_mmPERFMON_CNTL 0x173
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#define CAR_mmDC_PERFMON0_PERFMON_CNTL 0x173
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#define CAR_mmDC_PERFMON1_PERFMON_CNTL 0x367
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#define CAR_mmDC_PERFMON2_PERFMON_CNTL 0x18cb
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#define CAR_mmDC_PERFMON3_PERFMON_CNTL 0x1b27
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#define CAR_mmDC_PERFMON4_PERFMON_CNTL 0x1d27
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#define CAR_mmDC_PERFMON5_PERFMON_CNTL 0x1f27
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#define CAR_mmDC_PERFMON6_PERFMON_CNTL 0x4127
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#define CAR_mmDC_PERFMON7_PERFMON_CNTL 0x4327
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#define CAR_mmDC_PERFMON8_PERFMON_CNTL 0x4527
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#define CAR_mmDC_PERFMON9_PERFMON_CNTL 0x4727
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#define CAR_mmDC_PERFMON10_PERFMON_CNTL 0x59a3
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#define CAR_mmDC_PERFMON11_PERFMON_CNTL 0x5f6b
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#define CAR_mmPERFMON_CNTL2 0x17a
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#define CAR_mmDC_PERFMON0_PERFMON_CNTL2 0x17a
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#define CAR_mmDC_PERFMON1_PERFMON_CNTL2 0x36e
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#define CAR_mmDC_PERFMON2_PERFMON_CNTL2 0x18d2
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#define CAR_mmDC_PERFMON3_PERFMON_CNTL2 0x1b2e
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#define CAR_mmDC_PERFMON4_PERFMON_CNTL2 0x1d2e
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#define CAR_mmDC_PERFMON5_PERFMON_CNTL2 0x1f2e
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#define CAR_mmDC_PERFMON6_PERFMON_CNTL2 0x412e
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#define CAR_mmDC_PERFMON7_PERFMON_CNTL2 0x432e
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#define CAR_mmDC_PERFMON8_PERFMON_CNTL2 0x452e
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#define CAR_mmDC_PERFMON9_PERFMON_CNTL2 0x472e
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#define CAR_mmDC_PERFMON10_PERFMON_CNTL2 0x59aa
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#define CAR_mmDC_PERFMON11_PERFMON_CNTL2 0x5f72
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#define CAR_mmPERFMON_CVALUE_INT_MISC 0x172
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#define CAR_mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x172
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#define CAR_mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x366
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#define CAR_mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x18ca
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#define CAR_mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x1b26
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#define CAR_mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x1d26
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#define CAR_mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x1f26
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#define CAR_mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x4126
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#define CAR_mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x4326
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#define CAR_mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x4526
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#define CAR_mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x4726
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#define CAR_mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x59a2
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#define CAR_mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x5f6a
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#define CAR_mmPERFMON_CVALUE_LOW 0x174
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#define CAR_mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x174
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#define CAR_mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x368
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#define CAR_mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x18cc
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#define CAR_mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x1b28
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#define CAR_mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x1d28
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#define CAR_mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x1f28
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#define CAR_mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x4128
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#define CAR_mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x4328
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#define CAR_mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x4528
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#define CAR_mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x4728
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#define CAR_mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x59a4
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#define CAR_mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x5f6c
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#define CAR_mmPERFMON_HI 0x175
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#define CAR_mmDC_PERFMON0_PERFMON_HI 0x175
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#define CAR_mmDC_PERFMON1_PERFMON_HI 0x369
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#define CAR_mmDC_PERFMON2_PERFMON_HI 0x18cd
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#define CAR_mmDC_PERFMON3_PERFMON_HI 0x1b29
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#define CAR_mmDC_PERFMON4_PERFMON_HI 0x1d29
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#define CAR_mmDC_PERFMON5_PERFMON_HI 0x1f29
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#define CAR_mmDC_PERFMON6_PERFMON_HI 0x4129
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#define CAR_mmDC_PERFMON7_PERFMON_HI 0x4329
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#define CAR_mmDC_PERFMON8_PERFMON_HI 0x4529
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#define CAR_mmDC_PERFMON9_PERFMON_HI 0x4729
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#define CAR_mmDC_PERFMON10_PERFMON_HI 0x59a5
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#define CAR_mmDC_PERFMON11_PERFMON_HI 0x5f6d
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#define CAR_mmPERFMON_LOW 0x176
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#define CAR_mmDC_PERFMON0_PERFMON_LOW 0x176
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#define CAR_mmDC_PERFMON1_PERFMON_LOW 0x36a
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#define CAR_mmDC_PERFMON2_PERFMON_LOW 0x18ce
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#define CAR_mmDC_PERFMON3_PERFMON_LOW 0x1b2a
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#define CAR_mmDC_PERFMON4_PERFMON_LOW 0x1d2a
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#define CAR_mmDC_PERFMON5_PERFMON_LOW 0x1f2a
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#define CAR_mmDC_PERFMON6_PERFMON_LOW 0x412a
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#define CAR_mmDC_PERFMON7_PERFMON_LOW 0x432a
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#define CAR_mmDC_PERFMON8_PERFMON_LOW 0x452a
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#define CAR_mmDC_PERFMON9_PERFMON_LOW 0x472a
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#define CAR_mmDC_PERFMON10_PERFMON_LOW 0x59a6
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#define CAR_mmDC_PERFMON11_PERFMON_LOW 0x5f6e
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#define CAR_mmPERFMON_TEST_DEBUG_INDEX 0x177
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#define CAR_mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX 0x177
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#define CAR_mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX 0x36b
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#define CAR_mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX 0x18cf
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#define CAR_mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX 0x1b2b
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#define CAR_mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX 0x1d2b
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#define CAR_mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX 0x1f2b
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#define CAR_mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX 0x412b
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#define CAR_mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX 0x432b
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#define CAR_mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX 0x452b
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#define CAR_mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX 0x472b
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#define CAR_mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX 0x59a7
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#define CAR_mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX 0x5f6f
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#define CAR_mmPERFMON_TEST_DEBUG_DATA 0x178
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#define CAR_mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA 0x178
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#define CAR_mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA 0x36c
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#define CAR_mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA 0x18d0
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#define CAR_mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA 0x1b2c
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#define CAR_mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA 0x1d2c
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#define CAR_mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA 0x1f2c
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#define CAR_mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA 0x412c
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#define CAR_mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA 0x432c
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#define CAR_mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA 0x452c
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#define CAR_mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA 0x472c
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#define CAR_mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA 0x59a8
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#define CAR_mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA 0x5f70
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#define CAR_mmREFCLK_CNTL 0x109
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#define CAR_mmDCCG_CBUS_WRCMD_DELAY 0x110
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#define CAR_mmDPREFCLK_CNTL 0x118
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#define CAR_mmDCE_VERSION 0x11e
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#define CAR_mmAVSYNC_COUNTER_WRITE 0x12a
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#define CAR_mmAVSYNC_COUNTER_CONTROL 0x12b
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#define CAR_mmAVSYNC_COUNTER_READ 0x12f
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#define CAR_mmDCCG_GTC_CNTL 0x120
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#define CAR_mmDCCG_GTC_DTO_INCR 0x121
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#define CAR_mmDCCG_GTC_DTO_MODULO 0x122
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#define CAR_mmDCCG_GTC_CURRENT 0x123
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#define CAR_mmDCCG_DS_DTO_INCR 0x113
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#define CAR_mmDCCG_DS_DTO_MODULO 0x114
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#define CAR_mmDCCG_DS_CNTL 0x115
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#define CAR_mmDCCG_DS_HW_CAL_INTERVAL 0x116
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#define CAR_mmDCCG_DS_DEBUG_CNTL 0x112
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#define CAR_mmDMCU_SMU_INTERRUPT_CNTL 0x12c
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#define CAR_mmSMU_CONTROL 0x12d
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#define CAR_mmSMU_INTERRUPT_CONTROL 0x12e
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#define CAR_mmDAC_CLK_ENABLE 0x128
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#define CAR_mmDVO_CLK_ENABLE 0x129
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#define CAR_mmDCCG_GATE_DISABLE_CNTL 0x134
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#define CAR_mmDCCG_GATE_DISABLE_CNTL2 0x13c
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#define CAR_mmDISPCLK_CGTT_BLK_CTRL_REG 0x135
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#define CAR_mmSCLK_CGTT_BLK_CTRL_REG 0x136
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#define CAR_mmDPREFCLK_CGTT_BLK_CTRL_REG 0x108
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#define CAR_mmREFCLK_CGTT_BLK_CTRL_REG 0x10b
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#define CAR_mmSYMCLK_CGTT_BLK_CTRL_REG 0x13d
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#define CAR_mmDCCG_CAC_STATUS 0x137
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#define CAR_mmPIXCLK1_RESYNC_CNTL 0x138
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#define CAR_mmPIXCLK2_RESYNC_CNTL 0x139
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#define CAR_mmPIXCLK0_RESYNC_CNTL 0x13a
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#define CAR_mmPHYPLL_PIXCLK_CNTL 0x13e
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#define CAR_mmMICROSECOND_TIME_BASE_DIV 0x13b
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#define CAR_mmDCCG_DISP_CNTL_REG 0x13f
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#define CAR_mmMILLISECOND_TIME_BASE_DIV 0x130
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#define CAR_mmDISPCLK_FREQ_CHANGE_CNTL 0x131
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#define CAR_mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x132
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#define CAR_mmDCCG_PERFMON_CNTL 0x133
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#define CAR_mmDCCG_PERFMON_CNTL2 0x10e
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#define CAR_mmCRTC0_PIXEL_RATE_CNTL 0x140
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#define CAR_mmDP_DTO0_PHASE 0x141
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#define CAR_mmDP_DTO0_MODULO 0x142
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#define CAR_mmCRTC1_PIXEL_RATE_CNTL 0x144
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#define CAR_mmDP_DTO1_PHASE 0x145
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#define CAR_mmDP_DTO1_MODULO 0x146
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#define CAR_mmCRTC2_PIXEL_RATE_CNTL 0x148
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#define CAR_mmDP_DTO2_PHASE 0x149
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#define CAR_mmDP_DTO2_MODULO 0x14a
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#define CAR_mmCRTC3_PIXEL_RATE_CNTL 0x14c
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#define CAR_mmDP_DTO3_PHASE 0x14d
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#define CAR_mmDP_DTO3_MODULO 0x14e
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#define CAR_mmCRTC4_PIXEL_RATE_CNTL 0x150
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#define CAR_mmDP_DTO4_PHASE 0x151
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#define CAR_mmDP_DTO4_MODULO 0x152
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#define CAR_mmCRTC5_PIXEL_RATE_CNTL 0x154
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#define CAR_mmDP_DTO5_PHASE 0x155
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#define CAR_mmDP_DTO5_MODULO 0x156
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#define CAR_mmDCFEV0_CRTC_PIXEL_RATE_CNTL 0x104
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#define CAR_mmDCCG_SOFT_RESET 0x15f
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#define CAR_mmSYMCLKA_CLOCK_ENABLE 0x160
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#define CAR_mmSYMCLKB_CLOCK_ENABLE 0x161
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#define CAR_mmSYMCLKC_CLOCK_ENABLE 0x162
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#define CAR_mmSYMCLKD_CLOCK_ENABLE 0x163
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#define CAR_mmSYMCLKE_CLOCK_ENABLE 0x164
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#define CAR_mmSYMCLKF_CLOCK_ENABLE 0x165
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#define CAR_mmSYMCLKG_CLOCK_ENABLE 0x117
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#define CAR_mmDPDBG_CLK_FORCE_CONTROL 0x10d
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#define CAR_mmDCCG_AUDIO_DTO_SOURCE 0x16b
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#define CAR_mmDCCG_AUDIO_DTO0_PHASE 0x16c
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#define CAR_mmDCCG_AUDIO_DTO0_MODULE 0x16d
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#define CAR_mmDCCG_AUDIO_DTO1_PHASE 0x16e
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#define CAR_mmDCCG_AUDIO_DTO1_MODULE 0x16f
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#define CAR_mmDCCG_TEST_DEBUG_INDEX 0x17c
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#define CAR_mmDCCG_TEST_DEBUG_DATA 0x17d
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#define CAR_mmDCCG_TEST_CLK_SEL 0x17e
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#define CAR_mmCPLL_MACRO_CNTL_RESERVED0 0x5fd0
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#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0 0x5fd0
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#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0 0x5fdc
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#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0 0x5fe8
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#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0 0x5ff4
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#define CAR_mmCPLL_MACRO_CNTL_RESERVED1 0x5fd1
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#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1 0x5fd1
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#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1 0x5fdd
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#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1 0x5fe9
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#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1 0x5ff5
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#define CAR_mmCPLL_MACRO_CNTL_RESERVED2 0x5fd2
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#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2 0x5fd2
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#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2 0x5fde
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#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2 0x5fea
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#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2 0x5ff6
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#define CAR_mmCPLL_MACRO_CNTL_RESERVED3 0x5fd3
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#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3 0x5fd3
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#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3 0x5fdf
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#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3 0x5feb
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#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3 0x5ff7
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#define CAR_mmCPLL_MACRO_CNTL_RESERVED4 0x5fd4
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#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4 0x5fd4
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#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4 0x5fe0
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#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4 0x5fec
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#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4 0x5ff8
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#define CAR_mmCPLL_MACRO_CNTL_RESERVED5 0x5fd5
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#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5 0x5fd5
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#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5 0x5fe1
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#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5 0x5fed
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#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5 0x5ff9
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#define CAR_mmCPLL_MACRO_CNTL_RESERVED6 0x5fd6
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#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6 0x5fd6
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#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6 0x5fe2
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#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6 0x5fee
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#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6 0x5ffa
|
|
#define CAR_mmCPLL_MACRO_CNTL_RESERVED7 0x5fd7
|
|
#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7 0x5fd7
|
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#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7 0x5fe3
|
|
#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7 0x5fef
|
|
#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7 0x5ffb
|
|
#define CAR_mmCPLL_MACRO_CNTL_RESERVED8 0x5fd8
|
|
#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8 0x5fd8
|
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#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8 0x5fe4
|
|
#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8 0x5ff0
|
|
#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8 0x5ffc
|
|
#define CAR_mmCPLL_MACRO_CNTL_RESERVED9 0x5fd9
|
|
#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9 0x5fd9
|
|
#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9 0x5fe5
|
|
#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9 0x5ff1
|
|
#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9 0x5ffd
|
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#define CAR_mmCPLL_MACRO_CNTL_RESERVED10 0x5fda
|
|
#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10 0x5fda
|
|
#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10 0x5fe6
|
|
#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10 0x5ff2
|
|
#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10 0x5ffe
|
|
#define CAR_mmCPLL_MACRO_CNTL_RESERVED11 0x5fdb
|
|
#define CAR_mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11 0x5fdb
|
|
#define CAR_mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11 0x5fe7
|
|
#define CAR_mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11 0x5ff3
|
|
#define CAR_mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11 0x5fff
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED0 0x1700
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0 0x1700
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0 0x172a
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0 0x1754
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED1 0x1701
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1 0x1701
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1 0x172b
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1 0x1755
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED2 0x1702
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2 0x1702
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2 0x172c
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2 0x1756
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED3 0x1703
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3 0x1703
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3 0x172d
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3 0x1757
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED4 0x1704
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4 0x1704
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4 0x172e
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4 0x1758
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED5 0x1705
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5 0x1705
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5 0x172f
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5 0x1759
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED6 0x1706
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6 0x1706
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6 0x1730
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6 0x175a
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED7 0x1707
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7 0x1707
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7 0x1731
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7 0x175b
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED8 0x1708
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8 0x1708
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8 0x1732
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8 0x175c
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED9 0x1709
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9 0x1709
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9 0x1733
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9 0x175d
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED10 0x170a
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10 0x170a
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10 0x1734
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10 0x175e
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED11 0x170b
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11 0x170b
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11 0x1735
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11 0x175f
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED12 0x170c
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12 0x170c
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12 0x1736
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12 0x1760
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED13 0x170d
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13 0x170d
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13 0x1737
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13 0x1761
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED14 0x170e
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14 0x170e
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14 0x1738
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14 0x1762
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED15 0x170f
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15 0x170f
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15 0x1739
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15 0x1763
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED16 0x1710
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16 0x1710
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16 0x173a
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16 0x1764
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED17 0x1711
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17 0x1711
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17 0x173b
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17 0x1765
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED18 0x1712
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18 0x1712
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18 0x173c
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18 0x1766
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED19 0x1713
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19 0x1713
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19 0x173d
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19 0x1767
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED20 0x1714
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20 0x1714
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20 0x173e
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20 0x1768
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED21 0x1715
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21 0x1715
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21 0x173f
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21 0x1769
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED22 0x1716
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22 0x1716
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22 0x1740
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22 0x176a
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED23 0x1717
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23 0x1717
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23 0x1741
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23 0x176b
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED24 0x1718
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24 0x1718
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24 0x1742
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24 0x176c
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED25 0x1719
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25 0x1719
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25 0x1743
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25 0x176d
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED26 0x171a
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26 0x171a
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26 0x1744
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26 0x176e
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED27 0x171b
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27 0x171b
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27 0x1745
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27 0x176f
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED28 0x171c
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28 0x171c
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28 0x1746
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28 0x1770
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED29 0x171d
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29 0x171d
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29 0x1747
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29 0x1771
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED30 0x171e
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30 0x171e
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30 0x1748
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30 0x1772
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED31 0x171f
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31 0x171f
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31 0x1749
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31 0x1773
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED32 0x1720
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32 0x1720
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32 0x174a
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32 0x1774
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED33 0x1721
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33 0x1721
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33 0x174b
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33 0x1775
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED34 0x1722
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34 0x1722
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34 0x174c
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34 0x1776
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED35 0x1723
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35 0x1723
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35 0x174d
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35 0x1777
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED36 0x1724
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36 0x1724
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36 0x174e
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36 0x1778
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED37 0x1725
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37 0x1725
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37 0x174f
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37 0x1779
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED38 0x1726
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38 0x1726
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38 0x1750
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38 0x177a
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED39 0x1727
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39 0x1727
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39 0x1751
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39 0x177b
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED40 0x1728
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40 0x1728
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40 0x1752
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40 0x177c
|
|
#define CAR_mmPLL_MACRO_CNTL_RESERVED41 0x1729
|
|
#define CAR_mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41 0x1729
|
|
#define CAR_mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41 0x1753
|
|
#define CAR_mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41 0x177d
|
|
#define CAR_mmDENTIST_DISPCLK_CNTL 0x124
|
|
#define CAR_mmDCDEBUG_BUS_CLK1_SEL 0x16c4
|
|
#define CAR_mmDCDEBUG_BUS_CLK2_SEL 0x16c5
|
|
#define CAR_mmDCDEBUG_BUS_CLK3_SEL 0x16c6
|
|
#define CAR_mmDCDEBUG_BUS_CLK4_SEL 0x16c7
|
|
#define CAR_mmDCDEBUG_BUS_CLK5_SEL 0x16c8
|
|
#define CAR_mmDCDEBUG_OUT_PIN_OVERRIDE 0x16c9
|
|
#define CAR_mmDCDEBUG_OUT_CNTL 0x16ca
|
|
#define CAR_mmDCDEBUG_OUT_DATA 0x16cb
|
|
#define CAR_mmDMIF_ADDR_CONFIG 0x2f5
|
|
#define CAR_mmDMIF_CONTROL 0x2f6
|
|
#define CAR_mmDMIF_STATUS 0x2f7
|
|
#define CAR_mmDMIF_HW_DEBUG 0x2f8
|
|
#define CAR_mmDMIF_ARBITRATION_CONTROL 0x2f9
|
|
#define CAR_mmPIPE0_ARBITRATION_CONTROL3 0x2fa
|
|
#define CAR_mmPIPE1_ARBITRATION_CONTROL3 0x2fb
|
|
#define CAR_mmPIPE2_ARBITRATION_CONTROL3 0x2fc
|
|
#define CAR_mmPIPE3_ARBITRATION_CONTROL3 0x2fd
|
|
#define CAR_mmPIPE4_ARBITRATION_CONTROL3 0x2fe
|
|
#define CAR_mmPIPE5_ARBITRATION_CONTROL3 0x2ff
|
|
#define CAR_mmPIPE6_ARBITRATION_CONTROL3 0x32a
|
|
#define CAR_mmPIPE7_ARBITRATION_CONTROL3 0x32b
|
|
#define CAR_mmDMIF_P_VMID 0x300
|
|
#define CAR_mmDMIF_URG_OVERRIDE 0x329
|
|
#define CAR_mmDMIF_TEST_DEBUG_INDEX 0x301
|
|
#define CAR_mmDMIF_TEST_DEBUG_DATA 0x302
|
|
#define CAR_ixDMIF_DEBUG02_CORE0 0x2
|
|
#define CAR_ixDMIF_DEBUG02_CORE1 0xa
|
|
#define CAR_mmDMIF_ADDR_CALC 0x303
|
|
#define CAR_mmDMIF_STATUS2 0x304
|
|
#define CAR_mmPIPE0_MAX_REQUESTS 0x305
|
|
#define CAR_mmPIPE1_MAX_REQUESTS 0x306
|
|
#define CAR_mmPIPE2_MAX_REQUESTS 0x307
|
|
#define CAR_mmPIPE3_MAX_REQUESTS 0x308
|
|
#define CAR_mmPIPE4_MAX_REQUESTS 0x309
|
|
#define CAR_mmPIPE5_MAX_REQUESTS 0x30a
|
|
#define CAR_mmPIPE6_MAX_REQUESTS 0x32c
|
|
#define CAR_mmPIPE7_MAX_REQUESTS 0x32d
|
|
#define CAR_mmDVMM_REG_RD_STATUS 0x32e
|
|
#define CAR_mmDVMM_REG_RD_DATA 0x32f
|
|
#define CAR_mmDVMM_PTE_REQ 0x330
|
|
#define CAR_mmDVMM_CNTL 0x331
|
|
#define CAR_mmDVMM_FAULT_STATUS 0x332
|
|
#define CAR_mmDVMM_FAULT_ADDR 0x333
|
|
#define CAR_mmLOW_POWER_TILING_CONTROL 0x30b
|
|
#define CAR_mmMCIF_CONTROL 0x30c
|
|
#define CAR_mmMCIF_WRITE_COMBINE_CONTROL 0x30d
|
|
#define CAR_mmMCIF_TEST_DEBUG_INDEX 0x30e
|
|
#define CAR_mmMCIF_TEST_DEBUG_DATA 0x30f
|
|
#define CAR_ixIDDCCIF02_DBG_DCCIF_C 0x9
|
|
#define CAR_ixIDDCCIF04_DBG_DCCIF_E 0xb
|
|
#define CAR_ixIDDCCIF05_DBG_DCCIF_F 0xc
|
|
#define CAR_mmMCIF_VMID 0x310
|
|
#define CAR_mmMCIF_MEM_CONTROL 0x311
|
|
#define CAR_mmCC_DC_PIPE_DIS 0x312
|
|
#define CAR_mmMC_DC_INTERFACE_NACK_STATUS 0x313
|
|
#define CAR_mmRBBMIF_TIMEOUT 0x314
|
|
#define CAR_mmRBBMIF_STATUS 0x315
|
|
#define CAR_mmRBBMIF_TIMEOUT_DIS 0x316
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#define CAR_mmRBBMIF_STATUS_FLAG 0x327
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#define CAR_mmDCI_MEM_PWR_STATUS 0x317
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#define CAR_mmDCI_MEM_PWR_STATUS2 0x318
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#define CAR_mmDCI_CLK_CNTL 0x319
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#define CAR_mmDCI_CLK_RAMP_CNTL 0x31a
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#define CAR_mmDCI_MEM_PWR_CNTL 0x31b
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|
#define CAR_mmDCI_MEM_PWR_CNTL2 0x31c
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#define CAR_mmDCI_MEM_PWR_CNTL3 0x31d
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|
#define CAR_mmDVMM_PTE_PGMEM_CONTROL 0x335
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|
#define CAR_mmDVMM_PTE_PGMEM_STATE 0x336
|
|
#define CAR_mmDCI_SOFT_RESET 0x328
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#define CAR_mmDCI_MISC 0x334
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|
#define CAR_mmDCI_TEST_DEBUG_INDEX 0x31e
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|
#define CAR_mmDCI_TEST_DEBUG_DATA 0x31f
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|
#define CAR_mmDCI_DEBUG_CONFIG 0x320
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#define CAR_mmPIPE0_DMIF_BUFFER_CONTROL 0x321
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|
#define CAR_mmPIPE1_DMIF_BUFFER_CONTROL 0x322
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|
#define CAR_mmPIPE2_DMIF_BUFFER_CONTROL 0x323
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|
#define CAR_mmPIPE3_DMIF_BUFFER_CONTROL 0x324
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#define CAR_mmPIPE4_DMIF_BUFFER_CONTROL 0x325
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|
#define CAR_mmPIPE5_DMIF_BUFFER_CONTROL 0x326
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#define CAR_mmDC_GENERICA 0x4800
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#define CAR_mmDC_GENERICB 0x4801
|
|
#define CAR_mmDC_PAD_EXTERN_SIG 0x4802
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#define CAR_mmDC_REF_CLK_CNTL 0x4803
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#define CAR_mmDC_GPIO_DEBUG 0x4804
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|
#define CAR_mmUNIPHYA_LINK_CNTL 0x4805
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#define CAR_mmUNIPHYB_LINK_CNTL 0x4807
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|
#define CAR_mmUNIPHYC_LINK_CNTL 0x4809
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#define CAR_mmUNIPHYD_LINK_CNTL 0x480b
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#define CAR_mmUNIPHYE_LINK_CNTL 0x480d
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#define CAR_mmUNIPHYF_LINK_CNTL 0x480f
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#define CAR_mmUNIPHYG_LINK_CNTL 0x4811
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#define CAR_mmUNIPHYA_CHANNEL_XBAR_CNTL 0x4806
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#define CAR_mmUNIPHYB_CHANNEL_XBAR_CNTL 0x4808
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#define CAR_mmUNIPHYC_CHANNEL_XBAR_CNTL 0x480a
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#define CAR_mmUNIPHYD_CHANNEL_XBAR_CNTL 0x480c
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|
#define CAR_mmUNIPHYE_CHANNEL_XBAR_CNTL 0x480e
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|
#define CAR_mmUNIPHYF_CHANNEL_XBAR_CNTL 0x4810
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|
#define CAR_mmUNIPHYG_CHANNEL_XBAR_CNTL 0x4812
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|
#define CAR_mmUNIPHYLPA_LINK_CNTL 0x4847
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|
#define CAR_mmUNIPHYLPB_LINK_CNTL 0x4848
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#define CAR_mmUNIPHYLPA_CHANNEL_XBAR_CNTL 0x4849
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#define CAR_mmUNIPHYLPB_CHANNEL_XBAR_CNTL 0x484a
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|
#define CAR_mmUNIPHY_IMPCAL_LINKA 0x4838
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|
#define CAR_mmUNIPHY_IMPCAL_LINKB 0x4839
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|
#define CAR_mmUNIPHY_IMPCAL_LINKC 0x483f
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|
#define CAR_mmUNIPHY_IMPCAL_LINKD 0x4840
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|
#define CAR_mmUNIPHY_IMPCAL_LINKE 0x4843
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|
#define CAR_mmUNIPHY_IMPCAL_LINKF 0x4844
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|
#define CAR_mmUNIPHY_IMPCAL_PERIOD 0x483a
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|
#define CAR_mmAUXP_IMPCAL 0x483b
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|
#define CAR_mmAUXN_IMPCAL 0x483c
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|
#define CAR_mmDCIO_IMPCAL_CNTL 0x483d
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|
#define CAR_mmUNIPHY_IMPCAL_PSW_AB 0x483e
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|
#define CAR_mmDCIO_IMPCAL_CNTL_CD 0x4841
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|
#define CAR_mmUNIPHY_IMPCAL_PSW_CD 0x4842
|
|
#define CAR_mmDCIO_IMPCAL_CNTL_EF 0x4845
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|
#define CAR_mmUNIPHY_IMPCAL_PSW_EF 0x4846
|
|
#define CAR_mmDCIO_WRCMD_DELAY 0x4816
|
|
#define CAR_mmDC_PINSTRAPS 0x4818
|
|
#define CAR_mmDC_DVODATA_CONFIG 0x481a
|
|
#define CAR_mmLVTMA_PWRSEQ_CNTL 0x481b
|
|
#define CAR_mmLVTMA_PWRSEQ_STATE 0x481c
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|
#define CAR_mmLVTMA_PWRSEQ_REF_DIV 0x481d
|
|
#define CAR_mmLVTMA_PWRSEQ_DELAY1 0x481e
|
|
#define CAR_mmLVTMA_PWRSEQ_DELAY2 0x481f
|
|
#define CAR_mmBL_PWM_CNTL 0x4820
|
|
#define CAR_mmBL_PWM_CNTL2 0x4821
|
|
#define CAR_mmBL_PWM_PERIOD_CNTL 0x4822
|
|
#define CAR_mmBL_PWM_GRP1_REG_LOCK 0x4823
|
|
#define CAR_mmDCIO_GSL_GENLK_PAD_CNTL 0x4824
|
|
#define CAR_mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x4825
|
|
#define CAR_mmDCIO_GSL0_CNTL 0x4826
|
|
#define CAR_mmDCIO_GSL1_CNTL 0x4827
|
|
#define CAR_mmDCIO_GSL2_CNTL 0x4828
|
|
#define CAR_mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x4829
|
|
#define CAR_mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x482a
|
|
#define CAR_mmDC_GPU_TIMER_READ 0x482b
|
|
#define CAR_mmDC_GPU_TIMER_READ_CNTL 0x482c
|
|
#define CAR_mmDCIO_CLOCK_CNTL 0x482d
|
|
#define CAR_mmDCIO_DEBUG 0x482f
|
|
#define CAR_mmDCO_DCFE_EXT_VSYNC_CNTL 0x4830
|
|
#define CAR_mmDBG_OUT_CNTL 0x4834
|
|
#define CAR_mmDCIO_DEBUG_CONFIG 0x4835
|
|
#define CAR_mmDCIO_SOFT_RESET 0x4836
|
|
#define CAR_mmDCIO_DPHY_SEL 0x4837
|
|
#define CAR_mmDCIO_TEST_DEBUG_INDEX 0x4831
|
|
#define CAR_mmDCIO_TEST_DEBUG_DATA 0x4832
|
|
#define CAR_ixDCIO_DEBUG1 0x1
|
|
#define CAR_ixDCIO_DEBUG2 0x2
|
|
#define CAR_ixDCIO_DEBUG3 0x3
|
|
#define CAR_ixDCIO_DEBUG4 0x4
|
|
#define CAR_ixDCIO_DEBUG5 0x5
|
|
#define CAR_ixDCIO_DEBUG6 0x6
|
|
#define CAR_ixDCIO_DEBUG7 0x7
|
|
#define CAR_ixDCIO_DEBUG8 0x8
|
|
#define CAR_ixDCIO_DEBUG9 0x9
|
|
#define CAR_ixDCIO_DEBUGA 0xa
|
|
#define CAR_ixDCIO_DEBUGB 0xb
|
|
#define CAR_ixDCIO_DEBUGC 0xc
|
|
#define CAR_ixDCIO_DEBUGD 0xd
|
|
#define CAR_ixDCIO_DEBUGE 0xe
|
|
#define CAR_ixDCIO_DEBUGF 0xf
|
|
#define CAR_ixDCIO_DEBUG10 0x10
|
|
#define CAR_ixDCIO_DEBUG11 0x11
|
|
#define CAR_ixDCIO_DEBUG12 0x12
|
|
#define CAR_ixDCIO_DEBUG13 0x13
|
|
#define CAR_ixDCIO_DEBUG14 0x14
|
|
#define CAR_ixDCIO_DEBUG15 0x15
|
|
#define CAR_ixDCIO_DEBUG16 0x16
|
|
#define CAR_ixDCIO_DEBUG17 0x17
|
|
#define CAR_ixDCIO_DEBUG18 0x18
|
|
#define CAR_ixDCIO_DEBUG19 0x19
|
|
#define CAR_ixDCIO_DEBUG1A 0x1a
|
|
#define CAR_ixDCIO_DEBUG1B 0x1b
|
|
#define CAR_ixDCIO_DEBUG_ID 0x0
|
|
#define CAR_mmDC_GPIO_GENERIC_MASK 0x4860
|
|
#define CAR_mmDC_GPIO_GENERIC_A 0x4861
|
|
#define CAR_mmDC_GPIO_GENERIC_EN 0x4862
|
|
#define CAR_mmDC_GPIO_GENERIC_Y 0x4863
|
|
#define CAR_mmDC_GPIO_DVODATA_MASK 0x4864
|
|
#define CAR_mmDC_GPIO_DVODATA_A 0x4865
|
|
#define CAR_mmDC_GPIO_DVODATA_EN 0x4866
|
|
#define CAR_mmDC_GPIO_DVODATA_Y 0x4867
|
|
#define CAR_mmDC_GPIO_DDC1_MASK 0x4868
|
|
#define CAR_mmDC_GPIO_DDC1_A 0x4869
|
|
#define CAR_mmDC_GPIO_DDC1_EN 0x486a
|
|
#define CAR_mmDC_GPIO_DDC1_Y 0x486b
|
|
#define CAR_mmDC_GPIO_DDC2_MASK 0x486c
|
|
#define CAR_mmDC_GPIO_DDC2_A 0x486d
|
|
#define CAR_mmDC_GPIO_DDC2_EN 0x486e
|
|
#define CAR_mmDC_GPIO_DDC2_Y 0x486f
|
|
#define CAR_mmDC_GPIO_DDC3_MASK 0x4870
|
|
#define CAR_mmDC_GPIO_DDC3_A 0x4871
|
|
#define CAR_mmDC_GPIO_DDC3_EN 0x4872
|
|
#define CAR_mmDC_GPIO_DDC3_Y 0x4873
|
|
#define CAR_mmDC_GPIO_DDC4_MASK 0x4874
|
|
#define CAR_mmDC_GPIO_DDC4_A 0x4875
|
|
#define CAR_mmDC_GPIO_DDC4_EN 0x4876
|
|
#define CAR_mmDC_GPIO_DDC4_Y 0x4877
|
|
#define CAR_mmDC_GPIO_DDC5_MASK 0x4878
|
|
#define CAR_mmDC_GPIO_DDC5_A 0x4879
|
|
#define CAR_mmDC_GPIO_DDC5_EN 0x487a
|
|
#define CAR_mmDC_GPIO_DDC5_Y 0x487b
|
|
#define CAR_mmDC_GPIO_DDC6_MASK 0x487c
|
|
#define CAR_mmDC_GPIO_DDC6_A 0x487d
|
|
#define CAR_mmDC_GPIO_DDC6_EN 0x487e
|
|
#define CAR_mmDC_GPIO_DDC6_Y 0x487f
|
|
#define CAR_mmDC_GPIO_DDCVGA_MASK 0x4880
|
|
#define CAR_mmDC_GPIO_DDCVGA_A 0x4881
|
|
#define CAR_mmDC_GPIO_DDCVGA_EN 0x4882
|
|
#define CAR_mmDC_GPIO_DDCVGA_Y 0x4883
|
|
#define CAR_mmDC_GPIO_SYNCA_MASK 0x4884
|
|
#define CAR_mmDC_GPIO_SYNCA_A 0x4885
|
|
#define CAR_mmDC_GPIO_SYNCA_EN 0x4886
|
|
#define CAR_mmDC_GPIO_SYNCA_Y 0x4887
|
|
#define CAR_mmDC_GPIO_GENLK_MASK 0x4888
|
|
#define CAR_mmDC_GPIO_GENLK_A 0x4889
|
|
#define CAR_mmDC_GPIO_GENLK_EN 0x488a
|
|
#define CAR_mmDC_GPIO_GENLK_Y 0x488b
|
|
#define CAR_mmDC_GPIO_HPD_MASK 0x488c
|
|
#define CAR_mmDC_GPIO_HPD_A 0x488d
|
|
#define CAR_mmDC_GPIO_HPD_EN 0x488e
|
|
#define CAR_mmDC_GPIO_HPD_Y 0x488f
|
|
#define CAR_mmDC_GPIO_PWRSEQ_MASK 0x4890
|
|
#define CAR_mmDC_GPIO_PWRSEQ_A 0x4891
|
|
#define CAR_mmDC_GPIO_PWRSEQ_EN 0x4892
|
|
#define CAR_mmDC_GPIO_PWRSEQ_Y 0x4893
|
|
#define CAR_mmDC_GPIO_PAD_STRENGTH_1 0x4894
|
|
#define CAR_mmDC_GPIO_PAD_STRENGTH_2 0x4895
|
|
#define CAR_mmPHY_AUX_CNTL 0x4897
|
|
#define CAR_mmDC_GPIO_I2CPAD_MASK 0x4898
|
|
#define CAR_mmDC_GPIO_I2CPAD_A 0x4899
|
|
#define CAR_mmDC_GPIO_I2CPAD_EN 0x489a
|
|
#define CAR_mmDC_GPIO_I2CPAD_Y 0x489b
|
|
#define CAR_mmDC_GPIO_I2CPAD_STRENGTH 0x489c
|
|
#define CAR_mmDVO_VREF_CONTROL 0x489e
|
|
#define CAR_mmDVO_SKEW_ADJUST 0x489f
|
|
#define CAR_mmDAC_MACRO_CNTL_RESERVED0 0x48b8
|
|
#define CAR_mmDAC_MACRO_CNTL_RESERVED1 0x48b9
|
|
#define CAR_mmDAC_MACRO_CNTL_RESERVED2 0x48ba
|
|
#define CAR_mmDAC_MACRO_CNTL_RESERVED3 0x48bb
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED0 0x48c0
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x48c0
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x48e0
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x4900
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x4920
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x4940
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x4960
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x4980
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED0 0x49c0
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0 0x49e0
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED1 0x48c1
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x48c1
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x48e1
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x4901
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x4921
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x4941
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x4961
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x4981
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED1 0x49c1
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1 0x49e1
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED2 0x48c2
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x48c2
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x48e2
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x4902
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x4922
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x4942
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x4962
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x4982
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED2 0x49c2
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2 0x49e2
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED3 0x48c3
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x48c3
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x48e3
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x4903
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x4923
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x4943
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x4963
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x4983
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED3 0x49c3
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3 0x49e3
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED4 0x48c4
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x48c4
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x48e4
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x4904
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x4924
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x4944
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x4964
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x4984
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED4 0x49c4
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4 0x49e4
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED5 0x48c5
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x48c5
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x48e5
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x4905
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x4925
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x4945
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x4965
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x4985
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED5 0x49c5
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5 0x49e5
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED6 0x48c6
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x48c6
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x48e6
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x4906
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x4926
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x4946
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x4966
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x4986
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED6 0x49c6
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6 0x49e6
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED7 0x48c7
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x48c7
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x48e7
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x4907
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x4927
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x4947
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x4967
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x4987
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED7 0x49c7
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7 0x49e7
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED8 0x48c8
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x48c8
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x48e8
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x4908
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x4928
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x4948
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x4968
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x4988
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED8 0x49c8
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8 0x49e8
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED9 0x48c9
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#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x48c9
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#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x48e9
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#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x4909
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#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x4929
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|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x4949
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x4969
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#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x4989
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#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED9 0x49c9
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#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9 0x49e9
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#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED10 0x48ca
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#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x48ca
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#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x48ea
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#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x490a
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|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x492a
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|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x494a
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#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x496a
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#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x498a
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#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED10 0x49ca
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#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10 0x49ea
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#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED11 0x48cb
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#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x48cb
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#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x48eb
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#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x490b
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#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x492b
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#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x494b
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#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x496b
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#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x498b
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#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED11 0x49cb
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|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11 0x49eb
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#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED12 0x48cc
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|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x48cc
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|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x48ec
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|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x490c
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|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x492c
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#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x494c
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#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x496c
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#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x498c
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|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED12 0x49cc
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|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12 0x49ec
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED13 0x48cd
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|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x48cd
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|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x48ed
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x490d
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x492d
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x494d
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x496d
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x498d
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED13 0x49cd
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13 0x49ed
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED14 0x48ce
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x48ce
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x48ee
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x490e
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x492e
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x494e
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|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x496e
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|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x498e
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|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED14 0x49ce
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|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14 0x49ee
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED15 0x48cf
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|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x48cf
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x48ef
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x490f
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|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x492f
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x494f
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|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x496f
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|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x498f
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|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED15 0x49cf
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|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15 0x49ef
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|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED16 0x48d0
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|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x48d0
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|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x48f0
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|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x4910
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|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x4930
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|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x4950
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|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x4970
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|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x4990
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|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED16 0x49d0
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|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16 0x49f0
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED17 0x48d1
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|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x48d1
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x48f1
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|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x4911
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x4931
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x4951
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|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x4971
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|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x4991
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|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED17 0x49d1
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17 0x49f1
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED18 0x48d2
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x48d2
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x48f2
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x4912
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x4932
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x4952
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|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x4972
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|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x4992
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|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED18 0x49d2
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|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18 0x49f2
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|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED19 0x48d3
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|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x48d3
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|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x48f3
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x4913
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x4933
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x4953
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|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x4973
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x4993
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED19 0x49d3
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19 0x49f3
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED20 0x48d4
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x48d4
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x48f4
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x4914
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x4934
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x4954
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x4974
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x4994
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED20 0x49d4
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20 0x49f4
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED21 0x48d5
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x48d5
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x48f5
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x4915
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x4935
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x4955
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x4975
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x4995
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED21 0x49d5
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21 0x49f5
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED22 0x48d6
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x48d6
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x48f6
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x4916
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x4936
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x4956
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x4976
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x4996
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED22 0x49d6
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22 0x49f6
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED23 0x48d7
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x48d7
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x48f7
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x4917
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x4937
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x4957
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x4977
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x4997
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED23 0x49d7
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23 0x49f7
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED24 0x48d8
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x48d8
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x48f8
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x4918
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x4938
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x4958
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x4978
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x4998
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED24 0x49d8
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24 0x49f8
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED25 0x48d9
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x48d9
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x48f9
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x4919
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x4939
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x4959
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x4979
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x4999
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED25 0x49d9
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25 0x49f9
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED26 0x48da
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x48da
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x48fa
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x491a
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x493a
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x495a
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x497a
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x499a
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED26 0x49da
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26 0x49fa
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED27 0x48db
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x48db
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x48fb
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x491b
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x493b
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x495b
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x497b
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x499b
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED27 0x49db
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27 0x49fb
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED28 0x48dc
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x48dc
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x48fc
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x491c
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x493c
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x495c
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x497c
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x499c
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED28 0x49dc
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28 0x49fc
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED29 0x48dd
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x48dd
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x48fd
|
|
#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x491d
|
|
#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x493d
|
|
#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x495d
|
|
#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x497d
|
|
#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x499d
|
|
#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED29 0x49dd
|
|
#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29 0x49fd
|
|
#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED30 0x48de
|
|
#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x48de
|
|
#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x48fe
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#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x491e
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#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x493e
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#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x495e
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#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x497e
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#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x499e
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#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED30 0x49de
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#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30 0x49fe
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#define CAR_mmUNIPHY_MACRO_CNTL_RESERVED31 0x48df
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#define CAR_mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x48df
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#define CAR_mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x48ff
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#define CAR_mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x491f
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#define CAR_mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x493f
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#define CAR_mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x495f
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#define CAR_mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x497f
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#define CAR_mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x499f
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#define CAR_mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED31 0x49df
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#define CAR_mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31 0x49ff
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED0 0x5a84
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED1 0x5a85
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED2 0x5a86
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED3 0x5a87
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED4 0x5a88
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED5 0x5a89
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED6 0x5a8a
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED7 0x5a8b
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED8 0x5a8c
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED9 0x5a8d
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED10 0x5a8e
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED11 0x5a8f
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED12 0x5a90
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED13 0x5a91
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED14 0x5a92
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED15 0x5a93
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED16 0x5a94
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED17 0x5a95
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED18 0x5a96
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED19 0x5a97
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED20 0x5a98
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED21 0x5a99
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED22 0x5a9a
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED23 0x5a9b
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED24 0x5a9c
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED25 0x5a9d
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED26 0x5a9e
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED27 0x5a9f
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED28 0x5aa0
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED29 0x5aa1
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED30 0x5aa2
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED31 0x5aa3
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED32 0x5aa4
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED33 0x5aa5
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED34 0x5aa6
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED35 0x5aa7
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED36 0x5aa8
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED37 0x5aa9
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED38 0x5aaa
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED39 0x5aab
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED40 0x5aac
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED41 0x5aad
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED42 0x5aae
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED43 0x5aaf
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED44 0x5ab0
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED45 0x5ab1
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED46 0x5ab2
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED47 0x5ab3
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED48 0x5ab4
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED49 0x5ab5
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED50 0x5ab6
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED51 0x5ab7
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED52 0x5ab8
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED53 0x5ab9
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED54 0x5aba
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED55 0x5abb
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED56 0x5abc
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED57 0x5abd
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED58 0x5abe
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED59 0x5abf
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED60 0x5ac0
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED61 0x5ac1
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED62 0x5ac2
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED63 0x5ac3
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED64 0x5ac4
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED65 0x5ac5
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED66 0x5ac6
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED67 0x5ac7
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED68 0x5ac8
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED69 0x5ac9
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED70 0x5aca
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED71 0x5acb
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED72 0x5acc
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED73 0x5acd
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED74 0x5ace
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED75 0x5acf
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED76 0x5ad0
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED77 0x5ad1
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED78 0x5ad2
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED79 0x5ad3
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED80 0x5ad4
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED81 0x5ad5
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED82 0x5ad6
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED83 0x5ad7
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED84 0x5ad8
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED85 0x5ad9
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED86 0x5ada
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED87 0x5adb
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED88 0x5adc
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED89 0x5add
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED90 0x5ade
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED91 0x5adf
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED92 0x5ae0
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED93 0x5ae1
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED94 0x5ae2
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED95 0x5ae3
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED96 0x5ae4
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED97 0x5ae5
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED98 0x5ae6
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED99 0x5ae7
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED100 0x5ae8
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED101 0x5ae9
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED102 0x5aea
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED103 0x5aeb
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED104 0x5aec
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED105 0x5aed
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED106 0x5aee
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED107 0x5aef
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED108 0x5af0
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED109 0x5af1
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED110 0x5af2
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED111 0x5af3
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED112 0x5af4
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED113 0x5af5
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED114 0x5af6
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED115 0x5af7
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED116 0x5af8
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED117 0x5af9
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED118 0x5afa
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED119 0x5afb
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED120 0x5afc
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED121 0x5afd
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED122 0x5afe
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED123 0x5aff
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED124 0x5b00
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED125 0x5b01
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED126 0x5b02
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED127 0x5b03
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED128 0x5b04
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED129 0x5b05
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED130 0x5b06
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED131 0x5b07
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED132 0x5b08
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED133 0x5b09
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED134 0x5b0a
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED135 0x5b0b
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED136 0x5b0c
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED137 0x5b0d
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED138 0x5b0e
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED139 0x5b0f
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED140 0x5b10
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED141 0x5b11
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED142 0x5b12
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED143 0x5b13
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED144 0x5b14
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED145 0x5b15
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED146 0x5b16
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED147 0x5b17
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED148 0x5b18
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED149 0x5b19
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED150 0x5b1a
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED151 0x5b1b
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED152 0x5b1c
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED153 0x5b1d
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED154 0x5b1e
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED155 0x5b1f
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED156 0x5b20
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED157 0x5b21
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED158 0x5b22
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED159 0x5b23
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED160 0x5b24
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED161 0x5b25
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED162 0x5b26
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED163 0x5b27
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED164 0x5b28
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED165 0x5b29
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED166 0x5b2a
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED167 0x5b2b
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED168 0x5b2c
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED169 0x5b2d
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED170 0x5b2e
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED171 0x5b2f
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED172 0x5b30
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED173 0x5b31
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED174 0x5b32
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED175 0x5b33
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED176 0x5b34
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED177 0x5b35
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED178 0x5b36
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED179 0x5b37
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED180 0x5b38
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED181 0x5b39
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED182 0x5b3a
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED183 0x5b3b
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED184 0x5b3c
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED185 0x5b3d
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED186 0x5b3e
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED187 0x5b3f
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED188 0x5b40
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED189 0x5b41
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED190 0x5b42
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED191 0x5b43
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED192 0x5b44
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED193 0x5b45
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED194 0x5b46
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED195 0x5b47
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED196 0x5b48
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED197 0x5b49
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED198 0x5b4a
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED199 0x5b4b
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED200 0x5b4c
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED201 0x5b4d
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED202 0x5b4e
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED203 0x5b4f
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED204 0x5b50
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED205 0x5b51
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED206 0x5b52
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED207 0x5b53
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED208 0x5b54
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED209 0x5b55
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED210 0x5b56
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED211 0x5b57
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED212 0x5b58
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED213 0x5b59
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED214 0x5b5a
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED215 0x5b5b
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED216 0x5b5c
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED217 0x5b5d
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED218 0x5b5e
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED219 0x5b5f
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED220 0x5b60
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED221 0x5b61
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED222 0x5b62
|
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED223 0x5b63
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED224 0x5b64
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED225 0x5b65
|
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED226 0x5b66
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED227 0x5b67
|
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED228 0x5b68
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED229 0x5b69
|
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED230 0x5b6a
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED231 0x5b6b
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED232 0x5b6c
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED233 0x5b6d
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED234 0x5b6e
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED235 0x5b6f
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED236 0x5b70
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED237 0x5b71
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED238 0x5b72
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|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED239 0x5b73
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|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED240 0x5b74
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|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED241 0x5b75
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED242 0x5b76
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED243 0x5b77
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED244 0x5b78
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED245 0x5b79
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED246 0x5b7a
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED247 0x5b7b
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED248 0x5b7c
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED249 0x5b7d
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED250 0x5b7e
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED251 0x5b7f
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED252 0x5b80
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|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED253 0x5b81
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED254 0x5b82
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED255 0x5b83
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|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED256 0x5b84
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|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED257 0x5b85
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|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED258 0x5b86
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED259 0x5b87
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|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED260 0x5b88
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED261 0x5b89
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|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED262 0x5b8a
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED263 0x5b8b
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|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED264 0x5b8c
|
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#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED265 0x5b8d
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|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED266 0x5b8e
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|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED267 0x5b8f
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED268 0x5b90
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED269 0x5b91
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED270 0x5b92
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED271 0x5b93
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED272 0x5b94
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED273 0x5b95
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED274 0x5b96
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED275 0x5b97
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED276 0x5b98
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED277 0x5b99
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED278 0x5b9a
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED279 0x5b9b
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED280 0x5b9c
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED281 0x5b9d
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED282 0x5b9e
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED283 0x5b9f
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED284 0x5ba0
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED285 0x5ba1
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED286 0x5ba2
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED287 0x5ba3
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED288 0x5ba4
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED289 0x5ba5
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED290 0x5ba6
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED291 0x5ba7
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED292 0x5ba8
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED293 0x5ba9
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED294 0x5baa
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED295 0x5bab
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED296 0x5bac
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED297 0x5bad
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED298 0x5bae
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED299 0x5baf
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED300 0x5bb0
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED301 0x5bb1
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED302 0x5bb2
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED303 0x5bb3
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED304 0x5bb4
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED305 0x5bb5
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED306 0x5bb6
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED307 0x5bb7
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED308 0x5bb8
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED309 0x5bb9
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED310 0x5bba
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED311 0x5bbb
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED312 0x5bbc
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED313 0x5bbd
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED314 0x5bbe
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED315 0x5bbf
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED316 0x5bc0
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED317 0x5bc1
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED318 0x5bc2
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED319 0x5bc3
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED320 0x5bc4
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED321 0x5bc5
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED322 0x5bc6
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED323 0x5bc7
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED324 0x5bc8
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED325 0x5bc9
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED326 0x5bca
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED327 0x5bcb
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED328 0x5bcc
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED329 0x5bcd
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED330 0x5bce
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED331 0x5bcf
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED332 0x5bd0
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED333 0x5bd1
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED334 0x5bd2
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED335 0x5bd3
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED336 0x5bd4
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED337 0x5bd5
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED338 0x5bd6
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED339 0x5bd7
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED340 0x5bd8
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED341 0x5bd9
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED342 0x5bda
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED343 0x5bdb
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED344 0x5bdc
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED345 0x5bdd
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED346 0x5bde
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED347 0x5bdf
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED348 0x5be0
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED349 0x5be1
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED350 0x5be2
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED351 0x5be3
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED352 0x5be4
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED353 0x5be5
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED354 0x5be6
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED355 0x5be7
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED356 0x5be8
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED357 0x5be9
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED358 0x5bea
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED359 0x5beb
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED360 0x5bec
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED361 0x5bed
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED362 0x5bee
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED363 0x5bef
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED364 0x5bf0
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED365 0x5bf1
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED366 0x5bf2
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED367 0x5bf3
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED368 0x5bf4
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED369 0x5bf5
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED370 0x5bf6
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED371 0x5bf7
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED372 0x5bf8
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED373 0x5bf9
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED374 0x5bfa
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED375 0x5bfb
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED376 0x5bfc
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED377 0x5bfd
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED378 0x5bfe
|
|
#define CAR_mmDCRX_PHY_MACRO_CNTL_RESERVED379 0x5bff
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED0 0x5d98
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED1 0x5d99
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED2 0x5d9a
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED3 0x5d9b
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED4 0x5d9c
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED5 0x5d9d
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED6 0x5d9e
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED7 0x5d9f
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED8 0x5da0
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED9 0x5da1
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED10 0x5da2
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED11 0x5da3
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED12 0x5da4
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED13 0x5da5
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED14 0x5da6
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED15 0x5da7
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED16 0x5da8
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED17 0x5da9
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED18 0x5daa
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED19 0x5dab
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED20 0x5dac
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED21 0x5dad
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED22 0x5dae
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED23 0x5daf
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED24 0x5db0
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED25 0x5db1
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED26 0x5db2
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED27 0x5db3
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED28 0x5db4
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED29 0x5db5
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED30 0x5db6
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED31 0x5db7
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED32 0x5db8
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED33 0x5db9
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED34 0x5dba
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED35 0x5dbb
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED36 0x5dbc
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED37 0x5dbd
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED38 0x5dbe
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED39 0x5dbf
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED40 0x5dc0
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED41 0x5dc1
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED42 0x5dc2
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED43 0x5dc3
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED44 0x5dc4
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED45 0x5dc5
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED46 0x5dc6
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED47 0x5dc7
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED48 0x5dc8
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED49 0x5dc9
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED50 0x5dca
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED51 0x5dcb
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED52 0x5dcc
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED53 0x5dcd
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED54 0x5dce
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED55 0x5dcf
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED56 0x5dd0
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED57 0x5dd1
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED58 0x5dd2
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED59 0x5dd3
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED60 0x5dd4
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED61 0x5dd5
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED62 0x5dd6
|
|
#define CAR_mmDPHY_MACRO_CNTL_RESERVED63 0x5dd7
|
|
#define CAR_mmGRPH_ENABLE 0x1a00
|
|
#define CAR_mmDCP0_GRPH_ENABLE 0x1a00
|
|
#define CAR_mmDCP1_GRPH_ENABLE 0x1c00
|
|
#define CAR_mmDCP2_GRPH_ENABLE 0x1e00
|
|
#define CAR_mmDCP3_GRPH_ENABLE 0x4000
|
|
#define CAR_mmDCP4_GRPH_ENABLE 0x4200
|
|
#define CAR_mmDCP5_GRPH_ENABLE 0x4400
|
|
#define CAR_mmGRPH_CONTROL 0x1a01
|
|
#define CAR_mmDCP0_GRPH_CONTROL 0x1a01
|
|
#define CAR_mmDCP1_GRPH_CONTROL 0x1c01
|
|
#define CAR_mmDCP2_GRPH_CONTROL 0x1e01
|
|
#define CAR_mmDCP3_GRPH_CONTROL 0x4001
|
|
#define CAR_mmDCP4_GRPH_CONTROL 0x4201
|
|
#define CAR_mmDCP5_GRPH_CONTROL 0x4401
|
|
#define CAR_mmGRPH_LUT_10BIT_BYPASS 0x1a02
|
|
#define CAR_mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1a02
|
|
#define CAR_mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1c02
|
|
#define CAR_mmDCP2_GRPH_LUT_10BIT_BYPASS 0x1e02
|
|
#define CAR_mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4002
|
|
#define CAR_mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4202
|
|
#define CAR_mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4402
|
|
#define CAR_mmGRPH_SWAP_CNTL 0x1a03
|
|
#define CAR_mmDCP0_GRPH_SWAP_CNTL 0x1a03
|
|
#define CAR_mmDCP1_GRPH_SWAP_CNTL 0x1c03
|
|
#define CAR_mmDCP2_GRPH_SWAP_CNTL 0x1e03
|
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#define CAR_mmDCP3_GRPH_SWAP_CNTL 0x4003
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#define CAR_mmDCP4_GRPH_SWAP_CNTL 0x4203
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#define CAR_mmDCP5_GRPH_SWAP_CNTL 0x4403
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#define CAR_mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
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#define CAR_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1a04
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#define CAR_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1c04
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#define CAR_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x1e04
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#define CAR_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004
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#define CAR_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4204
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#define CAR_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4404
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#define CAR_mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
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#define CAR_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1a05
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#define CAR_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1c05
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#define CAR_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x1e05
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#define CAR_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005
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#define CAR_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4205
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#define CAR_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4405
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#define CAR_mmGRPH_PITCH 0x1a06
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#define CAR_mmDCP0_GRPH_PITCH 0x1a06
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#define CAR_mmDCP1_GRPH_PITCH 0x1c06
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#define CAR_mmDCP2_GRPH_PITCH 0x1e06
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#define CAR_mmDCP3_GRPH_PITCH 0x4006
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#define CAR_mmDCP4_GRPH_PITCH 0x4206
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#define CAR_mmDCP5_GRPH_PITCH 0x4406
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#define CAR_mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
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#define CAR_mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1a07
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#define CAR_mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1c07
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#define CAR_mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1e07
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#define CAR_mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007
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#define CAR_mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4207
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#define CAR_mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4407
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#define CAR_mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
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#define CAR_mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1a08
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#define CAR_mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1c08
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#define CAR_mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1e08
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#define CAR_mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008
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#define CAR_mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4208
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#define CAR_mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4408
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#define CAR_mmGRPH_SURFACE_OFFSET_X 0x1a09
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#define CAR_mmDCP0_GRPH_SURFACE_OFFSET_X 0x1a09
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#define CAR_mmDCP1_GRPH_SURFACE_OFFSET_X 0x1c09
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#define CAR_mmDCP2_GRPH_SURFACE_OFFSET_X 0x1e09
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#define CAR_mmDCP3_GRPH_SURFACE_OFFSET_X 0x4009
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#define CAR_mmDCP4_GRPH_SURFACE_OFFSET_X 0x4209
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#define CAR_mmDCP5_GRPH_SURFACE_OFFSET_X 0x4409
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#define CAR_mmGRPH_SURFACE_OFFSET_Y 0x1a0a
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#define CAR_mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1a0a
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#define CAR_mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1c0a
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#define CAR_mmDCP2_GRPH_SURFACE_OFFSET_Y 0x1e0a
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#define CAR_mmDCP3_GRPH_SURFACE_OFFSET_Y 0x400a
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#define CAR_mmDCP4_GRPH_SURFACE_OFFSET_Y 0x420a
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#define CAR_mmDCP5_GRPH_SURFACE_OFFSET_Y 0x440a
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#define CAR_mmGRPH_X_START 0x1a0b
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#define CAR_mmDCP0_GRPH_X_START 0x1a0b
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#define CAR_mmDCP1_GRPH_X_START 0x1c0b
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#define CAR_mmDCP2_GRPH_X_START 0x1e0b
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#define CAR_mmDCP3_GRPH_X_START 0x400b
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#define CAR_mmDCP4_GRPH_X_START 0x420b
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#define CAR_mmDCP5_GRPH_X_START 0x440b
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#define CAR_mmGRPH_Y_START 0x1a0c
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#define CAR_mmDCP0_GRPH_Y_START 0x1a0c
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#define CAR_mmDCP1_GRPH_Y_START 0x1c0c
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#define CAR_mmDCP2_GRPH_Y_START 0x1e0c
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#define CAR_mmDCP3_GRPH_Y_START 0x400c
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#define CAR_mmDCP4_GRPH_Y_START 0x420c
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#define CAR_mmDCP5_GRPH_Y_START 0x440c
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#define CAR_mmGRPH_X_END 0x1a0d
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#define CAR_mmDCP0_GRPH_X_END 0x1a0d
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#define CAR_mmDCP1_GRPH_X_END 0x1c0d
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#define CAR_mmDCP2_GRPH_X_END 0x1e0d
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#define CAR_mmDCP3_GRPH_X_END 0x400d
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#define CAR_mmDCP4_GRPH_X_END 0x420d
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#define CAR_mmDCP5_GRPH_X_END 0x440d
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#define CAR_mmGRPH_Y_END 0x1a0e
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#define CAR_mmDCP0_GRPH_Y_END 0x1a0e
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#define CAR_mmDCP1_GRPH_Y_END 0x1c0e
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#define CAR_mmDCP2_GRPH_Y_END 0x1e0e
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#define CAR_mmDCP3_GRPH_Y_END 0x400e
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#define CAR_mmDCP4_GRPH_Y_END 0x420e
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#define CAR_mmDCP5_GRPH_Y_END 0x440e
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#define CAR_mmINPUT_GAMMA_CONTROL 0x1a10
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#define CAR_mmDCP0_INPUT_GAMMA_CONTROL 0x1a10
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#define CAR_mmDCP1_INPUT_GAMMA_CONTROL 0x1c10
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#define CAR_mmDCP2_INPUT_GAMMA_CONTROL 0x1e10
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#define CAR_mmDCP3_INPUT_GAMMA_CONTROL 0x4010
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#define CAR_mmDCP4_INPUT_GAMMA_CONTROL 0x4210
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#define CAR_mmDCP5_INPUT_GAMMA_CONTROL 0x4410
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#define CAR_mmGRPH_UPDATE 0x1a11
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#define CAR_mmDCP0_GRPH_UPDATE 0x1a11
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#define CAR_mmDCP1_GRPH_UPDATE 0x1c11
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#define CAR_mmDCP2_GRPH_UPDATE 0x1e11
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#define CAR_mmDCP3_GRPH_UPDATE 0x4011
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#define CAR_mmDCP4_GRPH_UPDATE 0x4211
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#define CAR_mmDCP5_GRPH_UPDATE 0x4411
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#define CAR_mmGRPH_FLIP_CONTROL 0x1a12
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#define CAR_mmDCP0_GRPH_FLIP_CONTROL 0x1a12
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#define CAR_mmDCP1_GRPH_FLIP_CONTROL 0x1c12
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#define CAR_mmDCP2_GRPH_FLIP_CONTROL 0x1e12
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#define CAR_mmDCP3_GRPH_FLIP_CONTROL 0x4012
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#define CAR_mmDCP4_GRPH_FLIP_CONTROL 0x4212
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#define CAR_mmDCP5_GRPH_FLIP_CONTROL 0x4412
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#define CAR_mmGRPH_SURFACE_ADDRESS_INUSE 0x1a13
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#define CAR_mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1a13
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#define CAR_mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1c13
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#define CAR_mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x1e13
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#define CAR_mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4013
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#define CAR_mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4213
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#define CAR_mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4413
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#define CAR_mmGRPH_DFQ_CONTROL 0x1a14
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#define CAR_mmDCP0_GRPH_DFQ_CONTROL 0x1a14
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#define CAR_mmDCP1_GRPH_DFQ_CONTROL 0x1c14
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#define CAR_mmDCP2_GRPH_DFQ_CONTROL 0x1e14
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#define CAR_mmDCP3_GRPH_DFQ_CONTROL 0x4014
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#define CAR_mmDCP4_GRPH_DFQ_CONTROL 0x4214
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#define CAR_mmDCP5_GRPH_DFQ_CONTROL 0x4414
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#define CAR_mmGRPH_DFQ_STATUS 0x1a15
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#define CAR_mmDCP0_GRPH_DFQ_STATUS 0x1a15
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#define CAR_mmDCP1_GRPH_DFQ_STATUS 0x1c15
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#define CAR_mmDCP2_GRPH_DFQ_STATUS 0x1e15
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#define CAR_mmDCP3_GRPH_DFQ_STATUS 0x4015
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#define CAR_mmDCP4_GRPH_DFQ_STATUS 0x4215
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#define CAR_mmDCP5_GRPH_DFQ_STATUS 0x4415
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#define CAR_mmGRPH_INTERRUPT_STATUS 0x1a16
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#define CAR_mmDCP0_GRPH_INTERRUPT_STATUS 0x1a16
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#define CAR_mmDCP1_GRPH_INTERRUPT_STATUS 0x1c16
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#define CAR_mmDCP2_GRPH_INTERRUPT_STATUS 0x1e16
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#define CAR_mmDCP3_GRPH_INTERRUPT_STATUS 0x4016
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#define CAR_mmDCP4_GRPH_INTERRUPT_STATUS 0x4216
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#define CAR_mmDCP5_GRPH_INTERRUPT_STATUS 0x4416
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#define CAR_mmGRPH_INTERRUPT_CONTROL 0x1a17
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#define CAR_mmDCP0_GRPH_INTERRUPT_CONTROL 0x1a17
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#define CAR_mmDCP1_GRPH_INTERRUPT_CONTROL 0x1c17
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#define CAR_mmDCP2_GRPH_INTERRUPT_CONTROL 0x1e17
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#define CAR_mmDCP3_GRPH_INTERRUPT_CONTROL 0x4017
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#define CAR_mmDCP4_GRPH_INTERRUPT_CONTROL 0x4217
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#define CAR_mmDCP5_GRPH_INTERRUPT_CONTROL 0x4417
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#define CAR_mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18
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#define CAR_mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1a18
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#define CAR_mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1c18
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#define CAR_mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1e18
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#define CAR_mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018
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#define CAR_mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4218
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#define CAR_mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4418
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#define CAR_mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1a19
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#define CAR_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1a19
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#define CAR_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1c19
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#define CAR_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x1e19
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#define CAR_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019
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#define CAR_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4219
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#define CAR_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4419
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#define CAR_mmGRPH_COMPRESS_PITCH 0x1a1a
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#define CAR_mmDCP0_GRPH_COMPRESS_PITCH 0x1a1a
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#define CAR_mmDCP1_GRPH_COMPRESS_PITCH 0x1c1a
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#define CAR_mmDCP2_GRPH_COMPRESS_PITCH 0x1e1a
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#define CAR_mmDCP3_GRPH_COMPRESS_PITCH 0x401a
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#define CAR_mmDCP4_GRPH_COMPRESS_PITCH 0x421a
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#define CAR_mmDCP5_GRPH_COMPRESS_PITCH 0x441a
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#define CAR_mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b
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#define CAR_mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1a1b
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#define CAR_mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1c1b
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#define CAR_mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1e1b
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#define CAR_mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401b
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#define CAR_mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x421b
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#define CAR_mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x441b
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#define CAR_mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c
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#define CAR_mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1a1c
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#define CAR_mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1c1c
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#define CAR_mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x1e1c
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#define CAR_mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x401c
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#define CAR_mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x421c
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#define CAR_mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT 0x441c
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#define CAR_mmPRESCALE_GRPH_CONTROL 0x1a2d
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#define CAR_mmDCP0_PRESCALE_GRPH_CONTROL 0x1a2d
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#define CAR_mmDCP1_PRESCALE_GRPH_CONTROL 0x1c2d
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#define CAR_mmDCP2_PRESCALE_GRPH_CONTROL 0x1e2d
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#define CAR_mmDCP3_PRESCALE_GRPH_CONTROL 0x402d
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#define CAR_mmDCP4_PRESCALE_GRPH_CONTROL 0x422d
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#define CAR_mmDCP5_PRESCALE_GRPH_CONTROL 0x442d
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#define CAR_mmPRESCALE_VALUES_GRPH_R 0x1a2e
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#define CAR_mmDCP0_PRESCALE_VALUES_GRPH_R 0x1a2e
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#define CAR_mmDCP1_PRESCALE_VALUES_GRPH_R 0x1c2e
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#define CAR_mmDCP2_PRESCALE_VALUES_GRPH_R 0x1e2e
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#define CAR_mmDCP3_PRESCALE_VALUES_GRPH_R 0x402e
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#define CAR_mmDCP4_PRESCALE_VALUES_GRPH_R 0x422e
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#define CAR_mmDCP5_PRESCALE_VALUES_GRPH_R 0x442e
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#define CAR_mmPRESCALE_VALUES_GRPH_G 0x1a2f
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#define CAR_mmDCP0_PRESCALE_VALUES_GRPH_G 0x1a2f
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#define CAR_mmDCP1_PRESCALE_VALUES_GRPH_G 0x1c2f
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#define CAR_mmDCP2_PRESCALE_VALUES_GRPH_G 0x1e2f
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#define CAR_mmDCP3_PRESCALE_VALUES_GRPH_G 0x402f
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#define CAR_mmDCP4_PRESCALE_VALUES_GRPH_G 0x422f
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#define CAR_mmDCP5_PRESCALE_VALUES_GRPH_G 0x442f
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#define CAR_mmPRESCALE_VALUES_GRPH_B 0x1a30
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#define CAR_mmDCP0_PRESCALE_VALUES_GRPH_B 0x1a30
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#define CAR_mmDCP1_PRESCALE_VALUES_GRPH_B 0x1c30
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#define CAR_mmDCP2_PRESCALE_VALUES_GRPH_B 0x1e30
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#define CAR_mmDCP3_PRESCALE_VALUES_GRPH_B 0x4030
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#define CAR_mmDCP4_PRESCALE_VALUES_GRPH_B 0x4230
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#define CAR_mmDCP5_PRESCALE_VALUES_GRPH_B 0x4430
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#define CAR_mmINPUT_CSC_CONTROL 0x1a35
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#define CAR_mmDCP0_INPUT_CSC_CONTROL 0x1a35
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#define CAR_mmDCP1_INPUT_CSC_CONTROL 0x1c35
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#define CAR_mmDCP2_INPUT_CSC_CONTROL 0x1e35
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#define CAR_mmDCP3_INPUT_CSC_CONTROL 0x4035
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#define CAR_mmDCP4_INPUT_CSC_CONTROL 0x4235
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#define CAR_mmDCP5_INPUT_CSC_CONTROL 0x4435
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#define CAR_mmINPUT_CSC_C11_C12 0x1a36
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#define CAR_mmDCP0_INPUT_CSC_C11_C12 0x1a36
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#define CAR_mmDCP1_INPUT_CSC_C11_C12 0x1c36
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#define CAR_mmDCP2_INPUT_CSC_C11_C12 0x1e36
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#define CAR_mmDCP3_INPUT_CSC_C11_C12 0x4036
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#define CAR_mmDCP4_INPUT_CSC_C11_C12 0x4236
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#define CAR_mmDCP5_INPUT_CSC_C11_C12 0x4436
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#define CAR_mmINPUT_CSC_C13_C14 0x1a37
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#define CAR_mmDCP0_INPUT_CSC_C13_C14 0x1a37
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#define CAR_mmDCP1_INPUT_CSC_C13_C14 0x1c37
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#define CAR_mmDCP2_INPUT_CSC_C13_C14 0x1e37
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#define CAR_mmDCP3_INPUT_CSC_C13_C14 0x4037
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#define CAR_mmDCP4_INPUT_CSC_C13_C14 0x4237
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#define CAR_mmDCP5_INPUT_CSC_C13_C14 0x4437
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#define CAR_mmINPUT_CSC_C21_C22 0x1a38
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#define CAR_mmDCP0_INPUT_CSC_C21_C22 0x1a38
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#define CAR_mmDCP1_INPUT_CSC_C21_C22 0x1c38
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#define CAR_mmDCP2_INPUT_CSC_C21_C22 0x1e38
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#define CAR_mmDCP3_INPUT_CSC_C21_C22 0x4038
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#define CAR_mmDCP4_INPUT_CSC_C21_C22 0x4238
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#define CAR_mmDCP5_INPUT_CSC_C21_C22 0x4438
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#define CAR_mmINPUT_CSC_C23_C24 0x1a39
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#define CAR_mmDCP0_INPUT_CSC_C23_C24 0x1a39
|
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#define CAR_mmDCP1_INPUT_CSC_C23_C24 0x1c39
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#define CAR_mmDCP2_INPUT_CSC_C23_C24 0x1e39
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#define CAR_mmDCP3_INPUT_CSC_C23_C24 0x4039
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#define CAR_mmDCP4_INPUT_CSC_C23_C24 0x4239
|
|
#define CAR_mmDCP5_INPUT_CSC_C23_C24 0x4439
|
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#define CAR_mmINPUT_CSC_C31_C32 0x1a3a
|
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#define CAR_mmDCP0_INPUT_CSC_C31_C32 0x1a3a
|
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#define CAR_mmDCP1_INPUT_CSC_C31_C32 0x1c3a
|
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#define CAR_mmDCP2_INPUT_CSC_C31_C32 0x1e3a
|
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#define CAR_mmDCP3_INPUT_CSC_C31_C32 0x403a
|
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#define CAR_mmDCP4_INPUT_CSC_C31_C32 0x423a
|
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#define CAR_mmDCP5_INPUT_CSC_C31_C32 0x443a
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#define CAR_mmINPUT_CSC_C33_C34 0x1a3b
|
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#define CAR_mmDCP0_INPUT_CSC_C33_C34 0x1a3b
|
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#define CAR_mmDCP1_INPUT_CSC_C33_C34 0x1c3b
|
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#define CAR_mmDCP2_INPUT_CSC_C33_C34 0x1e3b
|
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#define CAR_mmDCP3_INPUT_CSC_C33_C34 0x403b
|
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#define CAR_mmDCP4_INPUT_CSC_C33_C34 0x423b
|
|
#define CAR_mmDCP5_INPUT_CSC_C33_C34 0x443b
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#define CAR_mmOUTPUT_CSC_CONTROL 0x1a3c
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#define CAR_mmDCP0_OUTPUT_CSC_CONTROL 0x1a3c
|
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#define CAR_mmDCP1_OUTPUT_CSC_CONTROL 0x1c3c
|
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#define CAR_mmDCP2_OUTPUT_CSC_CONTROL 0x1e3c
|
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#define CAR_mmDCP3_OUTPUT_CSC_CONTROL 0x403c
|
|
#define CAR_mmDCP4_OUTPUT_CSC_CONTROL 0x423c
|
|
#define CAR_mmDCP5_OUTPUT_CSC_CONTROL 0x443c
|
|
#define CAR_mmOUTPUT_CSC_C11_C12 0x1a3d
|
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#define CAR_mmDCP0_OUTPUT_CSC_C11_C12 0x1a3d
|
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#define CAR_mmDCP1_OUTPUT_CSC_C11_C12 0x1c3d
|
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#define CAR_mmDCP2_OUTPUT_CSC_C11_C12 0x1e3d
|
|
#define CAR_mmDCP3_OUTPUT_CSC_C11_C12 0x403d
|
|
#define CAR_mmDCP4_OUTPUT_CSC_C11_C12 0x423d
|
|
#define CAR_mmDCP5_OUTPUT_CSC_C11_C12 0x443d
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#define CAR_mmOUTPUT_CSC_C13_C14 0x1a3e
|
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#define CAR_mmDCP0_OUTPUT_CSC_C13_C14 0x1a3e
|
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#define CAR_mmDCP1_OUTPUT_CSC_C13_C14 0x1c3e
|
|
#define CAR_mmDCP2_OUTPUT_CSC_C13_C14 0x1e3e
|
|
#define CAR_mmDCP3_OUTPUT_CSC_C13_C14 0x403e
|
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#define CAR_mmDCP4_OUTPUT_CSC_C13_C14 0x423e
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#define CAR_mmDCP5_OUTPUT_CSC_C13_C14 0x443e
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#define CAR_mmOUTPUT_CSC_C21_C22 0x1a3f
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#define CAR_mmDCP0_OUTPUT_CSC_C21_C22 0x1a3f
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#define CAR_mmDCP1_OUTPUT_CSC_C21_C22 0x1c3f
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#define CAR_mmDCP2_OUTPUT_CSC_C21_C22 0x1e3f
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#define CAR_mmDCP3_OUTPUT_CSC_C21_C22 0x403f
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#define CAR_mmDCP4_OUTPUT_CSC_C21_C22 0x423f
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#define CAR_mmDCP5_OUTPUT_CSC_C21_C22 0x443f
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#define CAR_mmOUTPUT_CSC_C23_C24 0x1a40
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#define CAR_mmDCP0_OUTPUT_CSC_C23_C24 0x1a40
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#define CAR_mmDCP1_OUTPUT_CSC_C23_C24 0x1c40
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#define CAR_mmDCP2_OUTPUT_CSC_C23_C24 0x1e40
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#define CAR_mmDCP3_OUTPUT_CSC_C23_C24 0x4040
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#define CAR_mmDCP4_OUTPUT_CSC_C23_C24 0x4240
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#define CAR_mmDCP5_OUTPUT_CSC_C23_C24 0x4440
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#define CAR_mmOUTPUT_CSC_C31_C32 0x1a41
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#define CAR_mmDCP0_OUTPUT_CSC_C31_C32 0x1a41
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#define CAR_mmDCP1_OUTPUT_CSC_C31_C32 0x1c41
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#define CAR_mmDCP2_OUTPUT_CSC_C31_C32 0x1e41
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#define CAR_mmDCP3_OUTPUT_CSC_C31_C32 0x4041
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#define CAR_mmDCP4_OUTPUT_CSC_C31_C32 0x4241
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#define CAR_mmDCP5_OUTPUT_CSC_C31_C32 0x4441
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#define CAR_mmOUTPUT_CSC_C33_C34 0x1a42
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#define CAR_mmDCP0_OUTPUT_CSC_C33_C34 0x1a42
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#define CAR_mmDCP1_OUTPUT_CSC_C33_C34 0x1c42
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#define CAR_mmDCP2_OUTPUT_CSC_C33_C34 0x1e42
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#define CAR_mmDCP3_OUTPUT_CSC_C33_C34 0x4042
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#define CAR_mmDCP4_OUTPUT_CSC_C33_C34 0x4242
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#define CAR_mmDCP5_OUTPUT_CSC_C33_C34 0x4442
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#define CAR_mmCOMM_MATRIXA_TRANS_C11_C12 0x1a43
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#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1a43
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#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1c43
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#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x1e43
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#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4043
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#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4243
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#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4443
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#define CAR_mmCOMM_MATRIXA_TRANS_C13_C14 0x1a44
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#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1a44
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#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1c44
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#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x1e44
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#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4044
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#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4244
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#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4444
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#define CAR_mmCOMM_MATRIXA_TRANS_C21_C22 0x1a45
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#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1a45
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#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1c45
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#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x1e45
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#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4045
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#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4245
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#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4445
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#define CAR_mmCOMM_MATRIXA_TRANS_C23_C24 0x1a46
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#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1a46
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#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1c46
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#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x1e46
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#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4046
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#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4246
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#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4446
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#define CAR_mmCOMM_MATRIXA_TRANS_C31_C32 0x1a47
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#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1a47
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#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1c47
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#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x1e47
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#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4047
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#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4247
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#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4447
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#define CAR_mmCOMM_MATRIXA_TRANS_C33_C34 0x1a48
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#define CAR_mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1a48
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#define CAR_mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1c48
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#define CAR_mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x1e48
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#define CAR_mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4048
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#define CAR_mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4248
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#define CAR_mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4448
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#define CAR_mmCOMM_MATRIXB_TRANS_C11_C12 0x1a49
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#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1a49
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#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1c49
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#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x1e49
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#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4049
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#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4249
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#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4449
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#define CAR_mmCOMM_MATRIXB_TRANS_C13_C14 0x1a4a
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#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1a4a
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#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1c4a
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#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x1e4a
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#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x404a
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#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x424a
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#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x444a
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#define CAR_mmCOMM_MATRIXB_TRANS_C21_C22 0x1a4b
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#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1a4b
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#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1c4b
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#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x1e4b
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#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x404b
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#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x424b
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#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x444b
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#define CAR_mmCOMM_MATRIXB_TRANS_C23_C24 0x1a4c
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#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1a4c
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#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1c4c
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#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x1e4c
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#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x404c
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#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x424c
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#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x444c
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#define CAR_mmCOMM_MATRIXB_TRANS_C31_C32 0x1a4d
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#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1a4d
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#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1c4d
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#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x1e4d
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#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x404d
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#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x424d
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#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x444d
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#define CAR_mmCOMM_MATRIXB_TRANS_C33_C34 0x1a4e
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#define CAR_mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1a4e
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#define CAR_mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1c4e
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#define CAR_mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x1e4e
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#define CAR_mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x404e
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#define CAR_mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x424e
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#define CAR_mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x444e
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#define CAR_mmDENORM_CONTROL 0x1a50
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#define CAR_mmDCP0_DENORM_CONTROL 0x1a50
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#define CAR_mmDCP1_DENORM_CONTROL 0x1c50
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#define CAR_mmDCP2_DENORM_CONTROL 0x1e50
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#define CAR_mmDCP3_DENORM_CONTROL 0x4050
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#define CAR_mmDCP4_DENORM_CONTROL 0x4250
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#define CAR_mmDCP5_DENORM_CONTROL 0x4450
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#define CAR_mmOUT_ROUND_CONTROL 0x1a51
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#define CAR_mmDCP0_OUT_ROUND_CONTROL 0x1a51
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#define CAR_mmDCP1_OUT_ROUND_CONTROL 0x1c51
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#define CAR_mmDCP2_OUT_ROUND_CONTROL 0x1e51
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#define CAR_mmDCP3_OUT_ROUND_CONTROL 0x4051
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#define CAR_mmDCP4_OUT_ROUND_CONTROL 0x4251
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#define CAR_mmDCP5_OUT_ROUND_CONTROL 0x4451
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#define CAR_mmOUT_CLAMP_CONTROL_R_CR 0x1a52
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#define CAR_mmDCP0_OUT_CLAMP_CONTROL_R_CR 0x1a52
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#define CAR_mmDCP1_OUT_CLAMP_CONTROL_R_CR 0x1c52
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#define CAR_mmDCP2_OUT_CLAMP_CONTROL_R_CR 0x1e52
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#define CAR_mmDCP3_OUT_CLAMP_CONTROL_R_CR 0x4052
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#define CAR_mmDCP4_OUT_CLAMP_CONTROL_R_CR 0x4252
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#define CAR_mmDCP5_OUT_CLAMP_CONTROL_R_CR 0x4452
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#define CAR_mmOUT_CLAMP_CONTROL_G_Y 0x1a9c
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#define CAR_mmDCP0_OUT_CLAMP_CONTROL_G_Y 0x1a9c
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#define CAR_mmDCP1_OUT_CLAMP_CONTROL_G_Y 0x1c9c
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#define CAR_mmDCP2_OUT_CLAMP_CONTROL_G_Y 0x1e9c
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#define CAR_mmDCP3_OUT_CLAMP_CONTROL_G_Y 0x409c
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#define CAR_mmDCP4_OUT_CLAMP_CONTROL_G_Y 0x429c
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#define CAR_mmDCP5_OUT_CLAMP_CONTROL_G_Y 0x449c
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#define CAR_mmOUT_CLAMP_CONTROL_B_CB 0x1a9d
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#define CAR_mmDCP0_OUT_CLAMP_CONTROL_B_CB 0x1a9d
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#define CAR_mmDCP1_OUT_CLAMP_CONTROL_B_CB 0x1c9d
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#define CAR_mmDCP2_OUT_CLAMP_CONTROL_B_CB 0x1e9d
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#define CAR_mmDCP3_OUT_CLAMP_CONTROL_B_CB 0x409d
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#define CAR_mmDCP4_OUT_CLAMP_CONTROL_B_CB 0x429d
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#define CAR_mmDCP5_OUT_CLAMP_CONTROL_B_CB 0x449d
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#define CAR_mmKEY_CONTROL 0x1a53
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#define CAR_mmDCP0_KEY_CONTROL 0x1a53
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#define CAR_mmDCP1_KEY_CONTROL 0x1c53
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#define CAR_mmDCP2_KEY_CONTROL 0x1e53
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#define CAR_mmDCP3_KEY_CONTROL 0x4053
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#define CAR_mmDCP4_KEY_CONTROL 0x4253
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#define CAR_mmDCP5_KEY_CONTROL 0x4453
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#define CAR_mmKEY_RANGE_ALPHA 0x1a54
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#define CAR_mmDCP0_KEY_RANGE_ALPHA 0x1a54
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#define CAR_mmDCP1_KEY_RANGE_ALPHA 0x1c54
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#define CAR_mmDCP2_KEY_RANGE_ALPHA 0x1e54
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#define CAR_mmDCP3_KEY_RANGE_ALPHA 0x4054
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#define CAR_mmDCP4_KEY_RANGE_ALPHA 0x4254
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#define CAR_mmDCP5_KEY_RANGE_ALPHA 0x4454
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#define CAR_mmKEY_RANGE_RED 0x1a55
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#define CAR_mmDCP0_KEY_RANGE_RED 0x1a55
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#define CAR_mmDCP1_KEY_RANGE_RED 0x1c55
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#define CAR_mmDCP2_KEY_RANGE_RED 0x1e55
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#define CAR_mmDCP3_KEY_RANGE_RED 0x4055
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#define CAR_mmDCP4_KEY_RANGE_RED 0x4255
|
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#define CAR_mmDCP5_KEY_RANGE_RED 0x4455
|
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#define CAR_mmKEY_RANGE_GREEN 0x1a56
|
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#define CAR_mmDCP0_KEY_RANGE_GREEN 0x1a56
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#define CAR_mmDCP1_KEY_RANGE_GREEN 0x1c56
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#define CAR_mmDCP2_KEY_RANGE_GREEN 0x1e56
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#define CAR_mmDCP3_KEY_RANGE_GREEN 0x4056
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#define CAR_mmDCP4_KEY_RANGE_GREEN 0x4256
|
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#define CAR_mmDCP5_KEY_RANGE_GREEN 0x4456
|
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#define CAR_mmKEY_RANGE_BLUE 0x1a57
|
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#define CAR_mmDCP0_KEY_RANGE_BLUE 0x1a57
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#define CAR_mmDCP1_KEY_RANGE_BLUE 0x1c57
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#define CAR_mmDCP2_KEY_RANGE_BLUE 0x1e57
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#define CAR_mmDCP3_KEY_RANGE_BLUE 0x4057
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#define CAR_mmDCP4_KEY_RANGE_BLUE 0x4257
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#define CAR_mmDCP5_KEY_RANGE_BLUE 0x4457
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#define CAR_mmDEGAMMA_CONTROL 0x1a58
|
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#define CAR_mmDCP0_DEGAMMA_CONTROL 0x1a58
|
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#define CAR_mmDCP1_DEGAMMA_CONTROL 0x1c58
|
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#define CAR_mmDCP2_DEGAMMA_CONTROL 0x1e58
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#define CAR_mmDCP3_DEGAMMA_CONTROL 0x4058
|
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#define CAR_mmDCP4_DEGAMMA_CONTROL 0x4258
|
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#define CAR_mmDCP5_DEGAMMA_CONTROL 0x4458
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#define CAR_mmGAMUT_REMAP_CONTROL 0x1a59
|
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#define CAR_mmDCP0_GAMUT_REMAP_CONTROL 0x1a59
|
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#define CAR_mmDCP1_GAMUT_REMAP_CONTROL 0x1c59
|
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#define CAR_mmDCP2_GAMUT_REMAP_CONTROL 0x1e59
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#define CAR_mmDCP3_GAMUT_REMAP_CONTROL 0x4059
|
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#define CAR_mmDCP4_GAMUT_REMAP_CONTROL 0x4259
|
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#define CAR_mmDCP5_GAMUT_REMAP_CONTROL 0x4459
|
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#define CAR_mmGAMUT_REMAP_C11_C12 0x1a5a
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#define CAR_mmDCP0_GAMUT_REMAP_C11_C12 0x1a5a
|
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#define CAR_mmDCP1_GAMUT_REMAP_C11_C12 0x1c5a
|
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#define CAR_mmDCP2_GAMUT_REMAP_C11_C12 0x1e5a
|
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#define CAR_mmDCP3_GAMUT_REMAP_C11_C12 0x405a
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#define CAR_mmDCP4_GAMUT_REMAP_C11_C12 0x425a
|
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#define CAR_mmDCP5_GAMUT_REMAP_C11_C12 0x445a
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#define CAR_mmGAMUT_REMAP_C13_C14 0x1a5b
|
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#define CAR_mmDCP0_GAMUT_REMAP_C13_C14 0x1a5b
|
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#define CAR_mmDCP1_GAMUT_REMAP_C13_C14 0x1c5b
|
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#define CAR_mmDCP2_GAMUT_REMAP_C13_C14 0x1e5b
|
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#define CAR_mmDCP3_GAMUT_REMAP_C13_C14 0x405b
|
|
#define CAR_mmDCP4_GAMUT_REMAP_C13_C14 0x425b
|
|
#define CAR_mmDCP5_GAMUT_REMAP_C13_C14 0x445b
|
|
#define CAR_mmGAMUT_REMAP_C21_C22 0x1a5c
|
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#define CAR_mmDCP0_GAMUT_REMAP_C21_C22 0x1a5c
|
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#define CAR_mmDCP1_GAMUT_REMAP_C21_C22 0x1c5c
|
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#define CAR_mmDCP2_GAMUT_REMAP_C21_C22 0x1e5c
|
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#define CAR_mmDCP3_GAMUT_REMAP_C21_C22 0x405c
|
|
#define CAR_mmDCP4_GAMUT_REMAP_C21_C22 0x425c
|
|
#define CAR_mmDCP5_GAMUT_REMAP_C21_C22 0x445c
|
|
#define CAR_mmGAMUT_REMAP_C23_C24 0x1a5d
|
|
#define CAR_mmDCP0_GAMUT_REMAP_C23_C24 0x1a5d
|
|
#define CAR_mmDCP1_GAMUT_REMAP_C23_C24 0x1c5d
|
|
#define CAR_mmDCP2_GAMUT_REMAP_C23_C24 0x1e5d
|
|
#define CAR_mmDCP3_GAMUT_REMAP_C23_C24 0x405d
|
|
#define CAR_mmDCP4_GAMUT_REMAP_C23_C24 0x425d
|
|
#define CAR_mmDCP5_GAMUT_REMAP_C23_C24 0x445d
|
|
#define CAR_mmGAMUT_REMAP_C31_C32 0x1a5e
|
|
#define CAR_mmDCP0_GAMUT_REMAP_C31_C32 0x1a5e
|
|
#define CAR_mmDCP1_GAMUT_REMAP_C31_C32 0x1c5e
|
|
#define CAR_mmDCP2_GAMUT_REMAP_C31_C32 0x1e5e
|
|
#define CAR_mmDCP3_GAMUT_REMAP_C31_C32 0x405e
|
|
#define CAR_mmDCP4_GAMUT_REMAP_C31_C32 0x425e
|
|
#define CAR_mmDCP5_GAMUT_REMAP_C31_C32 0x445e
|
|
#define CAR_mmGAMUT_REMAP_C33_C34 0x1a5f
|
|
#define CAR_mmDCP0_GAMUT_REMAP_C33_C34 0x1a5f
|
|
#define CAR_mmDCP1_GAMUT_REMAP_C33_C34 0x1c5f
|
|
#define CAR_mmDCP2_GAMUT_REMAP_C33_C34 0x1e5f
|
|
#define CAR_mmDCP3_GAMUT_REMAP_C33_C34 0x405f
|
|
#define CAR_mmDCP4_GAMUT_REMAP_C33_C34 0x425f
|
|
#define CAR_mmDCP5_GAMUT_REMAP_C33_C34 0x445f
|
|
#define CAR_mmDCP_SPATIAL_DITHER_CNTL 0x1a60
|
|
#define CAR_mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1a60
|
|
#define CAR_mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1c60
|
|
#define CAR_mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x1e60
|
|
#define CAR_mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4060
|
|
#define CAR_mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4260
|
|
#define CAR_mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4460
|
|
#define CAR_mmDCP_FP_CONVERTED_FIELD 0x1a65
|
|
#define CAR_mmDCP0_DCP_FP_CONVERTED_FIELD 0x1a65
|
|
#define CAR_mmDCP1_DCP_FP_CONVERTED_FIELD 0x1c65
|
|
#define CAR_mmDCP2_DCP_FP_CONVERTED_FIELD 0x1e65
|
|
#define CAR_mmDCP3_DCP_FP_CONVERTED_FIELD 0x4065
|
|
#define CAR_mmDCP4_DCP_FP_CONVERTED_FIELD 0x4265
|
|
#define CAR_mmDCP5_DCP_FP_CONVERTED_FIELD 0x4465
|
|
#define CAR_mmCUR_CONTROL 0x1a66
|
|
#define CAR_mmDCP0_CUR_CONTROL 0x1a66
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#define CAR_mmDCP1_CUR_CONTROL 0x1c66
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#define CAR_mmDCP2_CUR_CONTROL 0x1e66
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#define CAR_mmDCP3_CUR_CONTROL 0x4066
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#define CAR_mmDCP4_CUR_CONTROL 0x4266
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#define CAR_mmDCP5_CUR_CONTROL 0x4466
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#define CAR_mmCUR_SURFACE_ADDRESS 0x1a67
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#define CAR_mmDCP0_CUR_SURFACE_ADDRESS 0x1a67
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#define CAR_mmDCP1_CUR_SURFACE_ADDRESS 0x1c67
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#define CAR_mmDCP2_CUR_SURFACE_ADDRESS 0x1e67
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#define CAR_mmDCP3_CUR_SURFACE_ADDRESS 0x4067
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#define CAR_mmDCP4_CUR_SURFACE_ADDRESS 0x4267
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#define CAR_mmDCP5_CUR_SURFACE_ADDRESS 0x4467
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#define CAR_mmCUR_SIZE 0x1a68
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#define CAR_mmDCP0_CUR_SIZE 0x1a68
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#define CAR_mmDCP1_CUR_SIZE 0x1c68
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#define CAR_mmDCP2_CUR_SIZE 0x1e68
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#define CAR_mmDCP3_CUR_SIZE 0x4068
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#define CAR_mmDCP4_CUR_SIZE 0x4268
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#define CAR_mmDCP5_CUR_SIZE 0x4468
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#define CAR_mmCUR_SURFACE_ADDRESS_HIGH 0x1a69
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#define CAR_mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1a69
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#define CAR_mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1c69
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#define CAR_mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x1e69
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#define CAR_mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4069
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#define CAR_mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4269
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#define CAR_mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4469
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#define CAR_mmCUR_POSITION 0x1a6a
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#define CAR_mmDCP0_CUR_POSITION 0x1a6a
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#define CAR_mmDCP1_CUR_POSITION 0x1c6a
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#define CAR_mmDCP2_CUR_POSITION 0x1e6a
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#define CAR_mmDCP3_CUR_POSITION 0x406a
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#define CAR_mmDCP4_CUR_POSITION 0x426a
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#define CAR_mmDCP5_CUR_POSITION 0x446a
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#define CAR_mmCUR_HOT_SPOT 0x1a6b
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#define CAR_mmDCP0_CUR_HOT_SPOT 0x1a6b
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#define CAR_mmDCP1_CUR_HOT_SPOT 0x1c6b
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#define CAR_mmDCP2_CUR_HOT_SPOT 0x1e6b
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#define CAR_mmDCP3_CUR_HOT_SPOT 0x406b
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#define CAR_mmDCP4_CUR_HOT_SPOT 0x426b
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#define CAR_mmDCP5_CUR_HOT_SPOT 0x446b
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#define CAR_mmCUR_COLOR1 0x1a6c
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#define CAR_mmDCP0_CUR_COLOR1 0x1a6c
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#define CAR_mmDCP1_CUR_COLOR1 0x1c6c
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#define CAR_mmDCP2_CUR_COLOR1 0x1e6c
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#define CAR_mmDCP3_CUR_COLOR1 0x406c
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#define CAR_mmDCP4_CUR_COLOR1 0x426c
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#define CAR_mmDCP5_CUR_COLOR1 0x446c
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#define CAR_mmCUR_COLOR2 0x1a6d
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#define CAR_mmDCP0_CUR_COLOR2 0x1a6d
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#define CAR_mmDCP1_CUR_COLOR2 0x1c6d
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#define CAR_mmDCP2_CUR_COLOR2 0x1e6d
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#define CAR_mmDCP3_CUR_COLOR2 0x406d
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#define CAR_mmDCP4_CUR_COLOR2 0x426d
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#define CAR_mmDCP5_CUR_COLOR2 0x446d
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#define CAR_mmCUR_UPDATE 0x1a6e
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#define CAR_mmDCP0_CUR_UPDATE 0x1a6e
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#define CAR_mmDCP1_CUR_UPDATE 0x1c6e
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#define CAR_mmDCP2_CUR_UPDATE 0x1e6e
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#define CAR_mmDCP3_CUR_UPDATE 0x406e
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#define CAR_mmDCP4_CUR_UPDATE 0x426e
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#define CAR_mmDCP5_CUR_UPDATE 0x446e
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#define CAR_mmCUR_REQUEST_FILTER_CNTL 0x1a99
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#define CAR_mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1a99
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#define CAR_mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1c99
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#define CAR_mmDCP2_CUR_REQUEST_FILTER_CNTL 0x1e99
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#define CAR_mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4099
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#define CAR_mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4299
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#define CAR_mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4499
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#define CAR_mmCUR_STEREO_CONTROL 0x1a9a
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#define CAR_mmDCP0_CUR_STEREO_CONTROL 0x1a9a
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#define CAR_mmDCP1_CUR_STEREO_CONTROL 0x1c9a
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#define CAR_mmDCP2_CUR_STEREO_CONTROL 0x1e9a
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#define CAR_mmDCP3_CUR_STEREO_CONTROL 0x409a
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#define CAR_mmDCP4_CUR_STEREO_CONTROL 0x429a
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#define CAR_mmDCP5_CUR_STEREO_CONTROL 0x449a
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#define CAR_mmDC_LUT_RW_MODE 0x1a78
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#define CAR_mmDCP0_DC_LUT_RW_MODE 0x1a78
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#define CAR_mmDCP1_DC_LUT_RW_MODE 0x1c78
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#define CAR_mmDCP2_DC_LUT_RW_MODE 0x1e78
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#define CAR_mmDCP3_DC_LUT_RW_MODE 0x4078
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#define CAR_mmDCP4_DC_LUT_RW_MODE 0x4278
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#define CAR_mmDCP5_DC_LUT_RW_MODE 0x4478
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#define CAR_mmDC_LUT_RW_INDEX 0x1a79
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#define CAR_mmDCP0_DC_LUT_RW_INDEX 0x1a79
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#define CAR_mmDCP1_DC_LUT_RW_INDEX 0x1c79
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#define CAR_mmDCP2_DC_LUT_RW_INDEX 0x1e79
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#define CAR_mmDCP3_DC_LUT_RW_INDEX 0x4079
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#define CAR_mmDCP4_DC_LUT_RW_INDEX 0x4279
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#define CAR_mmDCP5_DC_LUT_RW_INDEX 0x4479
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#define CAR_mmDC_LUT_SEQ_COLOR 0x1a7a
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#define CAR_mmDCP0_DC_LUT_SEQ_COLOR 0x1a7a
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#define CAR_mmDCP1_DC_LUT_SEQ_COLOR 0x1c7a
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#define CAR_mmDCP2_DC_LUT_SEQ_COLOR 0x1e7a
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#define CAR_mmDCP3_DC_LUT_SEQ_COLOR 0x407a
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#define CAR_mmDCP4_DC_LUT_SEQ_COLOR 0x427a
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#define CAR_mmDCP5_DC_LUT_SEQ_COLOR 0x447a
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#define CAR_mmDC_LUT_PWL_DATA 0x1a7b
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#define CAR_mmDCP0_DC_LUT_PWL_DATA 0x1a7b
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#define CAR_mmDCP1_DC_LUT_PWL_DATA 0x1c7b
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#define CAR_mmDCP2_DC_LUT_PWL_DATA 0x1e7b
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#define CAR_mmDCP3_DC_LUT_PWL_DATA 0x407b
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#define CAR_mmDCP4_DC_LUT_PWL_DATA 0x427b
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#define CAR_mmDCP5_DC_LUT_PWL_DATA 0x447b
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#define CAR_mmDC_LUT_30_COLOR 0x1a7c
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#define CAR_mmDCP0_DC_LUT_30_COLOR 0x1a7c
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#define CAR_mmDCP1_DC_LUT_30_COLOR 0x1c7c
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#define CAR_mmDCP2_DC_LUT_30_COLOR 0x1e7c
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#define CAR_mmDCP3_DC_LUT_30_COLOR 0x407c
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#define CAR_mmDCP4_DC_LUT_30_COLOR 0x427c
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#define CAR_mmDCP5_DC_LUT_30_COLOR 0x447c
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#define CAR_mmDC_LUT_VGA_ACCESS_ENABLE 0x1a7d
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#define CAR_mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1a7d
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#define CAR_mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1c7d
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#define CAR_mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x1e7d
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#define CAR_mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x407d
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#define CAR_mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x427d
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#define CAR_mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x447d
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#define CAR_mmDC_LUT_WRITE_EN_MASK 0x1a7e
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#define CAR_mmDCP0_DC_LUT_WRITE_EN_MASK 0x1a7e
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#define CAR_mmDCP1_DC_LUT_WRITE_EN_MASK 0x1c7e
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#define CAR_mmDCP2_DC_LUT_WRITE_EN_MASK 0x1e7e
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#define CAR_mmDCP3_DC_LUT_WRITE_EN_MASK 0x407e
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#define CAR_mmDCP4_DC_LUT_WRITE_EN_MASK 0x427e
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#define CAR_mmDCP5_DC_LUT_WRITE_EN_MASK 0x447e
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#define CAR_mmDC_LUT_AUTOFILL 0x1a7f
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#define CAR_mmDCP0_DC_LUT_AUTOFILL 0x1a7f
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#define CAR_mmDCP1_DC_LUT_AUTOFILL 0x1c7f
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#define CAR_mmDCP2_DC_LUT_AUTOFILL 0x1e7f
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#define CAR_mmDCP3_DC_LUT_AUTOFILL 0x407f
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#define CAR_mmDCP4_DC_LUT_AUTOFILL 0x427f
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#define CAR_mmDCP5_DC_LUT_AUTOFILL 0x447f
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#define CAR_mmDC_LUT_CONTROL 0x1a80
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#define CAR_mmDCP0_DC_LUT_CONTROL 0x1a80
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#define CAR_mmDCP1_DC_LUT_CONTROL 0x1c80
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#define CAR_mmDCP2_DC_LUT_CONTROL 0x1e80
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#define CAR_mmDCP3_DC_LUT_CONTROL 0x4080
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#define CAR_mmDCP4_DC_LUT_CONTROL 0x4280
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#define CAR_mmDCP5_DC_LUT_CONTROL 0x4480
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#define CAR_mmDC_LUT_BLACK_OFFSET_BLUE 0x1a81
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#define CAR_mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1a81
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#define CAR_mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1c81
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#define CAR_mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x1e81
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#define CAR_mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4081
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#define CAR_mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4281
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#define CAR_mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4481
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#define CAR_mmDC_LUT_BLACK_OFFSET_GREEN 0x1a82
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#define CAR_mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1a82
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#define CAR_mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1c82
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#define CAR_mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x1e82
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#define CAR_mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4082
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#define CAR_mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4282
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#define CAR_mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4482
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#define CAR_mmDC_LUT_BLACK_OFFSET_RED 0x1a83
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#define CAR_mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1a83
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#define CAR_mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1c83
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#define CAR_mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x1e83
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#define CAR_mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4083
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#define CAR_mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4283
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#define CAR_mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4483
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#define CAR_mmDC_LUT_WHITE_OFFSET_BLUE 0x1a84
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#define CAR_mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1a84
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#define CAR_mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1c84
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#define CAR_mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x1e84
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#define CAR_mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4084
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#define CAR_mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4284
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#define CAR_mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4484
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#define CAR_mmDC_LUT_WHITE_OFFSET_GREEN 0x1a85
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#define CAR_mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1a85
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#define CAR_mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1c85
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#define CAR_mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x1e85
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#define CAR_mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4085
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#define CAR_mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4285
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#define CAR_mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4485
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#define CAR_mmDC_LUT_WHITE_OFFSET_RED 0x1a86
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#define CAR_mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1a86
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#define CAR_mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1c86
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#define CAR_mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x1e86
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#define CAR_mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4086
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#define CAR_mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4286
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#define CAR_mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4486
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#define CAR_mmDCP_CRC_CONTROL 0x1a87
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#define CAR_mmDCP0_DCP_CRC_CONTROL 0x1a87
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#define CAR_mmDCP1_DCP_CRC_CONTROL 0x1c87
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#define CAR_mmDCP2_DCP_CRC_CONTROL 0x1e87
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#define CAR_mmDCP3_DCP_CRC_CONTROL 0x4087
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#define CAR_mmDCP4_DCP_CRC_CONTROL 0x4287
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#define CAR_mmDCP5_DCP_CRC_CONTROL 0x4487
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#define CAR_mmDCP_CRC_MASK 0x1a88
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#define CAR_mmDCP0_DCP_CRC_MASK 0x1a88
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#define CAR_mmDCP1_DCP_CRC_MASK 0x1c88
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#define CAR_mmDCP2_DCP_CRC_MASK 0x1e88
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#define CAR_mmDCP3_DCP_CRC_MASK 0x4088
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#define CAR_mmDCP4_DCP_CRC_MASK 0x4288
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#define CAR_mmDCP5_DCP_CRC_MASK 0x4488
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#define CAR_mmDCP_CRC_CURRENT 0x1a89
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#define CAR_mmDCP0_DCP_CRC_CURRENT 0x1a89
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#define CAR_mmDCP1_DCP_CRC_CURRENT 0x1c89
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#define CAR_mmDCP2_DCP_CRC_CURRENT 0x1e89
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#define CAR_mmDCP3_DCP_CRC_CURRENT 0x4089
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#define CAR_mmDCP4_DCP_CRC_CURRENT 0x4289
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#define CAR_mmDCP5_DCP_CRC_CURRENT 0x4489
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#define CAR_mmDVMM_PTE_CONTROL 0x1a8a
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#define CAR_mmDCP0_DVMM_PTE_CONTROL 0x1a8a
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#define CAR_mmDCP1_DVMM_PTE_CONTROL 0x1c8a
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#define CAR_mmDCP2_DVMM_PTE_CONTROL 0x1e8a
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#define CAR_mmDCP3_DVMM_PTE_CONTROL 0x408a
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#define CAR_mmDCP4_DVMM_PTE_CONTROL 0x428a
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#define CAR_mmDCP5_DVMM_PTE_CONTROL 0x448a
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#define CAR_mmDCP_CRC_LAST 0x1a8b
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#define CAR_mmDCP0_DCP_CRC_LAST 0x1a8b
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#define CAR_mmDCP1_DCP_CRC_LAST 0x1c8b
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#define CAR_mmDCP2_DCP_CRC_LAST 0x1e8b
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#define CAR_mmDCP3_DCP_CRC_LAST 0x408b
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#define CAR_mmDCP4_DCP_CRC_LAST 0x428b
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#define CAR_mmDCP5_DCP_CRC_LAST 0x448b
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#define CAR_mmDVMM_PTE_ARB_CONTROL 0x1a8c
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#define CAR_mmDCP0_DVMM_PTE_ARB_CONTROL 0x1a8c
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#define CAR_mmDCP1_DVMM_PTE_ARB_CONTROL 0x1c8c
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#define CAR_mmDCP2_DVMM_PTE_ARB_CONTROL 0x1e8c
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#define CAR_mmDCP3_DVMM_PTE_ARB_CONTROL 0x408c
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#define CAR_mmDCP4_DVMM_PTE_ARB_CONTROL 0x428c
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#define CAR_mmDCP5_DVMM_PTE_ARB_CONTROL 0x448c
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#define CAR_mmDCP_DEBUG 0x1a8d
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#define CAR_mmDCP0_DCP_DEBUG 0x1a8d
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#define CAR_mmDCP1_DCP_DEBUG 0x1c8d
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#define CAR_mmDCP2_DCP_DEBUG 0x1e8d
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#define CAR_mmDCP3_DCP_DEBUG 0x408d
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#define CAR_mmDCP4_DCP_DEBUG 0x428d
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#define CAR_mmDCP5_DCP_DEBUG 0x448d
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#define CAR_mmGRPH_FLIP_RATE_CNTL 0x1a8e
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#define CAR_mmDCP0_GRPH_FLIP_RATE_CNTL 0x1a8e
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#define CAR_mmDCP1_GRPH_FLIP_RATE_CNTL 0x1c8e
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#define CAR_mmDCP2_GRPH_FLIP_RATE_CNTL 0x1e8e
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#define CAR_mmDCP3_GRPH_FLIP_RATE_CNTL 0x408e
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#define CAR_mmDCP4_GRPH_FLIP_RATE_CNTL 0x428e
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#define CAR_mmDCP5_GRPH_FLIP_RATE_CNTL 0x448e
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#define CAR_mmDCP_GSL_CONTROL 0x1a90
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#define CAR_mmDCP0_DCP_GSL_CONTROL 0x1a90
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#define CAR_mmDCP1_DCP_GSL_CONTROL 0x1c90
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#define CAR_mmDCP2_DCP_GSL_CONTROL 0x1e90
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#define CAR_mmDCP3_DCP_GSL_CONTROL 0x4090
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#define CAR_mmDCP4_DCP_GSL_CONTROL 0x4290
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#define CAR_mmDCP5_DCP_GSL_CONTROL 0x4490
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#define CAR_mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91
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#define CAR_mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1a91
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#define CAR_mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1c91
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#define CAR_mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1e91
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#define CAR_mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091
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#define CAR_mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4291
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#define CAR_mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4491
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#define CAR_mmDCP_DEBUG_SG 0x1a92
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#define CAR_mmDCP0_DCP_DEBUG_SG 0x1a92
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#define CAR_mmDCP1_DCP_DEBUG_SG 0x1c92
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#define CAR_mmDCP2_DCP_DEBUG_SG 0x1e92
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#define CAR_mmDCP3_DCP_DEBUG_SG 0x4092
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#define CAR_mmDCP4_DCP_DEBUG_SG 0x4292
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#define CAR_mmDCP5_DCP_DEBUG_SG 0x4492
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#define CAR_mmDCP_DEBUG_SG2 0x1a94
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#define CAR_mmDCP0_DCP_DEBUG_SG2 0x1a94
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#define CAR_mmDCP1_DCP_DEBUG_SG2 0x1c94
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#define CAR_mmDCP2_DCP_DEBUG_SG2 0x1e94
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#define CAR_mmDCP3_DCP_DEBUG_SG2 0x4094
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#define CAR_mmDCP4_DCP_DEBUG_SG2 0x4294
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#define CAR_mmDCP5_DCP_DEBUG_SG2 0x4494
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#define CAR_mmDCP_DVMM_DEBUG 0x1a93
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#define CAR_mmDCP0_DCP_DVMM_DEBUG 0x1a93
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#define CAR_mmDCP1_DCP_DVMM_DEBUG 0x1c93
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#define CAR_mmDCP2_DCP_DVMM_DEBUG 0x1e93
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#define CAR_mmDCP3_DCP_DVMM_DEBUG 0x4093
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#define CAR_mmDCP4_DCP_DVMM_DEBUG 0x4293
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#define CAR_mmDCP5_DCP_DVMM_DEBUG 0x4493
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#define CAR_mmDCP_TEST_DEBUG_INDEX 0x1a95
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#define CAR_mmDCP0_DCP_TEST_DEBUG_INDEX 0x1a95
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#define CAR_mmDCP1_DCP_TEST_DEBUG_INDEX 0x1c95
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#define CAR_mmDCP2_DCP_TEST_DEBUG_INDEX 0x1e95
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#define CAR_mmDCP3_DCP_TEST_DEBUG_INDEX 0x4095
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#define CAR_mmDCP4_DCP_TEST_DEBUG_INDEX 0x4295
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#define CAR_mmDCP5_DCP_TEST_DEBUG_INDEX 0x4495
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#define CAR_mmDCP_TEST_DEBUG_DATA 0x1a96
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#define CAR_mmDCP0_DCP_TEST_DEBUG_DATA 0x1a96
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#define CAR_mmDCP1_DCP_TEST_DEBUG_DATA 0x1c96
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#define CAR_mmDCP2_DCP_TEST_DEBUG_DATA 0x1e96
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#define CAR_mmDCP3_DCP_TEST_DEBUG_DATA 0x4096
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#define CAR_mmDCP4_DCP_TEST_DEBUG_DATA 0x4296
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#define CAR_mmDCP5_DCP_TEST_DEBUG_DATA 0x4496
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#define CAR_mmGRPH_STEREOSYNC_FLIP 0x1a97
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#define CAR_mmDCP0_GRPH_STEREOSYNC_FLIP 0x1a97
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#define CAR_mmDCP1_GRPH_STEREOSYNC_FLIP 0x1c97
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#define CAR_mmDCP2_GRPH_STEREOSYNC_FLIP 0x1e97
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#define CAR_mmDCP3_GRPH_STEREOSYNC_FLIP 0x4097
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#define CAR_mmDCP4_GRPH_STEREOSYNC_FLIP 0x4297
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#define CAR_mmDCP5_GRPH_STEREOSYNC_FLIP 0x4497
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#define CAR_mmDCP_DEBUG2 0x1a98
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#define CAR_mmDCP0_DCP_DEBUG2 0x1a98
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#define CAR_mmDCP1_DCP_DEBUG2 0x1c98
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#define CAR_mmDCP2_DCP_DEBUG2 0x1e98
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#define CAR_mmDCP3_DCP_DEBUG2 0x4098
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#define CAR_mmDCP4_DCP_DEBUG2 0x4298
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#define CAR_mmDCP5_DCP_DEBUG2 0x4498
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#define CAR_mmHW_ROTATION 0x1a9e
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#define CAR_mmDCP0_HW_ROTATION 0x1a9e
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#define CAR_mmDCP1_HW_ROTATION 0x1c9e
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#define CAR_mmDCP2_HW_ROTATION 0x1e9e
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#define CAR_mmDCP3_HW_ROTATION 0x409e
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#define CAR_mmDCP4_HW_ROTATION 0x429e
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#define CAR_mmDCP5_HW_ROTATION 0x449e
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#define CAR_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f
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#define CAR_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1a9f
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#define CAR_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1c9f
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#define CAR_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x1e9f
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#define CAR_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x409f
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#define CAR_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x429f
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#define CAR_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL 0x449f
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#define CAR_mmREGAMMA_CONTROL 0x1aa0
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#define CAR_mmDCP0_REGAMMA_CONTROL 0x1aa0
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#define CAR_mmDCP1_REGAMMA_CONTROL 0x1ca0
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#define CAR_mmDCP2_REGAMMA_CONTROL 0x1ea0
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#define CAR_mmDCP3_REGAMMA_CONTROL 0x40a0
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#define CAR_mmDCP4_REGAMMA_CONTROL 0x42a0
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#define CAR_mmDCP5_REGAMMA_CONTROL 0x44a0
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#define CAR_mmREGAMMA_LUT_INDEX 0x1aa1
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#define CAR_mmDCP0_REGAMMA_LUT_INDEX 0x1aa1
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#define CAR_mmDCP1_REGAMMA_LUT_INDEX 0x1ca1
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#define CAR_mmDCP2_REGAMMA_LUT_INDEX 0x1ea1
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#define CAR_mmDCP3_REGAMMA_LUT_INDEX 0x40a1
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#define CAR_mmDCP4_REGAMMA_LUT_INDEX 0x42a1
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#define CAR_mmDCP5_REGAMMA_LUT_INDEX 0x44a1
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#define CAR_mmREGAMMA_LUT_DATA 0x1aa2
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#define CAR_mmDCP0_REGAMMA_LUT_DATA 0x1aa2
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#define CAR_mmDCP1_REGAMMA_LUT_DATA 0x1ca2
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#define CAR_mmDCP2_REGAMMA_LUT_DATA 0x1ea2
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#define CAR_mmDCP3_REGAMMA_LUT_DATA 0x40a2
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#define CAR_mmDCP4_REGAMMA_LUT_DATA 0x42a2
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#define CAR_mmDCP5_REGAMMA_LUT_DATA 0x44a2
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#define CAR_mmREGAMMA_LUT_WRITE_EN_MASK 0x1aa3
|
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#define CAR_mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1aa3
|
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#define CAR_mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1ca3
|
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#define CAR_mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x1ea3
|
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#define CAR_mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x40a3
|
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#define CAR_mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x42a3
|
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#define CAR_mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x44a3
|
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#define CAR_mmREGAMMA_CNTLA_START_CNTL 0x1aa4
|
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#define CAR_mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1aa4
|
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#define CAR_mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1ca4
|
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#define CAR_mmDCP2_REGAMMA_CNTLA_START_CNTL 0x1ea4
|
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#define CAR_mmDCP3_REGAMMA_CNTLA_START_CNTL 0x40a4
|
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#define CAR_mmDCP4_REGAMMA_CNTLA_START_CNTL 0x42a4
|
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#define CAR_mmDCP5_REGAMMA_CNTLA_START_CNTL 0x44a4
|
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#define CAR_mmREGAMMA_CNTLA_SLOPE_CNTL 0x1aa5
|
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#define CAR_mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1aa5
|
|
#define CAR_mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1ca5
|
|
#define CAR_mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x1ea5
|
|
#define CAR_mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x40a5
|
|
#define CAR_mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x42a5
|
|
#define CAR_mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x44a5
|
|
#define CAR_mmREGAMMA_CNTLA_END_CNTL1 0x1aa6
|
|
#define CAR_mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1aa6
|
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#define CAR_mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1ca6
|
|
#define CAR_mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x1ea6
|
|
#define CAR_mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x40a6
|
|
#define CAR_mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x42a6
|
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#define CAR_mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x44a6
|
|
#define CAR_mmREGAMMA_CNTLA_END_CNTL2 0x1aa7
|
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#define CAR_mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1aa7
|
|
#define CAR_mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1ca7
|
|
#define CAR_mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x1ea7
|
|
#define CAR_mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x40a7
|
|
#define CAR_mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x42a7
|
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#define CAR_mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x44a7
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#define CAR_mmREGAMMA_CNTLA_REGION_0_1 0x1aa8
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|
#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1aa8
|
|
#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1ca8
|
|
#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x1ea8
|
|
#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x40a8
|
|
#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x42a8
|
|
#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x44a8
|
|
#define CAR_mmREGAMMA_CNTLA_REGION_2_3 0x1aa9
|
|
#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1aa9
|
|
#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1ca9
|
|
#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x1ea9
|
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#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x40a9
|
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#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x42a9
|
|
#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x44a9
|
|
#define CAR_mmREGAMMA_CNTLA_REGION_4_5 0x1aaa
|
|
#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1aaa
|
|
#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1caa
|
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#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x1eaa
|
|
#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x40aa
|
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#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x42aa
|
|
#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x44aa
|
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#define CAR_mmREGAMMA_CNTLA_REGION_6_7 0x1aab
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#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1aab
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#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1cab
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#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x1eab
|
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#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x40ab
|
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#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x42ab
|
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#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x44ab
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#define CAR_mmREGAMMA_CNTLA_REGION_8_9 0x1aac
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#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1aac
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#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1cac
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#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x1eac
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#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x40ac
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#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x42ac
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#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x44ac
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#define CAR_mmREGAMMA_CNTLA_REGION_10_11 0x1aad
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#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1aad
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#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1cad
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#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x1ead
|
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#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x40ad
|
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#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x42ad
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#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x44ad
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#define CAR_mmREGAMMA_CNTLA_REGION_12_13 0x1aae
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#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1aae
|
|
#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1cae
|
|
#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x1eae
|
|
#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x40ae
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|
#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x42ae
|
|
#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x44ae
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|
#define CAR_mmREGAMMA_CNTLA_REGION_14_15 0x1aaf
|
|
#define CAR_mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1aaf
|
|
#define CAR_mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1caf
|
|
#define CAR_mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x1eaf
|
|
#define CAR_mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x40af
|
|
#define CAR_mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x42af
|
|
#define CAR_mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x44af
|
|
#define CAR_mmREGAMMA_CNTLB_START_CNTL 0x1ab0
|
|
#define CAR_mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1ab0
|
|
#define CAR_mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1cb0
|
|
#define CAR_mmDCP2_REGAMMA_CNTLB_START_CNTL 0x1eb0
|
|
#define CAR_mmDCP3_REGAMMA_CNTLB_START_CNTL 0x40b0
|
|
#define CAR_mmDCP4_REGAMMA_CNTLB_START_CNTL 0x42b0
|
|
#define CAR_mmDCP5_REGAMMA_CNTLB_START_CNTL 0x44b0
|
|
#define CAR_mmREGAMMA_CNTLB_SLOPE_CNTL 0x1ab1
|
|
#define CAR_mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1ab1
|
|
#define CAR_mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1cb1
|
|
#define CAR_mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x1eb1
|
|
#define CAR_mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x40b1
|
|
#define CAR_mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x42b1
|
|
#define CAR_mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x44b1
|
|
#define CAR_mmREGAMMA_CNTLB_END_CNTL1 0x1ab2
|
|
#define CAR_mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1ab2
|
|
#define CAR_mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1cb2
|
|
#define CAR_mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x1eb2
|
|
#define CAR_mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x40b2
|
|
#define CAR_mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x42b2
|
|
#define CAR_mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x44b2
|
|
#define CAR_mmREGAMMA_CNTLB_END_CNTL2 0x1ab3
|
|
#define CAR_mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1ab3
|
|
#define CAR_mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1cb3
|
|
#define CAR_mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x1eb3
|
|
#define CAR_mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x40b3
|
|
#define CAR_mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x42b3
|
|
#define CAR_mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x44b3
|
|
#define CAR_mmREGAMMA_CNTLB_REGION_0_1 0x1ab4
|
|
#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1ab4
|
|
#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1cb4
|
|
#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x1eb4
|
|
#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x40b4
|
|
#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x42b4
|
|
#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x44b4
|
|
#define CAR_mmREGAMMA_CNTLB_REGION_2_3 0x1ab5
|
|
#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1ab5
|
|
#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1cb5
|
|
#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x1eb5
|
|
#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x40b5
|
|
#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x42b5
|
|
#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x44b5
|
|
#define CAR_mmREGAMMA_CNTLB_REGION_4_5 0x1ab6
|
|
#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1ab6
|
|
#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1cb6
|
|
#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x1eb6
|
|
#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x40b6
|
|
#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x42b6
|
|
#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x44b6
|
|
#define CAR_mmREGAMMA_CNTLB_REGION_6_7 0x1ab7
|
|
#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1ab7
|
|
#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1cb7
|
|
#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x1eb7
|
|
#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x40b7
|
|
#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x42b7
|
|
#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x44b7
|
|
#define CAR_mmREGAMMA_CNTLB_REGION_8_9 0x1ab8
|
|
#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1ab8
|
|
#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1cb8
|
|
#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x1eb8
|
|
#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x40b8
|
|
#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x42b8
|
|
#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x44b8
|
|
#define CAR_mmREGAMMA_CNTLB_REGION_10_11 0x1ab9
|
|
#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1ab9
|
|
#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1cb9
|
|
#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x1eb9
|
|
#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x40b9
|
|
#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x42b9
|
|
#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x44b9
|
|
#define CAR_mmREGAMMA_CNTLB_REGION_12_13 0x1aba
|
|
#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1aba
|
|
#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1cba
|
|
#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x1eba
|
|
#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x40ba
|
|
#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x42ba
|
|
#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x44ba
|
|
#define CAR_mmREGAMMA_CNTLB_REGION_14_15 0x1abb
|
|
#define CAR_mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1abb
|
|
#define CAR_mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1cbb
|
|
#define CAR_mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x1ebb
|
|
#define CAR_mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x40bb
|
|
#define CAR_mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x42bb
|
|
#define CAR_mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x44bb
|
|
#define CAR_mmALPHA_CONTROL 0x1abc
|
|
#define CAR_mmDCP0_ALPHA_CONTROL 0x1abc
|
|
#define CAR_mmDCP1_ALPHA_CONTROL 0x1cbc
|
|
#define CAR_mmDCP2_ALPHA_CONTROL 0x1ebc
|
|
#define CAR_mmDCP3_ALPHA_CONTROL 0x40bc
|
|
#define CAR_mmDCP4_ALPHA_CONTROL 0x42bc
|
|
#define CAR_mmDCP5_ALPHA_CONTROL 0x44bc
|
|
#define CAR_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd
|
|
#define CAR_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1abd
|
|
#define CAR_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1cbd
|
|
#define CAR_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x1ebd
|
|
#define CAR_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x40bd
|
|
#define CAR_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x42bd
|
|
#define CAR_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS 0x44bd
|
|
#define CAR_mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe
|
|
#define CAR_mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1abe
|
|
#define CAR_mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1cbe
|
|
#define CAR_mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x1ebe
|
|
#define CAR_mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x40be
|
|
#define CAR_mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x42be
|
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#define CAR_mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH 0x44be
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#define CAR_mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf
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#define CAR_mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1abf
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#define CAR_mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1cbf
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#define CAR_mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x1ebf
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#define CAR_mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x40bf
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#define CAR_mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x42bf
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#define CAR_mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS 0x44bf
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#define CAR_mmGRPH_SURFACE_COUNTER_CONTROL 0x1a0f
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#define CAR_mmDCP0_GRPH_SURFACE_COUNTER_CONTROL 0x1a0f
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#define CAR_mmDCP1_GRPH_SURFACE_COUNTER_CONTROL 0x1c0f
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#define CAR_mmDCP2_GRPH_SURFACE_COUNTER_CONTROL 0x1e0f
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#define CAR_mmDCP3_GRPH_SURFACE_COUNTER_CONTROL 0x400f
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#define CAR_mmDCP4_GRPH_SURFACE_COUNTER_CONTROL 0x420f
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#define CAR_mmDCP5_GRPH_SURFACE_COUNTER_CONTROL 0x440f
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#define CAR_mmGRPH_SURFACE_COUNTER_OUTPUT 0x1a1d
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#define CAR_mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT 0x1a1d
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#define CAR_mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT 0x1c1d
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#define CAR_mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT 0x1e1d
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#define CAR_mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT 0x401d
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#define CAR_mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT 0x421d
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#define CAR_mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT 0x441d
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#define CAR_mmDIG_FE_CNTL 0x4a00
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#define CAR_mmDIG0_DIG_FE_CNTL 0x4a00
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#define CAR_mmDIG1_DIG_FE_CNTL 0x4b00
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#define CAR_mmDIG2_DIG_FE_CNTL 0x4c00
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#define CAR_mmDIG3_DIG_FE_CNTL 0x4d00
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#define CAR_mmDIG4_DIG_FE_CNTL 0x4e00
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#define CAR_mmDIG5_DIG_FE_CNTL 0x4f00
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#define CAR_mmDIG6_DIG_FE_CNTL 0x5400
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#define CAR_mmDIG7_DIG_FE_CNTL 0x5600
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#define CAR_mmDIG8_DIG_FE_CNTL 0x5700
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#define CAR_mmDIG_OUTPUT_CRC_CNTL 0x4a01
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#define CAR_mmDIG0_DIG_OUTPUT_CRC_CNTL 0x4a01
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#define CAR_mmDIG1_DIG_OUTPUT_CRC_CNTL 0x4b01
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#define CAR_mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4c01
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#define CAR_mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4d01
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#define CAR_mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4e01
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#define CAR_mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4f01
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#define CAR_mmDIG6_DIG_OUTPUT_CRC_CNTL 0x5401
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#define CAR_mmDIG7_DIG_OUTPUT_CRC_CNTL 0x5601
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#define CAR_mmDIG8_DIG_OUTPUT_CRC_CNTL 0x5701
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#define CAR_mmDIG_OUTPUT_CRC_RESULT 0x4a02
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#define CAR_mmDIG0_DIG_OUTPUT_CRC_RESULT 0x4a02
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#define CAR_mmDIG1_DIG_OUTPUT_CRC_RESULT 0x4b02
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#define CAR_mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4c02
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#define CAR_mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4d02
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#define CAR_mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4e02
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#define CAR_mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4f02
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#define CAR_mmDIG6_DIG_OUTPUT_CRC_RESULT 0x5402
|
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#define CAR_mmDIG7_DIG_OUTPUT_CRC_RESULT 0x5602
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#define CAR_mmDIG8_DIG_OUTPUT_CRC_RESULT 0x5702
|
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#define CAR_mmDIG_CLOCK_PATTERN 0x4a03
|
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#define CAR_mmDIG0_DIG_CLOCK_PATTERN 0x4a03
|
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#define CAR_mmDIG1_DIG_CLOCK_PATTERN 0x4b03
|
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#define CAR_mmDIG2_DIG_CLOCK_PATTERN 0x4c03
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#define CAR_mmDIG3_DIG_CLOCK_PATTERN 0x4d03
|
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#define CAR_mmDIG4_DIG_CLOCK_PATTERN 0x4e03
|
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#define CAR_mmDIG5_DIG_CLOCK_PATTERN 0x4f03
|
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#define CAR_mmDIG6_DIG_CLOCK_PATTERN 0x5403
|
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#define CAR_mmDIG7_DIG_CLOCK_PATTERN 0x5603
|
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#define CAR_mmDIG8_DIG_CLOCK_PATTERN 0x5703
|
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#define CAR_mmDIG_TEST_PATTERN 0x4a04
|
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#define CAR_mmDIG0_DIG_TEST_PATTERN 0x4a04
|
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#define CAR_mmDIG1_DIG_TEST_PATTERN 0x4b04
|
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#define CAR_mmDIG2_DIG_TEST_PATTERN 0x4c04
|
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#define CAR_mmDIG3_DIG_TEST_PATTERN 0x4d04
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#define CAR_mmDIG4_DIG_TEST_PATTERN 0x4e04
|
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#define CAR_mmDIG5_DIG_TEST_PATTERN 0x4f04
|
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#define CAR_mmDIG6_DIG_TEST_PATTERN 0x5404
|
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#define CAR_mmDIG7_DIG_TEST_PATTERN 0x5604
|
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#define CAR_mmDIG8_DIG_TEST_PATTERN 0x5704
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#define CAR_mmDIG_RANDOM_PATTERN_SEED 0x4a05
|
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#define CAR_mmDIG0_DIG_RANDOM_PATTERN_SEED 0x4a05
|
|
#define CAR_mmDIG1_DIG_RANDOM_PATTERN_SEED 0x4b05
|
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#define CAR_mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4c05
|
|
#define CAR_mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4d05
|
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#define CAR_mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4e05
|
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#define CAR_mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4f05
|
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#define CAR_mmDIG6_DIG_RANDOM_PATTERN_SEED 0x5405
|
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#define CAR_mmDIG7_DIG_RANDOM_PATTERN_SEED 0x5605
|
|
#define CAR_mmDIG8_DIG_RANDOM_PATTERN_SEED 0x5705
|
|
#define CAR_mmDIG_FIFO_STATUS 0x4a06
|
|
#define CAR_mmDIG0_DIG_FIFO_STATUS 0x4a06
|
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#define CAR_mmDIG1_DIG_FIFO_STATUS 0x4b06
|
|
#define CAR_mmDIG2_DIG_FIFO_STATUS 0x4c06
|
|
#define CAR_mmDIG3_DIG_FIFO_STATUS 0x4d06
|
|
#define CAR_mmDIG4_DIG_FIFO_STATUS 0x4e06
|
|
#define CAR_mmDIG5_DIG_FIFO_STATUS 0x4f06
|
|
#define CAR_mmDIG6_DIG_FIFO_STATUS 0x5406
|
|
#define CAR_mmDIG7_DIG_FIFO_STATUS 0x5606
|
|
#define CAR_mmDIG8_DIG_FIFO_STATUS 0x5706
|
|
#define CAR_mmDIG_DISPCLK_SWITCH_CNTL 0x4a07
|
|
#define CAR_mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x4a07
|
|
#define CAR_mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x4b07
|
|
#define CAR_mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4c07
|
|
#define CAR_mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4d07
|
|
#define CAR_mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4e07
|
|
#define CAR_mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4f07
|
|
#define CAR_mmDIG6_DIG_DISPCLK_SWITCH_CNTL 0x5407
|
|
#define CAR_mmDIG7_DIG_DISPCLK_SWITCH_CNTL 0x5607
|
|
#define CAR_mmDIG8_DIG_DISPCLK_SWITCH_CNTL 0x5707
|
|
#define CAR_mmDIG_DISPCLK_SWITCH_STATUS 0x4a08
|
|
#define CAR_mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x4a08
|
|
#define CAR_mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x4b08
|
|
#define CAR_mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4c08
|
|
#define CAR_mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4d08
|
|
#define CAR_mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4e08
|
|
#define CAR_mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4f08
|
|
#define CAR_mmDIG6_DIG_DISPCLK_SWITCH_STATUS 0x5408
|
|
#define CAR_mmDIG7_DIG_DISPCLK_SWITCH_STATUS 0x5608
|
|
#define CAR_mmDIG8_DIG_DISPCLK_SWITCH_STATUS 0x5708
|
|
#define CAR_mmHDMI_CONTROL 0x4a09
|
|
#define CAR_mmDIG0_HDMI_CONTROL 0x4a09
|
|
#define CAR_mmDIG1_HDMI_CONTROL 0x4b09
|
|
#define CAR_mmDIG2_HDMI_CONTROL 0x4c09
|
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#define CAR_mmDIG3_HDMI_CONTROL 0x4d09
|
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#define CAR_mmDIG4_HDMI_CONTROL 0x4e09
|
|
#define CAR_mmDIG5_HDMI_CONTROL 0x4f09
|
|
#define CAR_mmDIG6_HDMI_CONTROL 0x5409
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#define CAR_mmDIG7_HDMI_CONTROL 0x5609
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#define CAR_mmDIG8_HDMI_CONTROL 0x5709
|
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#define CAR_mmHDMI_STATUS 0x4a0a
|
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#define CAR_mmDIG0_HDMI_STATUS 0x4a0a
|
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#define CAR_mmDIG1_HDMI_STATUS 0x4b0a
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#define CAR_mmDIG2_HDMI_STATUS 0x4c0a
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#define CAR_mmDIG3_HDMI_STATUS 0x4d0a
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#define CAR_mmDIG4_HDMI_STATUS 0x4e0a
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#define CAR_mmDIG5_HDMI_STATUS 0x4f0a
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#define CAR_mmDIG6_HDMI_STATUS 0x540a
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#define CAR_mmDIG7_HDMI_STATUS 0x560a
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#define CAR_mmDIG8_HDMI_STATUS 0x570a
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#define CAR_mmHDMI_AUDIO_PACKET_CONTROL 0x4a0b
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#define CAR_mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x4a0b
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#define CAR_mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x4b0b
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#define CAR_mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x4c0b
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#define CAR_mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x4d0b
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#define CAR_mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x4e0b
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#define CAR_mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4f0b
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#define CAR_mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x540b
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#define CAR_mmDIG7_HDMI_AUDIO_PACKET_CONTROL 0x560b
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#define CAR_mmDIG8_HDMI_AUDIO_PACKET_CONTROL 0x570b
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#define CAR_mmHDMI_ACR_PACKET_CONTROL 0x4a0c
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#define CAR_mmDIG0_HDMI_ACR_PACKET_CONTROL 0x4a0c
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#define CAR_mmDIG1_HDMI_ACR_PACKET_CONTROL 0x4b0c
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#define CAR_mmDIG2_HDMI_ACR_PACKET_CONTROL 0x4c0c
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#define CAR_mmDIG3_HDMI_ACR_PACKET_CONTROL 0x4d0c
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#define CAR_mmDIG4_HDMI_ACR_PACKET_CONTROL 0x4e0c
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#define CAR_mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4f0c
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#define CAR_mmDIG6_HDMI_ACR_PACKET_CONTROL 0x540c
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#define CAR_mmDIG7_HDMI_ACR_PACKET_CONTROL 0x560c
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#define CAR_mmDIG8_HDMI_ACR_PACKET_CONTROL 0x570c
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#define CAR_mmHDMI_VBI_PACKET_CONTROL 0x4a0d
|
|
#define CAR_mmDIG0_HDMI_VBI_PACKET_CONTROL 0x4a0d
|
|
#define CAR_mmDIG1_HDMI_VBI_PACKET_CONTROL 0x4b0d
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#define CAR_mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4c0d
|
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#define CAR_mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4d0d
|
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#define CAR_mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4e0d
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#define CAR_mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4f0d
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#define CAR_mmDIG6_HDMI_VBI_PACKET_CONTROL 0x540d
|
|
#define CAR_mmDIG7_HDMI_VBI_PACKET_CONTROL 0x560d
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|
#define CAR_mmDIG8_HDMI_VBI_PACKET_CONTROL 0x570d
|
|
#define CAR_mmHDMI_INFOFRAME_CONTROL0 0x4a0e
|
|
#define CAR_mmDIG0_HDMI_INFOFRAME_CONTROL0 0x4a0e
|
|
#define CAR_mmDIG1_HDMI_INFOFRAME_CONTROL0 0x4b0e
|
|
#define CAR_mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4c0e
|
|
#define CAR_mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4d0e
|
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#define CAR_mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4e0e
|
|
#define CAR_mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4f0e
|
|
#define CAR_mmDIG6_HDMI_INFOFRAME_CONTROL0 0x540e
|
|
#define CAR_mmDIG7_HDMI_INFOFRAME_CONTROL0 0x560e
|
|
#define CAR_mmDIG8_HDMI_INFOFRAME_CONTROL0 0x570e
|
|
#define CAR_mmHDMI_INFOFRAME_CONTROL1 0x4a0f
|
|
#define CAR_mmDIG0_HDMI_INFOFRAME_CONTROL1 0x4a0f
|
|
#define CAR_mmDIG1_HDMI_INFOFRAME_CONTROL1 0x4b0f
|
|
#define CAR_mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4c0f
|
|
#define CAR_mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4d0f
|
|
#define CAR_mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4e0f
|
|
#define CAR_mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4f0f
|
|
#define CAR_mmDIG6_HDMI_INFOFRAME_CONTROL1 0x540f
|
|
#define CAR_mmDIG7_HDMI_INFOFRAME_CONTROL1 0x560f
|
|
#define CAR_mmDIG8_HDMI_INFOFRAME_CONTROL1 0x570f
|
|
#define CAR_mmHDMI_GENERIC_PACKET_CONTROL0 0x4a10
|
|
#define CAR_mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x4a10
|
|
#define CAR_mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x4b10
|
|
#define CAR_mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4c10
|
|
#define CAR_mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4d10
|
|
#define CAR_mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4e10
|
|
#define CAR_mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4f10
|
|
#define CAR_mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x5410
|
|
#define CAR_mmDIG7_HDMI_GENERIC_PACKET_CONTROL0 0x5610
|
|
#define CAR_mmDIG8_HDMI_GENERIC_PACKET_CONTROL0 0x5710
|
|
#define CAR_mmAFMT_INTERRUPT_STATUS 0x4a11
|
|
#define CAR_mmDIG0_AFMT_INTERRUPT_STATUS 0x4a11
|
|
#define CAR_mmDIG1_AFMT_INTERRUPT_STATUS 0x4b11
|
|
#define CAR_mmDIG2_AFMT_INTERRUPT_STATUS 0x4c11
|
|
#define CAR_mmDIG3_AFMT_INTERRUPT_STATUS 0x4d11
|
|
#define CAR_mmDIG4_AFMT_INTERRUPT_STATUS 0x4e11
|
|
#define CAR_mmDIG5_AFMT_INTERRUPT_STATUS 0x4f11
|
|
#define CAR_mmDIG6_AFMT_INTERRUPT_STATUS 0x5411
|
|
#define CAR_mmDIG7_AFMT_INTERRUPT_STATUS 0x5611
|
|
#define CAR_mmDIG8_AFMT_INTERRUPT_STATUS 0x5711
|
|
#define CAR_mmHDMI_GC 0x4a13
|
|
#define CAR_mmDIG0_HDMI_GC 0x4a13
|
|
#define CAR_mmDIG1_HDMI_GC 0x4b13
|
|
#define CAR_mmDIG2_HDMI_GC 0x4c13
|
|
#define CAR_mmDIG3_HDMI_GC 0x4d13
|
|
#define CAR_mmDIG4_HDMI_GC 0x4e13
|
|
#define CAR_mmDIG5_HDMI_GC 0x4f13
|
|
#define CAR_mmDIG6_HDMI_GC 0x5413
|
|
#define CAR_mmDIG7_HDMI_GC 0x5613
|
|
#define CAR_mmDIG8_HDMI_GC 0x5713
|
|
#define CAR_mmAFMT_AUDIO_PACKET_CONTROL2 0x4a14
|
|
#define CAR_mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x4a14
|
|
#define CAR_mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x4b14
|
|
#define CAR_mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4c14
|
|
#define CAR_mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4d14
|
|
#define CAR_mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4e14
|
|
#define CAR_mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4f14
|
|
#define CAR_mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x5414
|
|
#define CAR_mmDIG7_AFMT_AUDIO_PACKET_CONTROL2 0x5614
|
|
#define CAR_mmDIG8_AFMT_AUDIO_PACKET_CONTROL2 0x5714
|
|
#define CAR_mmAFMT_ISRC1_0 0x4a15
|
|
#define CAR_mmDIG0_AFMT_ISRC1_0 0x4a15
|
|
#define CAR_mmDIG1_AFMT_ISRC1_0 0x4b15
|
|
#define CAR_mmDIG2_AFMT_ISRC1_0 0x4c15
|
|
#define CAR_mmDIG3_AFMT_ISRC1_0 0x4d15
|
|
#define CAR_mmDIG4_AFMT_ISRC1_0 0x4e15
|
|
#define CAR_mmDIG5_AFMT_ISRC1_0 0x4f15
|
|
#define CAR_mmDIG6_AFMT_ISRC1_0 0x5415
|
|
#define CAR_mmDIG7_AFMT_ISRC1_0 0x5615
|
|
#define CAR_mmDIG8_AFMT_ISRC1_0 0x5715
|
|
#define CAR_mmAFMT_ISRC1_1 0x4a16
|
|
#define CAR_mmDIG0_AFMT_ISRC1_1 0x4a16
|
|
#define CAR_mmDIG1_AFMT_ISRC1_1 0x4b16
|
|
#define CAR_mmDIG2_AFMT_ISRC1_1 0x4c16
|
|
#define CAR_mmDIG3_AFMT_ISRC1_1 0x4d16
|
|
#define CAR_mmDIG4_AFMT_ISRC1_1 0x4e16
|
|
#define CAR_mmDIG5_AFMT_ISRC1_1 0x4f16
|
|
#define CAR_mmDIG6_AFMT_ISRC1_1 0x5416
|
|
#define CAR_mmDIG7_AFMT_ISRC1_1 0x5616
|
|
#define CAR_mmDIG8_AFMT_ISRC1_1 0x5716
|
|
#define CAR_mmAFMT_ISRC1_2 0x4a17
|
|
#define CAR_mmDIG0_AFMT_ISRC1_2 0x4a17
|
|
#define CAR_mmDIG1_AFMT_ISRC1_2 0x4b17
|
|
#define CAR_mmDIG2_AFMT_ISRC1_2 0x4c17
|
|
#define CAR_mmDIG3_AFMT_ISRC1_2 0x4d17
|
|
#define CAR_mmDIG4_AFMT_ISRC1_2 0x4e17
|
|
#define CAR_mmDIG5_AFMT_ISRC1_2 0x4f17
|
|
#define CAR_mmDIG6_AFMT_ISRC1_2 0x5417
|
|
#define CAR_mmDIG7_AFMT_ISRC1_2 0x5617
|
|
#define CAR_mmDIG8_AFMT_ISRC1_2 0x5717
|
|
#define CAR_mmAFMT_ISRC1_3 0x4a18
|
|
#define CAR_mmDIG0_AFMT_ISRC1_3 0x4a18
|
|
#define CAR_mmDIG1_AFMT_ISRC1_3 0x4b18
|
|
#define CAR_mmDIG2_AFMT_ISRC1_3 0x4c18
|
|
#define CAR_mmDIG3_AFMT_ISRC1_3 0x4d18
|
|
#define CAR_mmDIG4_AFMT_ISRC1_3 0x4e18
|
|
#define CAR_mmDIG5_AFMT_ISRC1_3 0x4f18
|
|
#define CAR_mmDIG6_AFMT_ISRC1_3 0x5418
|
|
#define CAR_mmDIG7_AFMT_ISRC1_3 0x5618
|
|
#define CAR_mmDIG8_AFMT_ISRC1_3 0x5718
|
|
#define CAR_mmAFMT_ISRC1_4 0x4a19
|
|
#define CAR_mmDIG0_AFMT_ISRC1_4 0x4a19
|
|
#define CAR_mmDIG1_AFMT_ISRC1_4 0x4b19
|
|
#define CAR_mmDIG2_AFMT_ISRC1_4 0x4c19
|
|
#define CAR_mmDIG3_AFMT_ISRC1_4 0x4d19
|
|
#define CAR_mmDIG4_AFMT_ISRC1_4 0x4e19
|
|
#define CAR_mmDIG5_AFMT_ISRC1_4 0x4f19
|
|
#define CAR_mmDIG6_AFMT_ISRC1_4 0x5419
|
|
#define CAR_mmDIG7_AFMT_ISRC1_4 0x5619
|
|
#define CAR_mmDIG8_AFMT_ISRC1_4 0x5719
|
|
#define CAR_mmAFMT_ISRC2_0 0x4a1a
|
|
#define CAR_mmDIG0_AFMT_ISRC2_0 0x4a1a
|
|
#define CAR_mmDIG1_AFMT_ISRC2_0 0x4b1a
|
|
#define CAR_mmDIG2_AFMT_ISRC2_0 0x4c1a
|
|
#define CAR_mmDIG3_AFMT_ISRC2_0 0x4d1a
|
|
#define CAR_mmDIG4_AFMT_ISRC2_0 0x4e1a
|
|
#define CAR_mmDIG5_AFMT_ISRC2_0 0x4f1a
|
|
#define CAR_mmDIG6_AFMT_ISRC2_0 0x541a
|
|
#define CAR_mmDIG7_AFMT_ISRC2_0 0x561a
|
|
#define CAR_mmDIG8_AFMT_ISRC2_0 0x571a
|
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#define CAR_mmAFMT_ISRC2_1 0x4a1b
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#define CAR_mmDIG0_AFMT_ISRC2_1 0x4a1b
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#define CAR_mmDIG1_AFMT_ISRC2_1 0x4b1b
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#define CAR_mmDIG2_AFMT_ISRC2_1 0x4c1b
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#define CAR_mmDIG3_AFMT_ISRC2_1 0x4d1b
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#define CAR_mmDIG4_AFMT_ISRC2_1 0x4e1b
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#define CAR_mmDIG5_AFMT_ISRC2_1 0x4f1b
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#define CAR_mmDIG6_AFMT_ISRC2_1 0x541b
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#define CAR_mmDIG7_AFMT_ISRC2_1 0x561b
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#define CAR_mmDIG8_AFMT_ISRC2_1 0x571b
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#define CAR_mmAFMT_ISRC2_2 0x4a1c
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#define CAR_mmDIG0_AFMT_ISRC2_2 0x4a1c
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#define CAR_mmDIG1_AFMT_ISRC2_2 0x4b1c
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#define CAR_mmDIG2_AFMT_ISRC2_2 0x4c1c
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#define CAR_mmDIG3_AFMT_ISRC2_2 0x4d1c
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#define CAR_mmDIG4_AFMT_ISRC2_2 0x4e1c
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#define CAR_mmDIG5_AFMT_ISRC2_2 0x4f1c
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#define CAR_mmDIG6_AFMT_ISRC2_2 0x541c
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#define CAR_mmDIG7_AFMT_ISRC2_2 0x561c
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#define CAR_mmDIG8_AFMT_ISRC2_2 0x571c
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#define CAR_mmAFMT_ISRC2_3 0x4a1d
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#define CAR_mmDIG0_AFMT_ISRC2_3 0x4a1d
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#define CAR_mmDIG1_AFMT_ISRC2_3 0x4b1d
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#define CAR_mmDIG2_AFMT_ISRC2_3 0x4c1d
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#define CAR_mmDIG3_AFMT_ISRC2_3 0x4d1d
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#define CAR_mmDIG4_AFMT_ISRC2_3 0x4e1d
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#define CAR_mmDIG5_AFMT_ISRC2_3 0x4f1d
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#define CAR_mmDIG6_AFMT_ISRC2_3 0x541d
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#define CAR_mmDIG7_AFMT_ISRC2_3 0x561d
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#define CAR_mmDIG8_AFMT_ISRC2_3 0x571d
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#define CAR_mmAFMT_AVI_INFO0 0x4a1e
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#define CAR_mmDIG0_AFMT_AVI_INFO0 0x4a1e
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#define CAR_mmDIG1_AFMT_AVI_INFO0 0x4b1e
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#define CAR_mmDIG2_AFMT_AVI_INFO0 0x4c1e
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#define CAR_mmDIG3_AFMT_AVI_INFO0 0x4d1e
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#define CAR_mmDIG4_AFMT_AVI_INFO0 0x4e1e
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#define CAR_mmDIG5_AFMT_AVI_INFO0 0x4f1e
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#define CAR_mmDIG6_AFMT_AVI_INFO0 0x541e
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#define CAR_mmDIG7_AFMT_AVI_INFO0 0x561e
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#define CAR_mmDIG8_AFMT_AVI_INFO0 0x571e
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#define CAR_mmAFMT_AVI_INFO1 0x4a1f
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#define CAR_mmDIG0_AFMT_AVI_INFO1 0x4a1f
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#define CAR_mmDIG1_AFMT_AVI_INFO1 0x4b1f
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#define CAR_mmDIG2_AFMT_AVI_INFO1 0x4c1f
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#define CAR_mmDIG3_AFMT_AVI_INFO1 0x4d1f
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#define CAR_mmDIG4_AFMT_AVI_INFO1 0x4e1f
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#define CAR_mmDIG5_AFMT_AVI_INFO1 0x4f1f
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#define CAR_mmDIG6_AFMT_AVI_INFO1 0x541f
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#define CAR_mmDIG7_AFMT_AVI_INFO1 0x561f
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#define CAR_mmDIG8_AFMT_AVI_INFO1 0x571f
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#define CAR_mmAFMT_AVI_INFO2 0x4a20
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#define CAR_mmDIG0_AFMT_AVI_INFO2 0x4a20
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#define CAR_mmDIG1_AFMT_AVI_INFO2 0x4b20
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#define CAR_mmDIG2_AFMT_AVI_INFO2 0x4c20
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#define CAR_mmDIG3_AFMT_AVI_INFO2 0x4d20
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#define CAR_mmDIG4_AFMT_AVI_INFO2 0x4e20
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#define CAR_mmDIG5_AFMT_AVI_INFO2 0x4f20
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#define CAR_mmDIG6_AFMT_AVI_INFO2 0x5420
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#define CAR_mmDIG7_AFMT_AVI_INFO2 0x5620
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#define CAR_mmDIG8_AFMT_AVI_INFO2 0x5720
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#define CAR_mmAFMT_AVI_INFO3 0x4a21
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#define CAR_mmDIG0_AFMT_AVI_INFO3 0x4a21
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#define CAR_mmDIG1_AFMT_AVI_INFO3 0x4b21
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#define CAR_mmDIG2_AFMT_AVI_INFO3 0x4c21
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#define CAR_mmDIG3_AFMT_AVI_INFO3 0x4d21
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#define CAR_mmDIG4_AFMT_AVI_INFO3 0x4e21
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#define CAR_mmDIG5_AFMT_AVI_INFO3 0x4f21
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#define CAR_mmDIG6_AFMT_AVI_INFO3 0x5421
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#define CAR_mmDIG7_AFMT_AVI_INFO3 0x5621
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#define CAR_mmDIG8_AFMT_AVI_INFO3 0x5721
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#define CAR_mmAFMT_MPEG_INFO0 0x4a22
|
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#define CAR_mmDIG0_AFMT_MPEG_INFO0 0x4a22
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#define CAR_mmDIG1_AFMT_MPEG_INFO0 0x4b22
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#define CAR_mmDIG2_AFMT_MPEG_INFO0 0x4c22
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#define CAR_mmDIG3_AFMT_MPEG_INFO0 0x4d22
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#define CAR_mmDIG4_AFMT_MPEG_INFO0 0x4e22
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#define CAR_mmDIG5_AFMT_MPEG_INFO0 0x4f22
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#define CAR_mmDIG6_AFMT_MPEG_INFO0 0x5422
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#define CAR_mmDIG7_AFMT_MPEG_INFO0 0x5622
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#define CAR_mmDIG8_AFMT_MPEG_INFO0 0x5722
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#define CAR_mmAFMT_MPEG_INFO1 0x4a23
|
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#define CAR_mmDIG0_AFMT_MPEG_INFO1 0x4a23
|
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#define CAR_mmDIG1_AFMT_MPEG_INFO1 0x4b23
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#define CAR_mmDIG2_AFMT_MPEG_INFO1 0x4c23
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#define CAR_mmDIG3_AFMT_MPEG_INFO1 0x4d23
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#define CAR_mmDIG4_AFMT_MPEG_INFO1 0x4e23
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#define CAR_mmDIG5_AFMT_MPEG_INFO1 0x4f23
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#define CAR_mmDIG6_AFMT_MPEG_INFO1 0x5423
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|
#define CAR_mmDIG7_AFMT_MPEG_INFO1 0x5623
|
|
#define CAR_mmDIG8_AFMT_MPEG_INFO1 0x5723
|
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#define CAR_mmAFMT_GENERIC_HDR 0x4a24
|
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#define CAR_mmDIG0_AFMT_GENERIC_HDR 0x4a24
|
|
#define CAR_mmDIG1_AFMT_GENERIC_HDR 0x4b24
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#define CAR_mmDIG2_AFMT_GENERIC_HDR 0x4c24
|
|
#define CAR_mmDIG3_AFMT_GENERIC_HDR 0x4d24
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#define CAR_mmDIG4_AFMT_GENERIC_HDR 0x4e24
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#define CAR_mmDIG5_AFMT_GENERIC_HDR 0x4f24
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|
#define CAR_mmDIG6_AFMT_GENERIC_HDR 0x5424
|
|
#define CAR_mmDIG7_AFMT_GENERIC_HDR 0x5624
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|
#define CAR_mmDIG8_AFMT_GENERIC_HDR 0x5724
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#define CAR_mmAFMT_GENERIC_0 0x4a25
|
|
#define CAR_mmDIG0_AFMT_GENERIC_0 0x4a25
|
|
#define CAR_mmDIG1_AFMT_GENERIC_0 0x4b25
|
|
#define CAR_mmDIG2_AFMT_GENERIC_0 0x4c25
|
|
#define CAR_mmDIG3_AFMT_GENERIC_0 0x4d25
|
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#define CAR_mmDIG4_AFMT_GENERIC_0 0x4e25
|
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#define CAR_mmDIG5_AFMT_GENERIC_0 0x4f25
|
|
#define CAR_mmDIG6_AFMT_GENERIC_0 0x5425
|
|
#define CAR_mmDIG7_AFMT_GENERIC_0 0x5625
|
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#define CAR_mmDIG8_AFMT_GENERIC_0 0x5725
|
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#define CAR_mmAFMT_GENERIC_1 0x4a26
|
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#define CAR_mmDIG0_AFMT_GENERIC_1 0x4a26
|
|
#define CAR_mmDIG1_AFMT_GENERIC_1 0x4b26
|
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#define CAR_mmDIG2_AFMT_GENERIC_1 0x4c26
|
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#define CAR_mmDIG3_AFMT_GENERIC_1 0x4d26
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#define CAR_mmDIG4_AFMT_GENERIC_1 0x4e26
|
|
#define CAR_mmDIG5_AFMT_GENERIC_1 0x4f26
|
|
#define CAR_mmDIG6_AFMT_GENERIC_1 0x5426
|
|
#define CAR_mmDIG7_AFMT_GENERIC_1 0x5626
|
|
#define CAR_mmDIG8_AFMT_GENERIC_1 0x5726
|
|
#define CAR_mmAFMT_GENERIC_2 0x4a27
|
|
#define CAR_mmDIG0_AFMT_GENERIC_2 0x4a27
|
|
#define CAR_mmDIG1_AFMT_GENERIC_2 0x4b27
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#define CAR_mmDIG2_AFMT_GENERIC_2 0x4c27
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#define CAR_mmDIG3_AFMT_GENERIC_2 0x4d27
|
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#define CAR_mmDIG4_AFMT_GENERIC_2 0x4e27
|
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#define CAR_mmDIG5_AFMT_GENERIC_2 0x4f27
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#define CAR_mmDIG6_AFMT_GENERIC_2 0x5427
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#define CAR_mmDIG7_AFMT_GENERIC_2 0x5627
|
|
#define CAR_mmDIG8_AFMT_GENERIC_2 0x5727
|
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#define CAR_mmAFMT_GENERIC_3 0x4a28
|
|
#define CAR_mmDIG0_AFMT_GENERIC_3 0x4a28
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#define CAR_mmDIG1_AFMT_GENERIC_3 0x4b28
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#define CAR_mmDIG2_AFMT_GENERIC_3 0x4c28
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#define CAR_mmDIG3_AFMT_GENERIC_3 0x4d28
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#define CAR_mmDIG4_AFMT_GENERIC_3 0x4e28
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#define CAR_mmDIG5_AFMT_GENERIC_3 0x4f28
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#define CAR_mmDIG6_AFMT_GENERIC_3 0x5428
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#define CAR_mmDIG7_AFMT_GENERIC_3 0x5628
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#define CAR_mmDIG8_AFMT_GENERIC_3 0x5728
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#define CAR_mmAFMT_GENERIC_4 0x4a29
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#define CAR_mmDIG0_AFMT_GENERIC_4 0x4a29
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#define CAR_mmDIG1_AFMT_GENERIC_4 0x4b29
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#define CAR_mmDIG2_AFMT_GENERIC_4 0x4c29
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#define CAR_mmDIG3_AFMT_GENERIC_4 0x4d29
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#define CAR_mmDIG4_AFMT_GENERIC_4 0x4e29
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#define CAR_mmDIG5_AFMT_GENERIC_4 0x4f29
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#define CAR_mmDIG6_AFMT_GENERIC_4 0x5429
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#define CAR_mmDIG7_AFMT_GENERIC_4 0x5629
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#define CAR_mmDIG8_AFMT_GENERIC_4 0x5729
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#define CAR_mmAFMT_GENERIC_5 0x4a2a
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#define CAR_mmDIG0_AFMT_GENERIC_5 0x4a2a
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#define CAR_mmDIG1_AFMT_GENERIC_5 0x4b2a
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#define CAR_mmDIG2_AFMT_GENERIC_5 0x4c2a
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#define CAR_mmDIG3_AFMT_GENERIC_5 0x4d2a
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#define CAR_mmDIG4_AFMT_GENERIC_5 0x4e2a
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#define CAR_mmDIG5_AFMT_GENERIC_5 0x4f2a
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#define CAR_mmDIG6_AFMT_GENERIC_5 0x542a
|
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#define CAR_mmDIG7_AFMT_GENERIC_5 0x562a
|
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#define CAR_mmDIG8_AFMT_GENERIC_5 0x572a
|
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#define CAR_mmAFMT_GENERIC_6 0x4a2b
|
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#define CAR_mmDIG0_AFMT_GENERIC_6 0x4a2b
|
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#define CAR_mmDIG1_AFMT_GENERIC_6 0x4b2b
|
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#define CAR_mmDIG2_AFMT_GENERIC_6 0x4c2b
|
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#define CAR_mmDIG3_AFMT_GENERIC_6 0x4d2b
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#define CAR_mmDIG4_AFMT_GENERIC_6 0x4e2b
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#define CAR_mmDIG5_AFMT_GENERIC_6 0x4f2b
|
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#define CAR_mmDIG6_AFMT_GENERIC_6 0x542b
|
|
#define CAR_mmDIG7_AFMT_GENERIC_6 0x562b
|
|
#define CAR_mmDIG8_AFMT_GENERIC_6 0x572b
|
|
#define CAR_mmAFMT_GENERIC_7 0x4a2c
|
|
#define CAR_mmDIG0_AFMT_GENERIC_7 0x4a2c
|
|
#define CAR_mmDIG1_AFMT_GENERIC_7 0x4b2c
|
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#define CAR_mmDIG2_AFMT_GENERIC_7 0x4c2c
|
|
#define CAR_mmDIG3_AFMT_GENERIC_7 0x4d2c
|
|
#define CAR_mmDIG4_AFMT_GENERIC_7 0x4e2c
|
|
#define CAR_mmDIG5_AFMT_GENERIC_7 0x4f2c
|
|
#define CAR_mmDIG6_AFMT_GENERIC_7 0x542c
|
|
#define CAR_mmDIG7_AFMT_GENERIC_7 0x562c
|
|
#define CAR_mmDIG8_AFMT_GENERIC_7 0x572c
|
|
#define CAR_mmHDMI_GENERIC_PACKET_CONTROL1 0x4a2d
|
|
#define CAR_mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x4a2d
|
|
#define CAR_mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x4b2d
|
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#define CAR_mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4c2d
|
|
#define CAR_mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4d2d
|
|
#define CAR_mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4e2d
|
|
#define CAR_mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4f2d
|
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#define CAR_mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x542d
|
|
#define CAR_mmDIG7_HDMI_GENERIC_PACKET_CONTROL1 0x562d
|
|
#define CAR_mmDIG8_HDMI_GENERIC_PACKET_CONTROL1 0x572d
|
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#define CAR_mmHDMI_ACR_32_0 0x4a2e
|
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#define CAR_mmDIG0_HDMI_ACR_32_0 0x4a2e
|
|
#define CAR_mmDIG1_HDMI_ACR_32_0 0x4b2e
|
|
#define CAR_mmDIG2_HDMI_ACR_32_0 0x4c2e
|
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#define CAR_mmDIG3_HDMI_ACR_32_0 0x4d2e
|
|
#define CAR_mmDIG4_HDMI_ACR_32_0 0x4e2e
|
|
#define CAR_mmDIG5_HDMI_ACR_32_0 0x4f2e
|
|
#define CAR_mmDIG6_HDMI_ACR_32_0 0x542e
|
|
#define CAR_mmDIG7_HDMI_ACR_32_0 0x562e
|
|
#define CAR_mmDIG8_HDMI_ACR_32_0 0x572e
|
|
#define CAR_mmHDMI_ACR_32_1 0x4a2f
|
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#define CAR_mmDIG0_HDMI_ACR_32_1 0x4a2f
|
|
#define CAR_mmDIG1_HDMI_ACR_32_1 0x4b2f
|
|
#define CAR_mmDIG2_HDMI_ACR_32_1 0x4c2f
|
|
#define CAR_mmDIG3_HDMI_ACR_32_1 0x4d2f
|
|
#define CAR_mmDIG4_HDMI_ACR_32_1 0x4e2f
|
|
#define CAR_mmDIG5_HDMI_ACR_32_1 0x4f2f
|
|
#define CAR_mmDIG6_HDMI_ACR_32_1 0x542f
|
|
#define CAR_mmDIG7_HDMI_ACR_32_1 0x562f
|
|
#define CAR_mmDIG8_HDMI_ACR_32_1 0x572f
|
|
#define CAR_mmHDMI_ACR_44_0 0x4a30
|
|
#define CAR_mmDIG0_HDMI_ACR_44_0 0x4a30
|
|
#define CAR_mmDIG1_HDMI_ACR_44_0 0x4b30
|
|
#define CAR_mmDIG2_HDMI_ACR_44_0 0x4c30
|
|
#define CAR_mmDIG3_HDMI_ACR_44_0 0x4d30
|
|
#define CAR_mmDIG4_HDMI_ACR_44_0 0x4e30
|
|
#define CAR_mmDIG5_HDMI_ACR_44_0 0x4f30
|
|
#define CAR_mmDIG6_HDMI_ACR_44_0 0x5430
|
|
#define CAR_mmDIG7_HDMI_ACR_44_0 0x5630
|
|
#define CAR_mmDIG8_HDMI_ACR_44_0 0x5730
|
|
#define CAR_mmHDMI_ACR_44_1 0x4a31
|
|
#define CAR_mmDIG0_HDMI_ACR_44_1 0x4a31
|
|
#define CAR_mmDIG1_HDMI_ACR_44_1 0x4b31
|
|
#define CAR_mmDIG2_HDMI_ACR_44_1 0x4c31
|
|
#define CAR_mmDIG3_HDMI_ACR_44_1 0x4d31
|
|
#define CAR_mmDIG4_HDMI_ACR_44_1 0x4e31
|
|
#define CAR_mmDIG5_HDMI_ACR_44_1 0x4f31
|
|
#define CAR_mmDIG6_HDMI_ACR_44_1 0x5431
|
|
#define CAR_mmDIG7_HDMI_ACR_44_1 0x5631
|
|
#define CAR_mmDIG8_HDMI_ACR_44_1 0x5731
|
|
#define CAR_mmHDMI_ACR_48_0 0x4a32
|
|
#define CAR_mmDIG0_HDMI_ACR_48_0 0x4a32
|
|
#define CAR_mmDIG1_HDMI_ACR_48_0 0x4b32
|
|
#define CAR_mmDIG2_HDMI_ACR_48_0 0x4c32
|
|
#define CAR_mmDIG3_HDMI_ACR_48_0 0x4d32
|
|
#define CAR_mmDIG4_HDMI_ACR_48_0 0x4e32
|
|
#define CAR_mmDIG5_HDMI_ACR_48_0 0x4f32
|
|
#define CAR_mmDIG6_HDMI_ACR_48_0 0x5432
|
|
#define CAR_mmDIG7_HDMI_ACR_48_0 0x5632
|
|
#define CAR_mmDIG8_HDMI_ACR_48_0 0x5732
|
|
#define CAR_mmHDMI_ACR_48_1 0x4a33
|
|
#define CAR_mmDIG0_HDMI_ACR_48_1 0x4a33
|
|
#define CAR_mmDIG1_HDMI_ACR_48_1 0x4b33
|
|
#define CAR_mmDIG2_HDMI_ACR_48_1 0x4c33
|
|
#define CAR_mmDIG3_HDMI_ACR_48_1 0x4d33
|
|
#define CAR_mmDIG4_HDMI_ACR_48_1 0x4e33
|
|
#define CAR_mmDIG5_HDMI_ACR_48_1 0x4f33
|
|
#define CAR_mmDIG6_HDMI_ACR_48_1 0x5433
|
|
#define CAR_mmDIG7_HDMI_ACR_48_1 0x5633
|
|
#define CAR_mmDIG8_HDMI_ACR_48_1 0x5733
|
|
#define CAR_mmHDMI_ACR_STATUS_0 0x4a34
|
|
#define CAR_mmDIG0_HDMI_ACR_STATUS_0 0x4a34
|
|
#define CAR_mmDIG1_HDMI_ACR_STATUS_0 0x4b34
|
|
#define CAR_mmDIG2_HDMI_ACR_STATUS_0 0x4c34
|
|
#define CAR_mmDIG3_HDMI_ACR_STATUS_0 0x4d34
|
|
#define CAR_mmDIG4_HDMI_ACR_STATUS_0 0x4e34
|
|
#define CAR_mmDIG5_HDMI_ACR_STATUS_0 0x4f34
|
|
#define CAR_mmDIG6_HDMI_ACR_STATUS_0 0x5434
|
|
#define CAR_mmDIG7_HDMI_ACR_STATUS_0 0x5634
|
|
#define CAR_mmDIG8_HDMI_ACR_STATUS_0 0x5734
|
|
#define CAR_mmHDMI_ACR_STATUS_1 0x4a35
|
|
#define CAR_mmDIG0_HDMI_ACR_STATUS_1 0x4a35
|
|
#define CAR_mmDIG1_HDMI_ACR_STATUS_1 0x4b35
|
|
#define CAR_mmDIG2_HDMI_ACR_STATUS_1 0x4c35
|
|
#define CAR_mmDIG3_HDMI_ACR_STATUS_1 0x4d35
|
|
#define CAR_mmDIG4_HDMI_ACR_STATUS_1 0x4e35
|
|
#define CAR_mmDIG5_HDMI_ACR_STATUS_1 0x4f35
|
|
#define CAR_mmDIG6_HDMI_ACR_STATUS_1 0x5435
|
|
#define CAR_mmDIG7_HDMI_ACR_STATUS_1 0x5635
|
|
#define CAR_mmDIG8_HDMI_ACR_STATUS_1 0x5735
|
|
#define CAR_mmAFMT_AUDIO_INFO0 0x4a36
|
|
#define CAR_mmDIG0_AFMT_AUDIO_INFO0 0x4a36
|
|
#define CAR_mmDIG1_AFMT_AUDIO_INFO0 0x4b36
|
|
#define CAR_mmDIG2_AFMT_AUDIO_INFO0 0x4c36
|
|
#define CAR_mmDIG3_AFMT_AUDIO_INFO0 0x4d36
|
|
#define CAR_mmDIG4_AFMT_AUDIO_INFO0 0x4e36
|
|
#define CAR_mmDIG5_AFMT_AUDIO_INFO0 0x4f36
|
|
#define CAR_mmDIG6_AFMT_AUDIO_INFO0 0x5436
|
|
#define CAR_mmDIG7_AFMT_AUDIO_INFO0 0x5636
|
|
#define CAR_mmDIG8_AFMT_AUDIO_INFO0 0x5736
|
|
#define CAR_mmAFMT_AUDIO_INFO1 0x4a37
|
|
#define CAR_mmDIG0_AFMT_AUDIO_INFO1 0x4a37
|
|
#define CAR_mmDIG1_AFMT_AUDIO_INFO1 0x4b37
|
|
#define CAR_mmDIG2_AFMT_AUDIO_INFO1 0x4c37
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#define CAR_mmDIG3_AFMT_AUDIO_INFO1 0x4d37
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#define CAR_mmDIG4_AFMT_AUDIO_INFO1 0x4e37
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#define CAR_mmDIG5_AFMT_AUDIO_INFO1 0x4f37
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#define CAR_mmDIG6_AFMT_AUDIO_INFO1 0x5437
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#define CAR_mmDIG7_AFMT_AUDIO_INFO1 0x5637
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#define CAR_mmDIG8_AFMT_AUDIO_INFO1 0x5737
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#define CAR_mmAFMT_60958_0 0x4a38
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#define CAR_mmDIG0_AFMT_60958_0 0x4a38
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#define CAR_mmDIG1_AFMT_60958_0 0x4b38
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#define CAR_mmDIG2_AFMT_60958_0 0x4c38
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#define CAR_mmDIG3_AFMT_60958_0 0x4d38
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#define CAR_mmDIG4_AFMT_60958_0 0x4e38
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#define CAR_mmDIG5_AFMT_60958_0 0x4f38
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#define CAR_mmDIG6_AFMT_60958_0 0x5438
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#define CAR_mmDIG7_AFMT_60958_0 0x5638
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#define CAR_mmDIG8_AFMT_60958_0 0x5738
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#define CAR_mmAFMT_60958_1 0x4a39
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#define CAR_mmDIG0_AFMT_60958_1 0x4a39
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#define CAR_mmDIG1_AFMT_60958_1 0x4b39
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#define CAR_mmDIG2_AFMT_60958_1 0x4c39
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#define CAR_mmDIG3_AFMT_60958_1 0x4d39
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#define CAR_mmDIG4_AFMT_60958_1 0x4e39
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#define CAR_mmDIG5_AFMT_60958_1 0x4f39
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#define CAR_mmDIG6_AFMT_60958_1 0x5439
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#define CAR_mmDIG7_AFMT_60958_1 0x5639
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#define CAR_mmDIG8_AFMT_60958_1 0x5739
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#define CAR_mmAFMT_AUDIO_CRC_CONTROL 0x4a3a
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#define CAR_mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x4a3a
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#define CAR_mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x4b3a
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#define CAR_mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4c3a
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#define CAR_mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4d3a
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#define CAR_mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4e3a
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#define CAR_mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4f3a
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#define CAR_mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x543a
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#define CAR_mmDIG7_AFMT_AUDIO_CRC_CONTROL 0x563a
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#define CAR_mmDIG8_AFMT_AUDIO_CRC_CONTROL 0x573a
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#define CAR_mmAFMT_RAMP_CONTROL0 0x4a3b
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#define CAR_mmDIG0_AFMT_RAMP_CONTROL0 0x4a3b
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#define CAR_mmDIG1_AFMT_RAMP_CONTROL0 0x4b3b
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#define CAR_mmDIG2_AFMT_RAMP_CONTROL0 0x4c3b
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#define CAR_mmDIG3_AFMT_RAMP_CONTROL0 0x4d3b
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#define CAR_mmDIG4_AFMT_RAMP_CONTROL0 0x4e3b
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#define CAR_mmDIG5_AFMT_RAMP_CONTROL0 0x4f3b
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#define CAR_mmDIG6_AFMT_RAMP_CONTROL0 0x543b
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#define CAR_mmDIG7_AFMT_RAMP_CONTROL0 0x563b
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#define CAR_mmDIG8_AFMT_RAMP_CONTROL0 0x573b
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#define CAR_mmAFMT_RAMP_CONTROL1 0x4a3c
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#define CAR_mmDIG0_AFMT_RAMP_CONTROL1 0x4a3c
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#define CAR_mmDIG1_AFMT_RAMP_CONTROL1 0x4b3c
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#define CAR_mmDIG2_AFMT_RAMP_CONTROL1 0x4c3c
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#define CAR_mmDIG3_AFMT_RAMP_CONTROL1 0x4d3c
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#define CAR_mmDIG4_AFMT_RAMP_CONTROL1 0x4e3c
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#define CAR_mmDIG5_AFMT_RAMP_CONTROL1 0x4f3c
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#define CAR_mmDIG6_AFMT_RAMP_CONTROL1 0x543c
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#define CAR_mmDIG7_AFMT_RAMP_CONTROL1 0x563c
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#define CAR_mmDIG8_AFMT_RAMP_CONTROL1 0x573c
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#define CAR_mmAFMT_RAMP_CONTROL2 0x4a3d
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#define CAR_mmDIG0_AFMT_RAMP_CONTROL2 0x4a3d
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#define CAR_mmDIG1_AFMT_RAMP_CONTROL2 0x4b3d
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#define CAR_mmDIG2_AFMT_RAMP_CONTROL2 0x4c3d
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#define CAR_mmDIG3_AFMT_RAMP_CONTROL2 0x4d3d
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#define CAR_mmDIG4_AFMT_RAMP_CONTROL2 0x4e3d
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#define CAR_mmDIG5_AFMT_RAMP_CONTROL2 0x4f3d
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#define CAR_mmDIG6_AFMT_RAMP_CONTROL2 0x543d
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#define CAR_mmDIG7_AFMT_RAMP_CONTROL2 0x563d
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#define CAR_mmDIG8_AFMT_RAMP_CONTROL2 0x573d
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#define CAR_mmAFMT_RAMP_CONTROL3 0x4a3e
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#define CAR_mmDIG0_AFMT_RAMP_CONTROL3 0x4a3e
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#define CAR_mmDIG1_AFMT_RAMP_CONTROL3 0x4b3e
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#define CAR_mmDIG2_AFMT_RAMP_CONTROL3 0x4c3e
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#define CAR_mmDIG3_AFMT_RAMP_CONTROL3 0x4d3e
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#define CAR_mmDIG4_AFMT_RAMP_CONTROL3 0x4e3e
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#define CAR_mmDIG5_AFMT_RAMP_CONTROL3 0x4f3e
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#define CAR_mmDIG6_AFMT_RAMP_CONTROL3 0x543e
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#define CAR_mmDIG7_AFMT_RAMP_CONTROL3 0x563e
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#define CAR_mmDIG8_AFMT_RAMP_CONTROL3 0x573e
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#define CAR_mmAFMT_60958_2 0x4a3f
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#define CAR_mmDIG0_AFMT_60958_2 0x4a3f
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#define CAR_mmDIG1_AFMT_60958_2 0x4b3f
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#define CAR_mmDIG2_AFMT_60958_2 0x4c3f
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#define CAR_mmDIG3_AFMT_60958_2 0x4d3f
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#define CAR_mmDIG4_AFMT_60958_2 0x4e3f
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#define CAR_mmDIG5_AFMT_60958_2 0x4f3f
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#define CAR_mmDIG6_AFMT_60958_2 0x543f
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#define CAR_mmDIG7_AFMT_60958_2 0x563f
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#define CAR_mmDIG8_AFMT_60958_2 0x573f
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#define CAR_mmAFMT_AUDIO_CRC_RESULT 0x4a40
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#define CAR_mmDIG0_AFMT_AUDIO_CRC_RESULT 0x4a40
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#define CAR_mmDIG1_AFMT_AUDIO_CRC_RESULT 0x4b40
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#define CAR_mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4c40
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#define CAR_mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4d40
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#define CAR_mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4e40
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#define CAR_mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4f40
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#define CAR_mmDIG6_AFMT_AUDIO_CRC_RESULT 0x5440
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#define CAR_mmDIG7_AFMT_AUDIO_CRC_RESULT 0x5640
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|
#define CAR_mmDIG8_AFMT_AUDIO_CRC_RESULT 0x5740
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#define CAR_mmAFMT_STATUS 0x4a41
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#define CAR_mmDIG0_AFMT_STATUS 0x4a41
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#define CAR_mmDIG1_AFMT_STATUS 0x4b41
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#define CAR_mmDIG2_AFMT_STATUS 0x4c41
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#define CAR_mmDIG3_AFMT_STATUS 0x4d41
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#define CAR_mmDIG4_AFMT_STATUS 0x4e41
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#define CAR_mmDIG5_AFMT_STATUS 0x4f41
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#define CAR_mmDIG6_AFMT_STATUS 0x5441
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#define CAR_mmDIG7_AFMT_STATUS 0x5641
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#define CAR_mmDIG8_AFMT_STATUS 0x5741
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#define CAR_mmAFMT_AUDIO_PACKET_CONTROL 0x4a42
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#define CAR_mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x4a42
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#define CAR_mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x4b42
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#define CAR_mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x4c42
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#define CAR_mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x4d42
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#define CAR_mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x4e42
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#define CAR_mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4f42
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#define CAR_mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x5442
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#define CAR_mmDIG7_AFMT_AUDIO_PACKET_CONTROL 0x5642
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#define CAR_mmDIG8_AFMT_AUDIO_PACKET_CONTROL 0x5742
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|
#define CAR_mmAFMT_VBI_PACKET_CONTROL 0x4a43
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#define CAR_mmDIG0_AFMT_VBI_PACKET_CONTROL 0x4a43
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#define CAR_mmDIG1_AFMT_VBI_PACKET_CONTROL 0x4b43
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#define CAR_mmDIG2_AFMT_VBI_PACKET_CONTROL 0x4c43
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#define CAR_mmDIG3_AFMT_VBI_PACKET_CONTROL 0x4d43
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#define CAR_mmDIG4_AFMT_VBI_PACKET_CONTROL 0x4e43
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#define CAR_mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4f43
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#define CAR_mmDIG6_AFMT_VBI_PACKET_CONTROL 0x5443
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#define CAR_mmDIG7_AFMT_VBI_PACKET_CONTROL 0x5643
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|
#define CAR_mmDIG8_AFMT_VBI_PACKET_CONTROL 0x5743
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#define CAR_mmAFMT_INFOFRAME_CONTROL0 0x4a44
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|
#define CAR_mmDIG0_AFMT_INFOFRAME_CONTROL0 0x4a44
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#define CAR_mmDIG1_AFMT_INFOFRAME_CONTROL0 0x4b44
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#define CAR_mmDIG2_AFMT_INFOFRAME_CONTROL0 0x4c44
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#define CAR_mmDIG3_AFMT_INFOFRAME_CONTROL0 0x4d44
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#define CAR_mmDIG4_AFMT_INFOFRAME_CONTROL0 0x4e44
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#define CAR_mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4f44
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#define CAR_mmDIG6_AFMT_INFOFRAME_CONTROL0 0x5444
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#define CAR_mmDIG7_AFMT_INFOFRAME_CONTROL0 0x5644
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#define CAR_mmDIG8_AFMT_INFOFRAME_CONTROL0 0x5744
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#define CAR_mmAFMT_AUDIO_SRC_CONTROL 0x4a45
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#define CAR_mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x4a45
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#define CAR_mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x4b45
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#define CAR_mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x4c45
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#define CAR_mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x4d45
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#define CAR_mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x4e45
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#define CAR_mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4f45
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#define CAR_mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x5445
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#define CAR_mmDIG7_AFMT_AUDIO_SRC_CONTROL 0x5645
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#define CAR_mmDIG8_AFMT_AUDIO_SRC_CONTROL 0x5745
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#define CAR_mmAFMT_AUDIO_DBG_DTO_CNTL 0x4a46
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#define CAR_mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x4a46
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#define CAR_mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x4b46
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#define CAR_mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4c46
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#define CAR_mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4d46
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#define CAR_mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4e46
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#define CAR_mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4f46
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#define CAR_mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL 0x5446
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|
#define CAR_mmDIG7_AFMT_AUDIO_DBG_DTO_CNTL 0x5646
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#define CAR_mmDIG8_AFMT_AUDIO_DBG_DTO_CNTL 0x5746
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#define CAR_mmAFMT_CNTL 0x4a7e
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#define CAR_mmDIG0_AFMT_CNTL 0x4a7e
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#define CAR_mmDIG1_AFMT_CNTL 0x4b7e
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#define CAR_mmDIG2_AFMT_CNTL 0x4c7e
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#define CAR_mmDIG3_AFMT_CNTL 0x4d7e
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#define CAR_mmDIG4_AFMT_CNTL 0x4e7e
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#define CAR_mmDIG5_AFMT_CNTL 0x4f7e
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#define CAR_mmDIG6_AFMT_CNTL 0x547e
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#define CAR_mmDIG7_AFMT_CNTL 0x567e
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#define CAR_mmDIG8_AFMT_CNTL 0x577e
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#define CAR_mmDIG_BE_CNTL 0x4a47
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#define CAR_mmDIG0_DIG_BE_CNTL 0x4a47
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#define CAR_mmDIG1_DIG_BE_CNTL 0x4b47
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#define CAR_mmDIG2_DIG_BE_CNTL 0x4c47
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#define CAR_mmDIG3_DIG_BE_CNTL 0x4d47
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#define CAR_mmDIG4_DIG_BE_CNTL 0x4e47
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#define CAR_mmDIG5_DIG_BE_CNTL 0x4f47
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#define CAR_mmDIG6_DIG_BE_CNTL 0x5447
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#define CAR_mmDIG7_DIG_BE_CNTL 0x5647
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#define CAR_mmDIG8_DIG_BE_CNTL 0x5747
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#define CAR_mmDIG_BE_EN_CNTL 0x4a48
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#define CAR_mmDIG0_DIG_BE_EN_CNTL 0x4a48
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#define CAR_mmDIG1_DIG_BE_EN_CNTL 0x4b48
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#define CAR_mmDIG2_DIG_BE_EN_CNTL 0x4c48
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#define CAR_mmDIG3_DIG_BE_EN_CNTL 0x4d48
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|
#define CAR_mmDIG4_DIG_BE_EN_CNTL 0x4e48
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|
#define CAR_mmDIG5_DIG_BE_EN_CNTL 0x4f48
|
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#define CAR_mmDIG6_DIG_BE_EN_CNTL 0x5448
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#define CAR_mmDIG7_DIG_BE_EN_CNTL 0x5648
|
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#define CAR_mmDIG8_DIG_BE_EN_CNTL 0x5748
|
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#define CAR_mmTMDS_CNTL 0x4a6b
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#define CAR_mmDIG0_TMDS_CNTL 0x4a6b
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#define CAR_mmDIG1_TMDS_CNTL 0x4b6b
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#define CAR_mmDIG2_TMDS_CNTL 0x4c6b
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#define CAR_mmDIG3_TMDS_CNTL 0x4d6b
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|
#define CAR_mmDIG4_TMDS_CNTL 0x4e6b
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#define CAR_mmDIG5_TMDS_CNTL 0x4f6b
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#define CAR_mmDIG6_TMDS_CNTL 0x546b
|
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#define CAR_mmDIG7_TMDS_CNTL 0x566b
|
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#define CAR_mmDIG8_TMDS_CNTL 0x576b
|
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#define CAR_mmTMDS_CONTROL_CHAR 0x4a6c
|
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#define CAR_mmDIG0_TMDS_CONTROL_CHAR 0x4a6c
|
|
#define CAR_mmDIG1_TMDS_CONTROL_CHAR 0x4b6c
|
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#define CAR_mmDIG2_TMDS_CONTROL_CHAR 0x4c6c
|
|
#define CAR_mmDIG3_TMDS_CONTROL_CHAR 0x4d6c
|
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#define CAR_mmDIG4_TMDS_CONTROL_CHAR 0x4e6c
|
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#define CAR_mmDIG5_TMDS_CONTROL_CHAR 0x4f6c
|
|
#define CAR_mmDIG6_TMDS_CONTROL_CHAR 0x546c
|
|
#define CAR_mmDIG7_TMDS_CONTROL_CHAR 0x566c
|
|
#define CAR_mmDIG8_TMDS_CONTROL_CHAR 0x576c
|
|
#define CAR_mmTMDS_CONTROL0_FEEDBACK 0x4a6d
|
|
#define CAR_mmDIG0_TMDS_CONTROL0_FEEDBACK 0x4a6d
|
|
#define CAR_mmDIG1_TMDS_CONTROL0_FEEDBACK 0x4b6d
|
|
#define CAR_mmDIG2_TMDS_CONTROL0_FEEDBACK 0x4c6d
|
|
#define CAR_mmDIG3_TMDS_CONTROL0_FEEDBACK 0x4d6d
|
|
#define CAR_mmDIG4_TMDS_CONTROL0_FEEDBACK 0x4e6d
|
|
#define CAR_mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4f6d
|
|
#define CAR_mmDIG6_TMDS_CONTROL0_FEEDBACK 0x546d
|
|
#define CAR_mmDIG7_TMDS_CONTROL0_FEEDBACK 0x566d
|
|
#define CAR_mmDIG8_TMDS_CONTROL0_FEEDBACK 0x576d
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|
#define CAR_mmTMDS_STEREOSYNC_CTL_SEL 0x4a6e
|
|
#define CAR_mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x4a6e
|
|
#define CAR_mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x4b6e
|
|
#define CAR_mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x4c6e
|
|
#define CAR_mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x4d6e
|
|
#define CAR_mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x4e6e
|
|
#define CAR_mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4f6e
|
|
#define CAR_mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x546e
|
|
#define CAR_mmDIG7_TMDS_STEREOSYNC_CTL_SEL 0x566e
|
|
#define CAR_mmDIG8_TMDS_STEREOSYNC_CTL_SEL 0x576e
|
|
#define CAR_mmTMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f
|
|
#define CAR_mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x4a6f
|
|
#define CAR_mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x4b6f
|
|
#define CAR_mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4c6f
|
|
#define CAR_mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4d6f
|
|
#define CAR_mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4e6f
|
|
#define CAR_mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4f6f
|
|
#define CAR_mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x546f
|
|
#define CAR_mmDIG7_TMDS_SYNC_CHAR_PATTERN_0_1 0x566f
|
|
#define CAR_mmDIG8_TMDS_SYNC_CHAR_PATTERN_0_1 0x576f
|
|
#define CAR_mmTMDS_SYNC_CHAR_PATTERN_2_3 0x4a70
|
|
#define CAR_mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x4a70
|
|
#define CAR_mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x4b70
|
|
#define CAR_mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4c70
|
|
#define CAR_mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4d70
|
|
#define CAR_mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4e70
|
|
#define CAR_mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4f70
|
|
#define CAR_mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x5470
|
|
#define CAR_mmDIG7_TMDS_SYNC_CHAR_PATTERN_2_3 0x5670
|
|
#define CAR_mmDIG8_TMDS_SYNC_CHAR_PATTERN_2_3 0x5770
|
|
#define CAR_mmTMDS_DEBUG 0x4a71
|
|
#define CAR_mmDIG0_TMDS_DEBUG 0x4a71
|
|
#define CAR_mmDIG1_TMDS_DEBUG 0x4b71
|
|
#define CAR_mmDIG2_TMDS_DEBUG 0x4c71
|
|
#define CAR_mmDIG3_TMDS_DEBUG 0x4d71
|
|
#define CAR_mmDIG4_TMDS_DEBUG 0x4e71
|
|
#define CAR_mmDIG5_TMDS_DEBUG 0x4f71
|
|
#define CAR_mmDIG6_TMDS_DEBUG 0x5471
|
|
#define CAR_mmDIG7_TMDS_DEBUG 0x5671
|
|
#define CAR_mmDIG8_TMDS_DEBUG 0x5771
|
|
#define CAR_mmTMDS_CTL_BITS 0x4a72
|
|
#define CAR_mmDIG0_TMDS_CTL_BITS 0x4a72
|
|
#define CAR_mmDIG1_TMDS_CTL_BITS 0x4b72
|
|
#define CAR_mmDIG2_TMDS_CTL_BITS 0x4c72
|
|
#define CAR_mmDIG3_TMDS_CTL_BITS 0x4d72
|
|
#define CAR_mmDIG4_TMDS_CTL_BITS 0x4e72
|
|
#define CAR_mmDIG5_TMDS_CTL_BITS 0x4f72
|
|
#define CAR_mmDIG6_TMDS_CTL_BITS 0x5472
|
|
#define CAR_mmDIG7_TMDS_CTL_BITS 0x5672
|
|
#define CAR_mmDIG8_TMDS_CTL_BITS 0x5772
|
|
#define CAR_mmTMDS_DCBALANCER_CONTROL 0x4a73
|
|
#define CAR_mmDIG0_TMDS_DCBALANCER_CONTROL 0x4a73
|
|
#define CAR_mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73
|
|
#define CAR_mmDIG2_TMDS_DCBALANCER_CONTROL 0x4c73
|
|
#define CAR_mmDIG3_TMDS_DCBALANCER_CONTROL 0x4d73
|
|
#define CAR_mmDIG4_TMDS_DCBALANCER_CONTROL 0x4e73
|
|
#define CAR_mmDIG5_TMDS_DCBALANCER_CONTROL 0x4f73
|
|
#define CAR_mmDIG6_TMDS_DCBALANCER_CONTROL 0x5473
|
|
#define CAR_mmDIG7_TMDS_DCBALANCER_CONTROL 0x5673
|
|
#define CAR_mmDIG8_TMDS_DCBALANCER_CONTROL 0x5773
|
|
#define CAR_mmTMDS_CTL0_1_GEN_CNTL 0x4a75
|
|
#define CAR_mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75
|
|
#define CAR_mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x4b75
|
|
#define CAR_mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4c75
|
|
#define CAR_mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4d75
|
|
#define CAR_mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4e75
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#define CAR_mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4f75
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#define CAR_mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x5475
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#define CAR_mmDIG7_TMDS_CTL0_1_GEN_CNTL 0x5675
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#define CAR_mmDIG8_TMDS_CTL0_1_GEN_CNTL 0x5775
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#define CAR_mmTMDS_CTL2_3_GEN_CNTL 0x4a76
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#define CAR_mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x4a76
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#define CAR_mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x4b76
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#define CAR_mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4c76
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#define CAR_mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4d76
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#define CAR_mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4e76
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#define CAR_mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4f76
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#define CAR_mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x5476
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#define CAR_mmDIG7_TMDS_CTL2_3_GEN_CNTL 0x5676
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#define CAR_mmDIG8_TMDS_CTL2_3_GEN_CNTL 0x5776
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#define CAR_mmDIG_VERSION 0x4a78
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#define CAR_mmDIG0_DIG_VERSION 0x4a78
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#define CAR_mmDIG1_DIG_VERSION 0x4b78
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#define CAR_mmDIG2_DIG_VERSION 0x4c78
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#define CAR_mmDIG3_DIG_VERSION 0x4d78
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#define CAR_mmDIG4_DIG_VERSION 0x4e78
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#define CAR_mmDIG5_DIG_VERSION 0x4f78
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#define CAR_mmDIG6_DIG_VERSION 0x5478
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#define CAR_mmDIG7_DIG_VERSION 0x5678
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#define CAR_mmDIG8_DIG_VERSION 0x5778
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#define CAR_mmDIG_LANE_ENABLE 0x4a79
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#define CAR_mmDIG0_DIG_LANE_ENABLE 0x4a79
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#define CAR_mmDIG1_DIG_LANE_ENABLE 0x4b79
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#define CAR_mmDIG2_DIG_LANE_ENABLE 0x4c79
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#define CAR_mmDIG3_DIG_LANE_ENABLE 0x4d79
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#define CAR_mmDIG4_DIG_LANE_ENABLE 0x4e79
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#define CAR_mmDIG5_DIG_LANE_ENABLE 0x4f79
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#define CAR_mmDIG6_DIG_LANE_ENABLE 0x5479
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#define CAR_mmDIG7_DIG_LANE_ENABLE 0x5679
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#define CAR_mmDIG8_DIG_LANE_ENABLE 0x5779
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#define CAR_mmDIG_TEST_DEBUG_INDEX 0x4a7a
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#define CAR_mmDIG0_DIG_TEST_DEBUG_INDEX 0x4a7a
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#define CAR_mmDIG1_DIG_TEST_DEBUG_INDEX 0x4b7a
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#define CAR_mmDIG2_DIG_TEST_DEBUG_INDEX 0x4c7a
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#define CAR_mmDIG3_DIG_TEST_DEBUG_INDEX 0x4d7a
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#define CAR_mmDIG4_DIG_TEST_DEBUG_INDEX 0x4e7a
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#define CAR_mmDIG5_DIG_TEST_DEBUG_INDEX 0x4f7a
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#define CAR_mmDIG6_DIG_TEST_DEBUG_INDEX 0x547a
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#define CAR_mmDIG7_DIG_TEST_DEBUG_INDEX 0x567a
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#define CAR_mmDIG8_DIG_TEST_DEBUG_INDEX 0x577a
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#define CAR_mmDIG_TEST_DEBUG_DATA 0x4a7b
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#define CAR_mmDIG0_DIG_TEST_DEBUG_DATA 0x4a7b
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#define CAR_mmDIG1_DIG_TEST_DEBUG_DATA 0x4b7b
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#define CAR_mmDIG2_DIG_TEST_DEBUG_DATA 0x4c7b
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#define CAR_mmDIG3_DIG_TEST_DEBUG_DATA 0x4d7b
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#define CAR_mmDIG4_DIG_TEST_DEBUG_DATA 0x4e7b
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#define CAR_mmDIG5_DIG_TEST_DEBUG_DATA 0x4f7b
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#define CAR_mmDIG6_DIG_TEST_DEBUG_DATA 0x547b
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#define CAR_mmDIG7_DIG_TEST_DEBUG_DATA 0x567b
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#define CAR_mmDIG8_DIG_TEST_DEBUG_DATA 0x577b
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#define CAR_mmDIG_FE_TEST_DEBUG_INDEX 0x4a7c
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#define CAR_mmDIG0_DIG_FE_TEST_DEBUG_INDEX 0x4a7c
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#define CAR_mmDIG1_DIG_FE_TEST_DEBUG_INDEX 0x4b7c
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#define CAR_mmDIG2_DIG_FE_TEST_DEBUG_INDEX 0x4c7c
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#define CAR_mmDIG3_DIG_FE_TEST_DEBUG_INDEX 0x4d7c
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#define CAR_mmDIG4_DIG_FE_TEST_DEBUG_INDEX 0x4e7c
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#define CAR_mmDIG5_DIG_FE_TEST_DEBUG_INDEX 0x4f7c
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#define CAR_mmDIG6_DIG_FE_TEST_DEBUG_INDEX 0x547c
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#define CAR_mmDIG7_DIG_FE_TEST_DEBUG_INDEX 0x567c
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#define CAR_mmDIG8_DIG_FE_TEST_DEBUG_INDEX 0x577c
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#define CAR_mmDIG_FE_TEST_DEBUG_DATA 0x4a7d
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#define CAR_mmDIG0_DIG_FE_TEST_DEBUG_DATA 0x4a7d
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#define CAR_mmDIG1_DIG_FE_TEST_DEBUG_DATA 0x4b7d
|
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#define CAR_mmDIG2_DIG_FE_TEST_DEBUG_DATA 0x4c7d
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#define CAR_mmDIG3_DIG_FE_TEST_DEBUG_DATA 0x4d7d
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#define CAR_mmDIG4_DIG_FE_TEST_DEBUG_DATA 0x4e7d
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#define CAR_mmDIG5_DIG_FE_TEST_DEBUG_DATA 0x4f7d
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#define CAR_mmDIG6_DIG_FE_TEST_DEBUG_DATA 0x547d
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#define CAR_mmDIG7_DIG_FE_TEST_DEBUG_DATA 0x567d
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#define CAR_mmDIG8_DIG_FE_TEST_DEBUG_DATA 0x577d
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#define CAR_mmDMCU_CTRL 0x1600
|
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#define CAR_mmDMCU_STATUS 0x1601
|
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#define CAR_mmDMCU_PC_START_ADDR 0x1602
|
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#define CAR_mmDMCU_FW_START_ADDR 0x1603
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#define CAR_mmDMCU_FW_END_ADDR 0x1604
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#define CAR_mmDMCU_FW_ISR_START_ADDR 0x1605
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#define CAR_mmDMCU_FW_CS_HI 0x1606
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#define CAR_mmDMCU_FW_CS_LO 0x1607
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#define CAR_mmDMCU_RAM_ACCESS_CTRL 0x1608
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#define CAR_mmDMCU_ERAM_WR_CTRL 0x1609
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#define CAR_mmDMCU_ERAM_WR_DATA 0x160a
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#define CAR_mmDMCU_ERAM_RD_CTRL 0x160b
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#define CAR_mmDMCU_ERAM_RD_DATA 0x160c
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#define CAR_mmDMCU_IRAM_WR_CTRL 0x160d
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#define CAR_mmDMCU_IRAM_WR_DATA 0x160e
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#define CAR_mmDMCU_IRAM_RD_CTRL 0x160f
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#define CAR_mmDMCU_IRAM_RD_DATA 0x1610
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|
#define CAR_mmDMCU_EVENT_TRIGGER 0x1611
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|
#define CAR_mmDMCU_UC_INTERNAL_INT_STATUS 0x1612
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#define CAR_mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x1613
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#define CAR_mmDMCU_INTERRUPT_STATUS 0x1614
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#define CAR_mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615
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#define CAR_mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616
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#define CAR_mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x1631
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#define CAR_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617
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#define CAR_mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x1632
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#define CAR_mmDC_DMCU_SCRATCH 0x1618
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#define CAR_mmDMCU_INT_CNT 0x1619
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#define CAR_mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161a
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|
#define CAR_mmDMCU_UC_CLK_GATING_CNTL 0x161b
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#define CAR_mmMASTER_COMM_DATA_REG1 0x161c
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#define CAR_mmMASTER_COMM_DATA_REG2 0x161d
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#define CAR_mmMASTER_COMM_DATA_REG3 0x161e
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#define CAR_mmMASTER_COMM_CMD_REG 0x161f
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|
#define CAR_mmMASTER_COMM_CNTL_REG 0x1620
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#define CAR_mmSLAVE_COMM_DATA_REG1 0x1621
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#define CAR_mmSLAVE_COMM_DATA_REG2 0x1622
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#define CAR_mmSLAVE_COMM_DATA_REG3 0x1623
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#define CAR_mmSLAVE_COMM_CMD_REG 0x1624
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#define CAR_mmSLAVE_COMM_CNTL_REG 0x1625
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|
#define CAR_mmDMCU_TEST_DEBUG_INDEX 0x1626
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#define CAR_mmDMCU_TEST_DEBUG_DATA 0x1627
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|
#define CAR_mmDMCU_PERFMON_INTERRUPT_STATUS1 0x1644
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#define CAR_mmDMCU_PERFMON_INTERRUPT_STATUS2 0x1645
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#define CAR_mmDMCU_PERFMON_INTERRUPT_STATUS3 0x1646
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#define CAR_mmDMCU_PERFMON_INTERRUPT_STATUS4 0x1647
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#define CAR_mmDMCU_PERFMON_INTERRUPT_STATUS5 0x1642
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#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x1674
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|
#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x1675
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#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x1676
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#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x1677
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#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x1643
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#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1678
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#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x1679
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#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x167a
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#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x167b
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#define CAR_mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x1673
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#define CAR_mmDMCU_DPRX_INTERRUPT_STATUS1 0x1634
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#define CAR_mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x1635
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#define CAR_mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x1636
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#define CAR_mmDP_LINK_CNTL 0x4aa0
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#define CAR_mmDP0_DP_LINK_CNTL 0x4aa0
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#define CAR_mmDP1_DP_LINK_CNTL 0x4ba0
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#define CAR_mmDP2_DP_LINK_CNTL 0x4ca0
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#define CAR_mmDP3_DP_LINK_CNTL 0x4da0
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#define CAR_mmDP4_DP_LINK_CNTL 0x4ea0
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#define CAR_mmDP5_DP_LINK_CNTL 0x4fa0
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#define CAR_mmDP6_DP_LINK_CNTL 0x54a0
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#define CAR_mmDP7_DP_LINK_CNTL 0x56a0
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#define CAR_mmDP8_DP_LINK_CNTL 0x57a0
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#define CAR_mmDP_PIXEL_FORMAT 0x4aa1
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#define CAR_mmDP0_DP_PIXEL_FORMAT 0x4aa1
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#define CAR_mmDP1_DP_PIXEL_FORMAT 0x4ba1
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#define CAR_mmDP2_DP_PIXEL_FORMAT 0x4ca1
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#define CAR_mmDP3_DP_PIXEL_FORMAT 0x4da1
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#define CAR_mmDP4_DP_PIXEL_FORMAT 0x4ea1
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#define CAR_mmDP5_DP_PIXEL_FORMAT 0x4fa1
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#define CAR_mmDP6_DP_PIXEL_FORMAT 0x54a1
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#define CAR_mmDP7_DP_PIXEL_FORMAT 0x56a1
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#define CAR_mmDP8_DP_PIXEL_FORMAT 0x57a1
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#define CAR_mmDP_MSA_COLORIMETRY 0x4aa2
|
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#define CAR_mmDP0_DP_MSA_COLORIMETRY 0x4aa2
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#define CAR_mmDP1_DP_MSA_COLORIMETRY 0x4ba2
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#define CAR_mmDP2_DP_MSA_COLORIMETRY 0x4ca2
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#define CAR_mmDP3_DP_MSA_COLORIMETRY 0x4da2
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#define CAR_mmDP4_DP_MSA_COLORIMETRY 0x4ea2
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#define CAR_mmDP5_DP_MSA_COLORIMETRY 0x4fa2
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#define CAR_mmDP6_DP_MSA_COLORIMETRY 0x54a2
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|
#define CAR_mmDP7_DP_MSA_COLORIMETRY 0x56a2
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|
#define CAR_mmDP8_DP_MSA_COLORIMETRY 0x57a2
|
|
#define CAR_mmDP_CONFIG 0x4aa3
|
|
#define CAR_mmDP0_DP_CONFIG 0x4aa3
|
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#define CAR_mmDP1_DP_CONFIG 0x4ba3
|
|
#define CAR_mmDP2_DP_CONFIG 0x4ca3
|
|
#define CAR_mmDP3_DP_CONFIG 0x4da3
|
|
#define CAR_mmDP4_DP_CONFIG 0x4ea3
|
|
#define CAR_mmDP5_DP_CONFIG 0x4fa3
|
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#define CAR_mmDP6_DP_CONFIG 0x54a3
|
|
#define CAR_mmDP7_DP_CONFIG 0x56a3
|
|
#define CAR_mmDP8_DP_CONFIG 0x57a3
|
|
#define CAR_mmDP_VID_STREAM_CNTL 0x4aa4
|
|
#define CAR_mmDP0_DP_VID_STREAM_CNTL 0x4aa4
|
|
#define CAR_mmDP1_DP_VID_STREAM_CNTL 0x4ba4
|
|
#define CAR_mmDP2_DP_VID_STREAM_CNTL 0x4ca4
|
|
#define CAR_mmDP3_DP_VID_STREAM_CNTL 0x4da4
|
|
#define CAR_mmDP4_DP_VID_STREAM_CNTL 0x4ea4
|
|
#define CAR_mmDP5_DP_VID_STREAM_CNTL 0x4fa4
|
|
#define CAR_mmDP6_DP_VID_STREAM_CNTL 0x54a4
|
|
#define CAR_mmDP7_DP_VID_STREAM_CNTL 0x56a4
|
|
#define CAR_mmDP8_DP_VID_STREAM_CNTL 0x57a4
|
|
#define CAR_mmDP_STEER_FIFO 0x4aa5
|
|
#define CAR_mmDP0_DP_STEER_FIFO 0x4aa5
|
|
#define CAR_mmDP1_DP_STEER_FIFO 0x4ba5
|
|
#define CAR_mmDP2_DP_STEER_FIFO 0x4ca5
|
|
#define CAR_mmDP3_DP_STEER_FIFO 0x4da5
|
|
#define CAR_mmDP4_DP_STEER_FIFO 0x4ea5
|
|
#define CAR_mmDP5_DP_STEER_FIFO 0x4fa5
|
|
#define CAR_mmDP6_DP_STEER_FIFO 0x54a5
|
|
#define CAR_mmDP7_DP_STEER_FIFO 0x56a5
|
|
#define CAR_mmDP8_DP_STEER_FIFO 0x57a5
|
|
#define CAR_mmDP_MSA_MISC 0x4aa6
|
|
#define CAR_mmDP0_DP_MSA_MISC 0x4aa6
|
|
#define CAR_mmDP1_DP_MSA_MISC 0x4ba6
|
|
#define CAR_mmDP2_DP_MSA_MISC 0x4ca6
|
|
#define CAR_mmDP3_DP_MSA_MISC 0x4da6
|
|
#define CAR_mmDP4_DP_MSA_MISC 0x4ea6
|
|
#define CAR_mmDP5_DP_MSA_MISC 0x4fa6
|
|
#define CAR_mmDP6_DP_MSA_MISC 0x54a6
|
|
#define CAR_mmDP7_DP_MSA_MISC 0x56a6
|
|
#define CAR_mmDP8_DP_MSA_MISC 0x57a6
|
|
#define CAR_mmDP_VID_TIMING 0x4aa8
|
|
#define CAR_mmDP0_DP_VID_TIMING 0x4aa8
|
|
#define CAR_mmDP1_DP_VID_TIMING 0x4ba8
|
|
#define CAR_mmDP2_DP_VID_TIMING 0x4ca8
|
|
#define CAR_mmDP3_DP_VID_TIMING 0x4da8
|
|
#define CAR_mmDP4_DP_VID_TIMING 0x4ea8
|
|
#define CAR_mmDP5_DP_VID_TIMING 0x4fa8
|
|
#define CAR_mmDP6_DP_VID_TIMING 0x54a8
|
|
#define CAR_mmDP7_DP_VID_TIMING 0x56a8
|
|
#define CAR_mmDP8_DP_VID_TIMING 0x57a8
|
|
#define CAR_mmDP_VID_N 0x4aa9
|
|
#define CAR_mmDP0_DP_VID_N 0x4aa9
|
|
#define CAR_mmDP1_DP_VID_N 0x4ba9
|
|
#define CAR_mmDP2_DP_VID_N 0x4ca9
|
|
#define CAR_mmDP3_DP_VID_N 0x4da9
|
|
#define CAR_mmDP4_DP_VID_N 0x4ea9
|
|
#define CAR_mmDP5_DP_VID_N 0x4fa9
|
|
#define CAR_mmDP6_DP_VID_N 0x54a9
|
|
#define CAR_mmDP7_DP_VID_N 0x56a9
|
|
#define CAR_mmDP8_DP_VID_N 0x57a9
|
|
#define CAR_mmDP_VID_M 0x4aaa
|
|
#define CAR_mmDP0_DP_VID_M 0x4aaa
|
|
#define CAR_mmDP1_DP_VID_M 0x4baa
|
|
#define CAR_mmDP2_DP_VID_M 0x4caa
|
|
#define CAR_mmDP3_DP_VID_M 0x4daa
|
|
#define CAR_mmDP4_DP_VID_M 0x4eaa
|
|
#define CAR_mmDP5_DP_VID_M 0x4faa
|
|
#define CAR_mmDP6_DP_VID_M 0x54aa
|
|
#define CAR_mmDP7_DP_VID_M 0x56aa
|
|
#define CAR_mmDP8_DP_VID_M 0x57aa
|
|
#define CAR_mmDP_LINK_FRAMING_CNTL 0x4aab
|
|
#define CAR_mmDP0_DP_LINK_FRAMING_CNTL 0x4aab
|
|
#define CAR_mmDP1_DP_LINK_FRAMING_CNTL 0x4bab
|
|
#define CAR_mmDP2_DP_LINK_FRAMING_CNTL 0x4cab
|
|
#define CAR_mmDP3_DP_LINK_FRAMING_CNTL 0x4dab
|
|
#define CAR_mmDP4_DP_LINK_FRAMING_CNTL 0x4eab
|
|
#define CAR_mmDP5_DP_LINK_FRAMING_CNTL 0x4fab
|
|
#define CAR_mmDP6_DP_LINK_FRAMING_CNTL 0x54ab
|
|
#define CAR_mmDP7_DP_LINK_FRAMING_CNTL 0x56ab
|
|
#define CAR_mmDP8_DP_LINK_FRAMING_CNTL 0x57ab
|
|
#define CAR_mmDP_HBR2_EYE_PATTERN 0x4aac
|
|
#define CAR_mmDP0_DP_HBR2_EYE_PATTERN 0x4aac
|
|
#define CAR_mmDP1_DP_HBR2_EYE_PATTERN 0x4bac
|
|
#define CAR_mmDP2_DP_HBR2_EYE_PATTERN 0x4cac
|
|
#define CAR_mmDP3_DP_HBR2_EYE_PATTERN 0x4dac
|
|
#define CAR_mmDP4_DP_HBR2_EYE_PATTERN 0x4eac
|
|
#define CAR_mmDP5_DP_HBR2_EYE_PATTERN 0x4fac
|
|
#define CAR_mmDP6_DP_HBR2_EYE_PATTERN 0x54ac
|
|
#define CAR_mmDP7_DP_HBR2_EYE_PATTERN 0x56ac
|
|
#define CAR_mmDP8_DP_HBR2_EYE_PATTERN 0x57ac
|
|
#define CAR_mmDP_VID_MSA_VBID 0x4aad
|
|
#define CAR_mmDP0_DP_VID_MSA_VBID 0x4aad
|
|
#define CAR_mmDP1_DP_VID_MSA_VBID 0x4bad
|
|
#define CAR_mmDP2_DP_VID_MSA_VBID 0x4cad
|
|
#define CAR_mmDP3_DP_VID_MSA_VBID 0x4dad
|
|
#define CAR_mmDP4_DP_VID_MSA_VBID 0x4ead
|
|
#define CAR_mmDP5_DP_VID_MSA_VBID 0x4fad
|
|
#define CAR_mmDP6_DP_VID_MSA_VBID 0x54ad
|
|
#define CAR_mmDP7_DP_VID_MSA_VBID 0x56ad
|
|
#define CAR_mmDP8_DP_VID_MSA_VBID 0x57ad
|
|
#define CAR_mmDP_VID_INTERRUPT_CNTL 0x4aae
|
|
#define CAR_mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae
|
|
#define CAR_mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae
|
|
#define CAR_mmDP2_DP_VID_INTERRUPT_CNTL 0x4cae
|
|
#define CAR_mmDP3_DP_VID_INTERRUPT_CNTL 0x4dae
|
|
#define CAR_mmDP4_DP_VID_INTERRUPT_CNTL 0x4eae
|
|
#define CAR_mmDP5_DP_VID_INTERRUPT_CNTL 0x4fae
|
|
#define CAR_mmDP6_DP_VID_INTERRUPT_CNTL 0x54ae
|
|
#define CAR_mmDP7_DP_VID_INTERRUPT_CNTL 0x56ae
|
|
#define CAR_mmDP8_DP_VID_INTERRUPT_CNTL 0x57ae
|
|
#define CAR_mmDP_DPHY_CNTL 0x4aaf
|
|
#define CAR_mmDP0_DP_DPHY_CNTL 0x4aaf
|
|
#define CAR_mmDP1_DP_DPHY_CNTL 0x4baf
|
|
#define CAR_mmDP2_DP_DPHY_CNTL 0x4caf
|
|
#define CAR_mmDP3_DP_DPHY_CNTL 0x4daf
|
|
#define CAR_mmDP4_DP_DPHY_CNTL 0x4eaf
|
|
#define CAR_mmDP5_DP_DPHY_CNTL 0x4faf
|
|
#define CAR_mmDP6_DP_DPHY_CNTL 0x54af
|
|
#define CAR_mmDP7_DP_DPHY_CNTL 0x56af
|
|
#define CAR_mmDP8_DP_DPHY_CNTL 0x57af
|
|
#define CAR_mmDP_DPHY_TRAINING_PATTERN_SEL 0x4ab0
|
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#define CAR_mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x4ab0
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#define CAR_mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x4bb0
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#define CAR_mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0
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#define CAR_mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x4db0
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#define CAR_mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0
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#define CAR_mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4fb0
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#define CAR_mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x54b0
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#define CAR_mmDP7_DP_DPHY_TRAINING_PATTERN_SEL 0x56b0
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#define CAR_mmDP8_DP_DPHY_TRAINING_PATTERN_SEL 0x57b0
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#define CAR_mmDP_DPHY_SYM0 0x4ab1
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#define CAR_mmDP0_DP_DPHY_SYM0 0x4ab1
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#define CAR_mmDP1_DP_DPHY_SYM0 0x4bb1
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#define CAR_mmDP2_DP_DPHY_SYM0 0x4cb1
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#define CAR_mmDP3_DP_DPHY_SYM0 0x4db1
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#define CAR_mmDP4_DP_DPHY_SYM0 0x4eb1
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#define CAR_mmDP5_DP_DPHY_SYM0 0x4fb1
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#define CAR_mmDP6_DP_DPHY_SYM0 0x54b1
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#define CAR_mmDP7_DP_DPHY_SYM0 0x56b1
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#define CAR_mmDP8_DP_DPHY_SYM0 0x57b1
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#define CAR_mmDP_DPHY_SYM1 0x4ab2
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#define CAR_mmDP0_DP_DPHY_SYM1 0x4ab2
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#define CAR_mmDP1_DP_DPHY_SYM1 0x4bb2
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#define CAR_mmDP2_DP_DPHY_SYM1 0x4cb2
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#define CAR_mmDP3_DP_DPHY_SYM1 0x4db2
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#define CAR_mmDP4_DP_DPHY_SYM1 0x4eb2
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#define CAR_mmDP5_DP_DPHY_SYM1 0x4fb2
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#define CAR_mmDP6_DP_DPHY_SYM1 0x54b2
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#define CAR_mmDP7_DP_DPHY_SYM1 0x56b2
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#define CAR_mmDP8_DP_DPHY_SYM1 0x57b2
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#define CAR_mmDP_DPHY_SYM2 0x4ab3
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#define CAR_mmDP0_DP_DPHY_SYM2 0x4ab3
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#define CAR_mmDP1_DP_DPHY_SYM2 0x4bb3
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#define CAR_mmDP2_DP_DPHY_SYM2 0x4cb3
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#define CAR_mmDP3_DP_DPHY_SYM2 0x4db3
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#define CAR_mmDP4_DP_DPHY_SYM2 0x4eb3
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#define CAR_mmDP5_DP_DPHY_SYM2 0x4fb3
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#define CAR_mmDP6_DP_DPHY_SYM2 0x54b3
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#define CAR_mmDP7_DP_DPHY_SYM2 0x56b3
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#define CAR_mmDP8_DP_DPHY_SYM2 0x57b3
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#define CAR_mmDP_DPHY_8B10B_CNTL 0x4ab4
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#define CAR_mmDP0_DP_DPHY_8B10B_CNTL 0x4ab4
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#define CAR_mmDP1_DP_DPHY_8B10B_CNTL 0x4bb4
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#define CAR_mmDP2_DP_DPHY_8B10B_CNTL 0x4cb4
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#define CAR_mmDP3_DP_DPHY_8B10B_CNTL 0x4db4
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#define CAR_mmDP4_DP_DPHY_8B10B_CNTL 0x4eb4
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#define CAR_mmDP5_DP_DPHY_8B10B_CNTL 0x4fb4
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#define CAR_mmDP6_DP_DPHY_8B10B_CNTL 0x54b4
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#define CAR_mmDP7_DP_DPHY_8B10B_CNTL 0x56b4
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#define CAR_mmDP8_DP_DPHY_8B10B_CNTL 0x57b4
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#define CAR_mmDP_DPHY_PRBS_CNTL 0x4ab5
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#define CAR_mmDP0_DP_DPHY_PRBS_CNTL 0x4ab5
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#define CAR_mmDP1_DP_DPHY_PRBS_CNTL 0x4bb5
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#define CAR_mmDP2_DP_DPHY_PRBS_CNTL 0x4cb5
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#define CAR_mmDP3_DP_DPHY_PRBS_CNTL 0x4db5
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#define CAR_mmDP4_DP_DPHY_PRBS_CNTL 0x4eb5
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#define CAR_mmDP5_DP_DPHY_PRBS_CNTL 0x4fb5
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#define CAR_mmDP6_DP_DPHY_PRBS_CNTL 0x54b5
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#define CAR_mmDP7_DP_DPHY_PRBS_CNTL 0x56b5
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#define CAR_mmDP8_DP_DPHY_PRBS_CNTL 0x57b5
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#define CAR_mmDP_DPHY_BS_SR_SWAP_CNTL 0x4adc
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#define CAR_mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4adc
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#define CAR_mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4bdc
|
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#define CAR_mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4cdc
|
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#define CAR_mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4ddc
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#define CAR_mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4edc
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#define CAR_mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4fdc
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#define CAR_mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54dc
|
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#define CAR_mmDP7_DP_DPHY_BS_SR_SWAP_CNTL 0x56dc
|
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#define CAR_mmDP8_DP_DPHY_BS_SR_SWAP_CNTL 0x57dc
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#define CAR_mmDP_DPHY_CRC_EN 0x4ab7
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#define CAR_mmDP0_DP_DPHY_CRC_EN 0x4ab7
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#define CAR_mmDP1_DP_DPHY_CRC_EN 0x4bb7
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#define CAR_mmDP2_DP_DPHY_CRC_EN 0x4cb7
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#define CAR_mmDP3_DP_DPHY_CRC_EN 0x4db7
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#define CAR_mmDP4_DP_DPHY_CRC_EN 0x4eb7
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#define CAR_mmDP5_DP_DPHY_CRC_EN 0x4fb7
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#define CAR_mmDP6_DP_DPHY_CRC_EN 0x54b7
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#define CAR_mmDP7_DP_DPHY_CRC_EN 0x56b7
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#define CAR_mmDP8_DP_DPHY_CRC_EN 0x57b7
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#define CAR_mmDP_DPHY_CRC_CNTL 0x4ab8
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#define CAR_mmDP0_DP_DPHY_CRC_CNTL 0x4ab8
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#define CAR_mmDP1_DP_DPHY_CRC_CNTL 0x4bb8
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#define CAR_mmDP2_DP_DPHY_CRC_CNTL 0x4cb8
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#define CAR_mmDP3_DP_DPHY_CRC_CNTL 0x4db8
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#define CAR_mmDP4_DP_DPHY_CRC_CNTL 0x4eb8
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#define CAR_mmDP5_DP_DPHY_CRC_CNTL 0x4fb8
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#define CAR_mmDP6_DP_DPHY_CRC_CNTL 0x54b8
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#define CAR_mmDP7_DP_DPHY_CRC_CNTL 0x56b8
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#define CAR_mmDP8_DP_DPHY_CRC_CNTL 0x57b8
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#define CAR_mmDP_DPHY_CRC_RESULT 0x4ab9
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#define CAR_mmDP0_DP_DPHY_CRC_RESULT 0x4ab9
|
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#define CAR_mmDP1_DP_DPHY_CRC_RESULT 0x4bb9
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#define CAR_mmDP2_DP_DPHY_CRC_RESULT 0x4cb9
|
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#define CAR_mmDP3_DP_DPHY_CRC_RESULT 0x4db9
|
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#define CAR_mmDP4_DP_DPHY_CRC_RESULT 0x4eb9
|
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#define CAR_mmDP5_DP_DPHY_CRC_RESULT 0x4fb9
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#define CAR_mmDP6_DP_DPHY_CRC_RESULT 0x54b9
|
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#define CAR_mmDP7_DP_DPHY_CRC_RESULT 0x56b9
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#define CAR_mmDP8_DP_DPHY_CRC_RESULT 0x57b9
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#define CAR_mmDP_DPHY_CRC_MST_CNTL 0x4aba
|
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#define CAR_mmDP0_DP_DPHY_CRC_MST_CNTL 0x4aba
|
|
#define CAR_mmDP1_DP_DPHY_CRC_MST_CNTL 0x4bba
|
|
#define CAR_mmDP2_DP_DPHY_CRC_MST_CNTL 0x4cba
|
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#define CAR_mmDP3_DP_DPHY_CRC_MST_CNTL 0x4dba
|
|
#define CAR_mmDP4_DP_DPHY_CRC_MST_CNTL 0x4eba
|
|
#define CAR_mmDP5_DP_DPHY_CRC_MST_CNTL 0x4fba
|
|
#define CAR_mmDP6_DP_DPHY_CRC_MST_CNTL 0x54ba
|
|
#define CAR_mmDP7_DP_DPHY_CRC_MST_CNTL 0x56ba
|
|
#define CAR_mmDP8_DP_DPHY_CRC_MST_CNTL 0x57ba
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|
#define CAR_mmDP_DPHY_CRC_MST_STATUS 0x4abb
|
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#define CAR_mmDP0_DP_DPHY_CRC_MST_STATUS 0x4abb
|
|
#define CAR_mmDP1_DP_DPHY_CRC_MST_STATUS 0x4bbb
|
|
#define CAR_mmDP2_DP_DPHY_CRC_MST_STATUS 0x4cbb
|
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#define CAR_mmDP3_DP_DPHY_CRC_MST_STATUS 0x4dbb
|
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#define CAR_mmDP4_DP_DPHY_CRC_MST_STATUS 0x4ebb
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#define CAR_mmDP5_DP_DPHY_CRC_MST_STATUS 0x4fbb
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|
#define CAR_mmDP6_DP_DPHY_CRC_MST_STATUS 0x54bb
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#define CAR_mmDP7_DP_DPHY_CRC_MST_STATUS 0x56bb
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|
#define CAR_mmDP8_DP_DPHY_CRC_MST_STATUS 0x57bb
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#define CAR_mmDP_DPHY_FAST_TRAINING 0x4abc
|
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#define CAR_mmDP0_DP_DPHY_FAST_TRAINING 0x4abc
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#define CAR_mmDP1_DP_DPHY_FAST_TRAINING 0x4bbc
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#define CAR_mmDP2_DP_DPHY_FAST_TRAINING 0x4cbc
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#define CAR_mmDP3_DP_DPHY_FAST_TRAINING 0x4dbc
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#define CAR_mmDP4_DP_DPHY_FAST_TRAINING 0x4ebc
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#define CAR_mmDP5_DP_DPHY_FAST_TRAINING 0x4fbc
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#define CAR_mmDP6_DP_DPHY_FAST_TRAINING 0x54bc
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#define CAR_mmDP7_DP_DPHY_FAST_TRAINING 0x56bc
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#define CAR_mmDP8_DP_DPHY_FAST_TRAINING 0x57bc
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#define CAR_mmDP_DPHY_FAST_TRAINING_STATUS 0x4abd
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#define CAR_mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x4abd
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#define CAR_mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x4bbd
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#define CAR_mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x4cbd
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#define CAR_mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x4dbd
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#define CAR_mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x4ebd
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#define CAR_mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4fbd
|
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#define CAR_mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x54bd
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#define CAR_mmDP7_DP_DPHY_FAST_TRAINING_STATUS 0x56bd
|
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#define CAR_mmDP8_DP_DPHY_FAST_TRAINING_STATUS 0x57bd
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#define CAR_mmDP_DPHY_HBR2_PATTERN_CONTROL 0x4add
|
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#define CAR_mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x4add
|
|
#define CAR_mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x4bdd
|
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#define CAR_mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x4cdd
|
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#define CAR_mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x4ddd
|
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#define CAR_mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x4edd
|
|
#define CAR_mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x4fdd
|
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#define CAR_mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x54dd
|
|
#define CAR_mmDP7_DP_DPHY_HBR2_PATTERN_CONTROL 0x56dd
|
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#define CAR_mmDP8_DP_DPHY_HBR2_PATTERN_CONTROL 0x57dd
|
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#define CAR_mmDP_MSA_V_TIMING_OVERRIDE1 0x4abe
|
|
#define CAR_mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x4abe
|
|
#define CAR_mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x4bbe
|
|
#define CAR_mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x4cbe
|
|
#define CAR_mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x4dbe
|
|
#define CAR_mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x4ebe
|
|
#define CAR_mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4fbe
|
|
#define CAR_mmDP6_DP_MSA_V_TIMING_OVERRIDE1 0x54be
|
|
#define CAR_mmDP7_DP_MSA_V_TIMING_OVERRIDE1 0x56be
|
|
#define CAR_mmDP8_DP_MSA_V_TIMING_OVERRIDE1 0x57be
|
|
#define CAR_mmDP_MSA_V_TIMING_OVERRIDE2 0x4abf
|
|
#define CAR_mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x4abf
|
|
#define CAR_mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x4bbf
|
|
#define CAR_mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x4cbf
|
|
#define CAR_mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x4dbf
|
|
#define CAR_mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x4ebf
|
|
#define CAR_mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4fbf
|
|
#define CAR_mmDP6_DP_MSA_V_TIMING_OVERRIDE2 0x54bf
|
|
#define CAR_mmDP7_DP_MSA_V_TIMING_OVERRIDE2 0x56bf
|
|
#define CAR_mmDP8_DP_MSA_V_TIMING_OVERRIDE2 0x57bf
|
|
#define CAR_mmDP_SEC_CNTL 0x4ac3
|
|
#define CAR_mmDP0_DP_SEC_CNTL 0x4ac3
|
|
#define CAR_mmDP1_DP_SEC_CNTL 0x4bc3
|
|
#define CAR_mmDP2_DP_SEC_CNTL 0x4cc3
|
|
#define CAR_mmDP3_DP_SEC_CNTL 0x4dc3
|
|
#define CAR_mmDP4_DP_SEC_CNTL 0x4ec3
|
|
#define CAR_mmDP5_DP_SEC_CNTL 0x4fc3
|
|
#define CAR_mmDP6_DP_SEC_CNTL 0x54c3
|
|
#define CAR_mmDP7_DP_SEC_CNTL 0x56c3
|
|
#define CAR_mmDP8_DP_SEC_CNTL 0x57c3
|
|
#define CAR_mmDP_SEC_CNTL1 0x4ac4
|
|
#define CAR_mmDP0_DP_SEC_CNTL1 0x4ac4
|
|
#define CAR_mmDP1_DP_SEC_CNTL1 0x4bc4
|
|
#define CAR_mmDP2_DP_SEC_CNTL1 0x4cc4
|
|
#define CAR_mmDP3_DP_SEC_CNTL1 0x4dc4
|
|
#define CAR_mmDP4_DP_SEC_CNTL1 0x4ec4
|
|
#define CAR_mmDP5_DP_SEC_CNTL1 0x4fc4
|
|
#define CAR_mmDP6_DP_SEC_CNTL1 0x54c4
|
|
#define CAR_mmDP7_DP_SEC_CNTL1 0x56c4
|
|
#define CAR_mmDP8_DP_SEC_CNTL1 0x57c4
|
|
#define CAR_mmDP_SEC_FRAMING1 0x4ac5
|
|
#define CAR_mmDP0_DP_SEC_FRAMING1 0x4ac5
|
|
#define CAR_mmDP1_DP_SEC_FRAMING1 0x4bc5
|
|
#define CAR_mmDP2_DP_SEC_FRAMING1 0x4cc5
|
|
#define CAR_mmDP3_DP_SEC_FRAMING1 0x4dc5
|
|
#define CAR_mmDP4_DP_SEC_FRAMING1 0x4ec5
|
|
#define CAR_mmDP5_DP_SEC_FRAMING1 0x4fc5
|
|
#define CAR_mmDP6_DP_SEC_FRAMING1 0x54c5
|
|
#define CAR_mmDP7_DP_SEC_FRAMING1 0x56c5
|
|
#define CAR_mmDP8_DP_SEC_FRAMING1 0x57c5
|
|
#define CAR_mmDP_SEC_FRAMING2 0x4ac6
|
|
#define CAR_mmDP0_DP_SEC_FRAMING2 0x4ac6
|
|
#define CAR_mmDP1_DP_SEC_FRAMING2 0x4bc6
|
|
#define CAR_mmDP2_DP_SEC_FRAMING2 0x4cc6
|
|
#define CAR_mmDP3_DP_SEC_FRAMING2 0x4dc6
|
|
#define CAR_mmDP4_DP_SEC_FRAMING2 0x4ec6
|
|
#define CAR_mmDP5_DP_SEC_FRAMING2 0x4fc6
|
|
#define CAR_mmDP6_DP_SEC_FRAMING2 0x54c6
|
|
#define CAR_mmDP7_DP_SEC_FRAMING2 0x56c6
|
|
#define CAR_mmDP8_DP_SEC_FRAMING2 0x57c6
|
|
#define CAR_mmDP_SEC_FRAMING3 0x4ac7
|
|
#define CAR_mmDP0_DP_SEC_FRAMING3 0x4ac7
|
|
#define CAR_mmDP1_DP_SEC_FRAMING3 0x4bc7
|
|
#define CAR_mmDP2_DP_SEC_FRAMING3 0x4cc7
|
|
#define CAR_mmDP3_DP_SEC_FRAMING3 0x4dc7
|
|
#define CAR_mmDP4_DP_SEC_FRAMING3 0x4ec7
|
|
#define CAR_mmDP5_DP_SEC_FRAMING3 0x4fc7
|
|
#define CAR_mmDP6_DP_SEC_FRAMING3 0x54c7
|
|
#define CAR_mmDP7_DP_SEC_FRAMING3 0x56c7
|
|
#define CAR_mmDP8_DP_SEC_FRAMING3 0x57c7
|
|
#define CAR_mmDP_SEC_FRAMING4 0x4ac8
|
|
#define CAR_mmDP0_DP_SEC_FRAMING4 0x4ac8
|
|
#define CAR_mmDP1_DP_SEC_FRAMING4 0x4bc8
|
|
#define CAR_mmDP2_DP_SEC_FRAMING4 0x4cc8
|
|
#define CAR_mmDP3_DP_SEC_FRAMING4 0x4dc8
|
|
#define CAR_mmDP4_DP_SEC_FRAMING4 0x4ec8
|
|
#define CAR_mmDP5_DP_SEC_FRAMING4 0x4fc8
|
|
#define CAR_mmDP6_DP_SEC_FRAMING4 0x54c8
|
|
#define CAR_mmDP7_DP_SEC_FRAMING4 0x56c8
|
|
#define CAR_mmDP8_DP_SEC_FRAMING4 0x57c8
|
|
#define CAR_mmDP_SEC_AUD_N 0x4ac9
|
|
#define CAR_mmDP0_DP_SEC_AUD_N 0x4ac9
|
|
#define CAR_mmDP1_DP_SEC_AUD_N 0x4bc9
|
|
#define CAR_mmDP2_DP_SEC_AUD_N 0x4cc9
|
|
#define CAR_mmDP3_DP_SEC_AUD_N 0x4dc9
|
|
#define CAR_mmDP4_DP_SEC_AUD_N 0x4ec9
|
|
#define CAR_mmDP5_DP_SEC_AUD_N 0x4fc9
|
|
#define CAR_mmDP6_DP_SEC_AUD_N 0x54c9
|
|
#define CAR_mmDP7_DP_SEC_AUD_N 0x56c9
|
|
#define CAR_mmDP8_DP_SEC_AUD_N 0x57c9
|
|
#define CAR_mmDP_SEC_AUD_N_READBACK 0x4aca
|
|
#define CAR_mmDP0_DP_SEC_AUD_N_READBACK 0x4aca
|
|
#define CAR_mmDP1_DP_SEC_AUD_N_READBACK 0x4bca
|
|
#define CAR_mmDP2_DP_SEC_AUD_N_READBACK 0x4cca
|
|
#define CAR_mmDP3_DP_SEC_AUD_N_READBACK 0x4dca
|
|
#define CAR_mmDP4_DP_SEC_AUD_N_READBACK 0x4eca
|
|
#define CAR_mmDP5_DP_SEC_AUD_N_READBACK 0x4fca
|
|
#define CAR_mmDP6_DP_SEC_AUD_N_READBACK 0x54ca
|
|
#define CAR_mmDP7_DP_SEC_AUD_N_READBACK 0x56ca
|
|
#define CAR_mmDP8_DP_SEC_AUD_N_READBACK 0x57ca
|
|
#define CAR_mmDP_SEC_AUD_M 0x4acb
|
|
#define CAR_mmDP0_DP_SEC_AUD_M 0x4acb
|
|
#define CAR_mmDP1_DP_SEC_AUD_M 0x4bcb
|
|
#define CAR_mmDP2_DP_SEC_AUD_M 0x4ccb
|
|
#define CAR_mmDP3_DP_SEC_AUD_M 0x4dcb
|
|
#define CAR_mmDP4_DP_SEC_AUD_M 0x4ecb
|
|
#define CAR_mmDP5_DP_SEC_AUD_M 0x4fcb
|
|
#define CAR_mmDP6_DP_SEC_AUD_M 0x54cb
|
|
#define CAR_mmDP7_DP_SEC_AUD_M 0x56cb
|
|
#define CAR_mmDP8_DP_SEC_AUD_M 0x57cb
|
|
#define CAR_mmDP_SEC_AUD_M_READBACK 0x4acc
|
|
#define CAR_mmDP0_DP_SEC_AUD_M_READBACK 0x4acc
|
|
#define CAR_mmDP1_DP_SEC_AUD_M_READBACK 0x4bcc
|
|
#define CAR_mmDP2_DP_SEC_AUD_M_READBACK 0x4ccc
|
|
#define CAR_mmDP3_DP_SEC_AUD_M_READBACK 0x4dcc
|
|
#define CAR_mmDP4_DP_SEC_AUD_M_READBACK 0x4ecc
|
|
#define CAR_mmDP5_DP_SEC_AUD_M_READBACK 0x4fcc
|
|
#define CAR_mmDP6_DP_SEC_AUD_M_READBACK 0x54cc
|
|
#define CAR_mmDP7_DP_SEC_AUD_M_READBACK 0x56cc
|
|
#define CAR_mmDP8_DP_SEC_AUD_M_READBACK 0x57cc
|
|
#define CAR_mmDP_SEC_TIMESTAMP 0x4acd
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#define CAR_mmDP0_DP_SEC_TIMESTAMP 0x4acd
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#define CAR_mmDP1_DP_SEC_TIMESTAMP 0x4bcd
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#define CAR_mmDP2_DP_SEC_TIMESTAMP 0x4ccd
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#define CAR_mmDP3_DP_SEC_TIMESTAMP 0x4dcd
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#define CAR_mmDP4_DP_SEC_TIMESTAMP 0x4ecd
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#define CAR_mmDP5_DP_SEC_TIMESTAMP 0x4fcd
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#define CAR_mmDP6_DP_SEC_TIMESTAMP 0x54cd
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#define CAR_mmDP7_DP_SEC_TIMESTAMP 0x56cd
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#define CAR_mmDP8_DP_SEC_TIMESTAMP 0x57cd
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#define CAR_mmDP_SEC_PACKET_CNTL 0x4ace
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#define CAR_mmDP0_DP_SEC_PACKET_CNTL 0x4ace
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#define CAR_mmDP1_DP_SEC_PACKET_CNTL 0x4bce
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#define CAR_mmDP2_DP_SEC_PACKET_CNTL 0x4cce
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#define CAR_mmDP3_DP_SEC_PACKET_CNTL 0x4dce
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#define CAR_mmDP4_DP_SEC_PACKET_CNTL 0x4ece
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#define CAR_mmDP5_DP_SEC_PACKET_CNTL 0x4fce
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#define CAR_mmDP6_DP_SEC_PACKET_CNTL 0x54ce
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#define CAR_mmDP7_DP_SEC_PACKET_CNTL 0x56ce
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#define CAR_mmDP8_DP_SEC_PACKET_CNTL 0x57ce
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#define CAR_mmDP_MSE_RATE_CNTL 0x4acf
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#define CAR_mmDP0_DP_MSE_RATE_CNTL 0x4acf
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#define CAR_mmDP1_DP_MSE_RATE_CNTL 0x4bcf
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#define CAR_mmDP2_DP_MSE_RATE_CNTL 0x4ccf
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#define CAR_mmDP3_DP_MSE_RATE_CNTL 0x4dcf
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#define CAR_mmDP4_DP_MSE_RATE_CNTL 0x4ecf
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#define CAR_mmDP5_DP_MSE_RATE_CNTL 0x4fcf
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#define CAR_mmDP6_DP_MSE_RATE_CNTL 0x54cf
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#define CAR_mmDP7_DP_MSE_RATE_CNTL 0x56cf
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#define CAR_mmDP8_DP_MSE_RATE_CNTL 0x57cf
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#define CAR_mmDP_MSE_RATE_UPDATE 0x4ad1
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#define CAR_mmDP0_DP_MSE_RATE_UPDATE 0x4ad1
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#define CAR_mmDP1_DP_MSE_RATE_UPDATE 0x4bd1
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#define CAR_mmDP2_DP_MSE_RATE_UPDATE 0x4cd1
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#define CAR_mmDP3_DP_MSE_RATE_UPDATE 0x4dd1
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#define CAR_mmDP4_DP_MSE_RATE_UPDATE 0x4ed1
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#define CAR_mmDP5_DP_MSE_RATE_UPDATE 0x4fd1
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#define CAR_mmDP6_DP_MSE_RATE_UPDATE 0x54d1
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#define CAR_mmDP7_DP_MSE_RATE_UPDATE 0x56d1
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#define CAR_mmDP8_DP_MSE_RATE_UPDATE 0x57d1
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#define CAR_mmDP_MSE_SAT0 0x4ad2
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#define CAR_mmDP0_DP_MSE_SAT0 0x4ad2
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#define CAR_mmDP1_DP_MSE_SAT0 0x4bd2
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#define CAR_mmDP2_DP_MSE_SAT0 0x4cd2
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#define CAR_mmDP3_DP_MSE_SAT0 0x4dd2
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#define CAR_mmDP4_DP_MSE_SAT0 0x4ed2
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#define CAR_mmDP5_DP_MSE_SAT0 0x4fd2
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#define CAR_mmDP6_DP_MSE_SAT0 0x54d2
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#define CAR_mmDP7_DP_MSE_SAT0 0x56d2
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#define CAR_mmDP8_DP_MSE_SAT0 0x57d2
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#define CAR_mmDP_MSE_SAT1 0x4ad3
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#define CAR_mmDP0_DP_MSE_SAT1 0x4ad3
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#define CAR_mmDP1_DP_MSE_SAT1 0x4bd3
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#define CAR_mmDP2_DP_MSE_SAT1 0x4cd3
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#define CAR_mmDP3_DP_MSE_SAT1 0x4dd3
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#define CAR_mmDP4_DP_MSE_SAT1 0x4ed3
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#define CAR_mmDP5_DP_MSE_SAT1 0x4fd3
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#define CAR_mmDP6_DP_MSE_SAT1 0x54d3
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#define CAR_mmDP7_DP_MSE_SAT1 0x56d3
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#define CAR_mmDP8_DP_MSE_SAT1 0x57d3
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#define CAR_mmDP_MSE_SAT2 0x4ad4
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#define CAR_mmDP0_DP_MSE_SAT2 0x4ad4
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#define CAR_mmDP1_DP_MSE_SAT2 0x4bd4
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#define CAR_mmDP2_DP_MSE_SAT2 0x4cd4
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#define CAR_mmDP3_DP_MSE_SAT2 0x4dd4
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#define CAR_mmDP4_DP_MSE_SAT2 0x4ed4
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#define CAR_mmDP5_DP_MSE_SAT2 0x4fd4
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#define CAR_mmDP6_DP_MSE_SAT2 0x54d4
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#define CAR_mmDP7_DP_MSE_SAT2 0x56d4
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#define CAR_mmDP8_DP_MSE_SAT2 0x57d4
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#define CAR_mmDP_MSE_SAT_UPDATE 0x4ad5
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#define CAR_mmDP0_DP_MSE_SAT_UPDATE 0x4ad5
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#define CAR_mmDP1_DP_MSE_SAT_UPDATE 0x4bd5
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#define CAR_mmDP2_DP_MSE_SAT_UPDATE 0x4cd5
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#define CAR_mmDP3_DP_MSE_SAT_UPDATE 0x4dd5
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#define CAR_mmDP4_DP_MSE_SAT_UPDATE 0x4ed5
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#define CAR_mmDP5_DP_MSE_SAT_UPDATE 0x4fd5
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#define CAR_mmDP6_DP_MSE_SAT_UPDATE 0x54d5
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#define CAR_mmDP7_DP_MSE_SAT_UPDATE 0x56d5
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#define CAR_mmDP8_DP_MSE_SAT_UPDATE 0x57d5
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#define CAR_mmDP_MSE_LINK_TIMING 0x4ad6
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#define CAR_mmDP0_DP_MSE_LINK_TIMING 0x4ad6
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#define CAR_mmDP1_DP_MSE_LINK_TIMING 0x4bd6
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#define CAR_mmDP2_DP_MSE_LINK_TIMING 0x4cd6
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#define CAR_mmDP3_DP_MSE_LINK_TIMING 0x4dd6
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#define CAR_mmDP4_DP_MSE_LINK_TIMING 0x4ed6
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#define CAR_mmDP5_DP_MSE_LINK_TIMING 0x4fd6
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#define CAR_mmDP6_DP_MSE_LINK_TIMING 0x54d6
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#define CAR_mmDP7_DP_MSE_LINK_TIMING 0x56d6
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#define CAR_mmDP8_DP_MSE_LINK_TIMING 0x57d6
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#define CAR_mmDP_MSE_MISC_CNTL 0x4ad7
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#define CAR_mmDP0_DP_MSE_MISC_CNTL 0x4ad7
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#define CAR_mmDP1_DP_MSE_MISC_CNTL 0x4bd7
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#define CAR_mmDP2_DP_MSE_MISC_CNTL 0x4cd7
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#define CAR_mmDP3_DP_MSE_MISC_CNTL 0x4dd7
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#define CAR_mmDP4_DP_MSE_MISC_CNTL 0x4ed7
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#define CAR_mmDP5_DP_MSE_MISC_CNTL 0x4fd7
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#define CAR_mmDP6_DP_MSE_MISC_CNTL 0x54d7
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#define CAR_mmDP7_DP_MSE_MISC_CNTL 0x56d7
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#define CAR_mmDP8_DP_MSE_MISC_CNTL 0x57d7
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#define CAR_mmDP_TEST_DEBUG_INDEX 0x4ad8
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#define CAR_mmDP0_DP_TEST_DEBUG_INDEX 0x4ad8
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#define CAR_mmDP1_DP_TEST_DEBUG_INDEX 0x4bd8
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#define CAR_mmDP2_DP_TEST_DEBUG_INDEX 0x4cd8
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#define CAR_mmDP3_DP_TEST_DEBUG_INDEX 0x4dd8
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#define CAR_mmDP4_DP_TEST_DEBUG_INDEX 0x4ed8
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#define CAR_mmDP5_DP_TEST_DEBUG_INDEX 0x4fd8
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#define CAR_mmDP6_DP_TEST_DEBUG_INDEX 0x54d8
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#define CAR_mmDP7_DP_TEST_DEBUG_INDEX 0x56d8
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#define CAR_mmDP8_DP_TEST_DEBUG_INDEX 0x57d8
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#define CAR_mmDP_TEST_DEBUG_DATA 0x4ad9
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#define CAR_mmDP0_DP_TEST_DEBUG_DATA 0x4ad9
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#define CAR_mmDP1_DP_TEST_DEBUG_DATA 0x4bd9
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#define CAR_mmDP2_DP_TEST_DEBUG_DATA 0x4cd9
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#define CAR_mmDP3_DP_TEST_DEBUG_DATA 0x4dd9
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#define CAR_mmDP4_DP_TEST_DEBUG_DATA 0x4ed9
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#define CAR_mmDP5_DP_TEST_DEBUG_DATA 0x4fd9
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#define CAR_mmDP6_DP_TEST_DEBUG_DATA 0x54d9
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#define CAR_mmDP7_DP_TEST_DEBUG_DATA 0x56d9
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#define CAR_mmDP8_DP_TEST_DEBUG_DATA 0x57d9
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#define CAR_mmDP_FE_TEST_DEBUG_INDEX 0x4ada
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#define CAR_mmDP0_DP_FE_TEST_DEBUG_INDEX 0x4ada
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#define CAR_mmDP1_DP_FE_TEST_DEBUG_INDEX 0x4bda
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#define CAR_mmDP2_DP_FE_TEST_DEBUG_INDEX 0x4cda
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#define CAR_mmDP3_DP_FE_TEST_DEBUG_INDEX 0x4dda
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#define CAR_mmDP4_DP_FE_TEST_DEBUG_INDEX 0x4eda
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#define CAR_mmDP5_DP_FE_TEST_DEBUG_INDEX 0x4fda
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#define CAR_mmDP6_DP_FE_TEST_DEBUG_INDEX 0x54da
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#define CAR_mmDP7_DP_FE_TEST_DEBUG_INDEX 0x56da
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#define CAR_mmDP8_DP_FE_TEST_DEBUG_INDEX 0x57da
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#define CAR_mmDP_FE_TEST_DEBUG_DATA 0x4adb
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#define CAR_mmDP0_DP_FE_TEST_DEBUG_DATA 0x4adb
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#define CAR_mmDP1_DP_FE_TEST_DEBUG_DATA 0x4bdb
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#define CAR_mmDP2_DP_FE_TEST_DEBUG_DATA 0x4cdb
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#define CAR_mmDP3_DP_FE_TEST_DEBUG_DATA 0x4ddb
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#define CAR_mmDP4_DP_FE_TEST_DEBUG_DATA 0x4edb
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#define CAR_mmDP5_DP_FE_TEST_DEBUG_DATA 0x4fdb
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#define CAR_mmDP6_DP_FE_TEST_DEBUG_DATA 0x54db
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#define CAR_mmDP7_DP_FE_TEST_DEBUG_DATA 0x56db
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#define CAR_mmDP8_DP_FE_TEST_DEBUG_DATA 0x57db
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#define CAR_mmAUX_CONTROL 0x5c00
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#define CAR_mmDP_AUX0_AUX_CONTROL 0x5c00
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#define CAR_mmDP_AUX1_AUX_CONTROL 0x5c1c
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#define CAR_mmDP_AUX2_AUX_CONTROL 0x5c38
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#define CAR_mmDP_AUX3_AUX_CONTROL 0x5c54
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#define CAR_mmDP_AUX4_AUX_CONTROL 0x5c70
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#define CAR_mmDP_AUX5_AUX_CONTROL 0x5c8c
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#define CAR_mmAUX_SW_CONTROL 0x5c01
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#define CAR_mmDP_AUX0_AUX_SW_CONTROL 0x5c01
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#define CAR_mmDP_AUX1_AUX_SW_CONTROL 0x5c1d
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#define CAR_mmDP_AUX2_AUX_SW_CONTROL 0x5c39
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#define CAR_mmDP_AUX3_AUX_SW_CONTROL 0x5c55
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#define CAR_mmDP_AUX4_AUX_SW_CONTROL 0x5c71
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#define CAR_mmDP_AUX5_AUX_SW_CONTROL 0x5c8d
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#define CAR_mmAUX_ARB_CONTROL 0x5c02
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#define CAR_mmDP_AUX0_AUX_ARB_CONTROL 0x5c02
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#define CAR_mmDP_AUX1_AUX_ARB_CONTROL 0x5c1e
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#define CAR_mmDP_AUX2_AUX_ARB_CONTROL 0x5c3a
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#define CAR_mmDP_AUX3_AUX_ARB_CONTROL 0x5c56
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#define CAR_mmDP_AUX4_AUX_ARB_CONTROL 0x5c72
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#define CAR_mmDP_AUX5_AUX_ARB_CONTROL 0x5c8e
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#define CAR_mmAUX_INTERRUPT_CONTROL 0x5c03
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#define CAR_mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x5c03
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#define CAR_mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x5c1f
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#define CAR_mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x5c3b
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#define CAR_mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x5c57
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#define CAR_mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x5c73
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#define CAR_mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x5c8f
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#define CAR_mmAUX_SW_STATUS 0x5c04
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#define CAR_mmDP_AUX0_AUX_SW_STATUS 0x5c04
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#define CAR_mmDP_AUX1_AUX_SW_STATUS 0x5c20
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#define CAR_mmDP_AUX2_AUX_SW_STATUS 0x5c3c
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#define CAR_mmDP_AUX3_AUX_SW_STATUS 0x5c58
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#define CAR_mmDP_AUX4_AUX_SW_STATUS 0x5c74
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#define CAR_mmDP_AUX5_AUX_SW_STATUS 0x5c90
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#define CAR_mmAUX_LS_STATUS 0x5c05
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#define CAR_mmDP_AUX0_AUX_LS_STATUS 0x5c05
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#define CAR_mmDP_AUX1_AUX_LS_STATUS 0x5c21
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#define CAR_mmDP_AUX2_AUX_LS_STATUS 0x5c3d
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#define CAR_mmDP_AUX3_AUX_LS_STATUS 0x5c59
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#define CAR_mmDP_AUX4_AUX_LS_STATUS 0x5c75
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#define CAR_mmDP_AUX5_AUX_LS_STATUS 0x5c91
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#define CAR_mmAUX_SW_DATA 0x5c06
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#define CAR_mmDP_AUX0_AUX_SW_DATA 0x5c06
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#define CAR_mmDP_AUX1_AUX_SW_DATA 0x5c22
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#define CAR_mmDP_AUX2_AUX_SW_DATA 0x5c3e
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#define CAR_mmDP_AUX3_AUX_SW_DATA 0x5c5a
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#define CAR_mmDP_AUX4_AUX_SW_DATA 0x5c76
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#define CAR_mmDP_AUX5_AUX_SW_DATA 0x5c92
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#define CAR_mmAUX_LS_DATA 0x5c07
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#define CAR_mmDP_AUX0_AUX_LS_DATA 0x5c07
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#define CAR_mmDP_AUX1_AUX_LS_DATA 0x5c23
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#define CAR_mmDP_AUX2_AUX_LS_DATA 0x5c3f
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#define CAR_mmDP_AUX3_AUX_LS_DATA 0x5c5b
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#define CAR_mmDP_AUX4_AUX_LS_DATA 0x5c77
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#define CAR_mmDP_AUX5_AUX_LS_DATA 0x5c93
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#define CAR_mmAUX_DPHY_TX_REF_CONTROL 0x5c08
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#define CAR_mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x5c08
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#define CAR_mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x5c24
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#define CAR_mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x5c40
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#define CAR_mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x5c5c
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#define CAR_mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x5c78
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#define CAR_mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x5c94
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#define CAR_mmAUX_DPHY_TX_CONTROL 0x5c09
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#define CAR_mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x5c09
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#define CAR_mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x5c25
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#define CAR_mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x5c41
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#define CAR_mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x5c5d
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#define CAR_mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x5c79
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#define CAR_mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x5c95
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#define CAR_mmAUX_DPHY_RX_CONTROL0 0x5c0a
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#define CAR_mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x5c0a
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#define CAR_mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x5c26
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#define CAR_mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x5c42
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#define CAR_mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x5c5e
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#define CAR_mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x5c7a
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#define CAR_mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x5c96
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#define CAR_mmAUX_DPHY_RX_CONTROL1 0x5c0b
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#define CAR_mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x5c0b
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#define CAR_mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x5c27
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#define CAR_mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x5c43
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#define CAR_mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x5c5f
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#define CAR_mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x5c7b
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#define CAR_mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x5c97
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#define CAR_mmAUX_DPHY_TX_STATUS 0x5c0c
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#define CAR_mmDP_AUX0_AUX_DPHY_TX_STATUS 0x5c0c
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#define CAR_mmDP_AUX1_AUX_DPHY_TX_STATUS 0x5c28
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#define CAR_mmDP_AUX2_AUX_DPHY_TX_STATUS 0x5c44
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#define CAR_mmDP_AUX3_AUX_DPHY_TX_STATUS 0x5c60
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#define CAR_mmDP_AUX4_AUX_DPHY_TX_STATUS 0x5c7c
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#define CAR_mmDP_AUX5_AUX_DPHY_TX_STATUS 0x5c98
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#define CAR_mmAUX_DPHY_RX_STATUS 0x5c0d
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#define CAR_mmDP_AUX0_AUX_DPHY_RX_STATUS 0x5c0d
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#define CAR_mmDP_AUX1_AUX_DPHY_RX_STATUS 0x5c29
|
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#define CAR_mmDP_AUX2_AUX_DPHY_RX_STATUS 0x5c45
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#define CAR_mmDP_AUX3_AUX_DPHY_RX_STATUS 0x5c61
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#define CAR_mmDP_AUX4_AUX_DPHY_RX_STATUS 0x5c7d
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#define CAR_mmDP_AUX5_AUX_DPHY_RX_STATUS 0x5c99
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#define CAR_mmAUX_GTC_SYNC_CONTROL 0x5c0e
|
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#define CAR_mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x5c0e
|
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#define CAR_mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x5c2a
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#define CAR_mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x5c46
|
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#define CAR_mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x5c62
|
|
#define CAR_mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x5c7e
|
|
#define CAR_mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x5c9a
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|
#define CAR_mmAUX_GTC_SYNC_ERROR_CONTROL 0x5c0f
|
|
#define CAR_mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x5c0f
|
|
#define CAR_mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x5c2b
|
|
#define CAR_mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x5c47
|
|
#define CAR_mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x5c63
|
|
#define CAR_mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x5c7f
|
|
#define CAR_mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x5c9b
|
|
#define CAR_mmAUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10
|
|
#define CAR_mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c10
|
|
#define CAR_mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c2c
|
|
#define CAR_mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c48
|
|
#define CAR_mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c64
|
|
#define CAR_mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c80
|
|
#define CAR_mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x5c9c
|
|
#define CAR_mmAUX_GTC_SYNC_STATUS 0x5c11
|
|
#define CAR_mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x5c11
|
|
#define CAR_mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x5c2d
|
|
#define CAR_mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x5c49
|
|
#define CAR_mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x5c65
|
|
#define CAR_mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x5c81
|
|
#define CAR_mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x5c9d
|
|
#define CAR_mmAUX_GTC_SYNC_DATA 0x5c12
|
|
#define CAR_mmDP_AUX0_AUX_GTC_SYNC_DATA 0x5c12
|
|
#define CAR_mmDP_AUX1_AUX_GTC_SYNC_DATA 0x5c2e
|
|
#define CAR_mmDP_AUX2_AUX_GTC_SYNC_DATA 0x5c4a
|
|
#define CAR_mmDP_AUX3_AUX_GTC_SYNC_DATA 0x5c66
|
|
#define CAR_mmDP_AUX4_AUX_GTC_SYNC_DATA 0x5c82
|
|
#define CAR_mmDP_AUX5_AUX_GTC_SYNC_DATA 0x5c9e
|
|
#define CAR_mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13
|
|
#define CAR_mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c13
|
|
#define CAR_mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c2f
|
|
#define CAR_mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c4b
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#define CAR_mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c67
|
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#define CAR_mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c83
|
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#define CAR_mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE 0x5c9f
|
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#define CAR_mmAUX_TEST_DEBUG_INDEX 0x5c14
|
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#define CAR_mmDP_AUX0_AUX_TEST_DEBUG_INDEX 0x5c14
|
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#define CAR_mmDP_AUX1_AUX_TEST_DEBUG_INDEX 0x5c30
|
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#define CAR_mmDP_AUX2_AUX_TEST_DEBUG_INDEX 0x5c4c
|
|
#define CAR_mmDP_AUX3_AUX_TEST_DEBUG_INDEX 0x5c68
|
|
#define CAR_mmDP_AUX4_AUX_TEST_DEBUG_INDEX 0x5c84
|
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#define CAR_mmDP_AUX5_AUX_TEST_DEBUG_INDEX 0x5ca0
|
|
#define CAR_mmAUX_TEST_DEBUG_DATA 0x5c15
|
|
#define CAR_mmDP_AUX0_AUX_TEST_DEBUG_DATA 0x5c15
|
|
#define CAR_mmDP_AUX1_AUX_TEST_DEBUG_DATA 0x5c31
|
|
#define CAR_mmDP_AUX2_AUX_TEST_DEBUG_DATA 0x5c4d
|
|
#define CAR_mmDP_AUX3_AUX_TEST_DEBUG_DATA 0x5c69
|
|
#define CAR_mmDP_AUX4_AUX_TEST_DEBUG_DATA 0x5c85
|
|
#define CAR_mmDP_AUX5_AUX_TEST_DEBUG_DATA 0x5ca1
|
|
#define CAR_ixDP_AUX_DEBUG_A 0x10
|
|
#define CAR_ixDP_AUX_DEBUG_B 0x11
|
|
#define CAR_ixDP_AUX_DEBUG_C 0x12
|
|
#define CAR_ixDP_AUX_DEBUG_D 0x13
|
|
#define CAR_ixDP_AUX_DEBUG_E 0x14
|
|
#define CAR_ixDP_AUX_DEBUG_F 0x15
|
|
#define CAR_ixDP_AUX_DEBUG_G 0x16
|
|
#define CAR_ixDP_AUX_DEBUG_H 0x17
|
|
#define CAR_ixDP_AUX_DEBUG_I 0x18
|
|
#define CAR_ixDP_AUX_DEBUG_J 0x19
|
|
#define CAR_ixDP_AUX_DEBUG_K 0x1a
|
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#define CAR_ixDP_AUX_DEBUG_L 0x1b
|
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#define CAR_ixDP_AUX_DEBUG_M 0x1c
|
|
#define CAR_ixDP_AUX_DEBUG_N 0x1d
|
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#define CAR_ixDP_AUX_DEBUG_O 0x1e
|
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#define CAR_ixDP_AUX_DEBUG_P 0x1f
|
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#define CAR_ixDP_AUX_DEBUG_Q 0x20
|
|
#define CAR_mmDVO_ENABLE 0x16a0
|
|
#define CAR_mmDVO_SOURCE_SELECT 0x16a1
|
|
#define CAR_mmDVO_OUTPUT 0x16a2
|
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#define CAR_mmDVO_CONTROL 0x16a3
|
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#define CAR_mmDVO_CRC_EN 0x16a4
|
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#define CAR_mmDVO_CRC2_SIG_MASK 0x16a5
|
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#define CAR_mmDVO_CRC2_SIG_RESULT 0x16a6
|
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#define CAR_mmDVO_FIFO_ERROR_STATUS 0x16a7
|
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#define CAR_mmDVO_TEST_DEBUG_INDEX 0x16a8
|
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#define CAR_mmDVO_TEST_DEBUG_DATA 0x16a9
|
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#define CAR_mmFBC_CNTL 0x280
|
|
#define CAR_mmFBC_IDLE_MASK 0x281
|
|
#define CAR_mmFBC_IDLE_FORCE_CLEAR_MASK 0x282
|
|
#define CAR_mmFBC_START_STOP_DELAY 0x283
|
|
#define CAR_mmFBC_COMP_CNTL 0x284
|
|
#define CAR_mmFBC_COMP_MODE 0x285
|
|
#define CAR_mmFBC_DEBUG0 0x286
|
|
#define CAR_mmFBC_DEBUG1 0x287
|
|
#define CAR_mmFBC_DEBUG2 0x288
|
|
#define CAR_mmFBC_IND_LUT0 0x289
|
|
#define CAR_mmFBC_IND_LUT1 0x28a
|
|
#define CAR_mmFBC_IND_LUT2 0x28b
|
|
#define CAR_mmFBC_IND_LUT3 0x28c
|
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#define CAR_mmFBC_IND_LUT4 0x28d
|
|
#define CAR_mmFBC_IND_LUT5 0x28e
|
|
#define CAR_mmFBC_IND_LUT6 0x28f
|
|
#define CAR_mmFBC_IND_LUT7 0x290
|
|
#define CAR_mmFBC_IND_LUT8 0x291
|
|
#define CAR_mmFBC_IND_LUT9 0x292
|
|
#define CAR_mmFBC_IND_LUT10 0x293
|
|
#define CAR_mmFBC_IND_LUT11 0x294
|
|
#define CAR_mmFBC_IND_LUT12 0x295
|
|
#define CAR_mmFBC_IND_LUT13 0x296
|
|
#define CAR_mmFBC_IND_LUT14 0x297
|
|
#define CAR_mmFBC_IND_LUT15 0x298
|
|
#define CAR_mmFBC_CSM_REGION_OFFSET_01 0x299
|
|
#define CAR_mmFBC_CSM_REGION_OFFSET_23 0x29a
|
|
#define CAR_mmFBC_CLIENT_REGION_MASK 0x29b
|
|
#define CAR_mmFBC_DEBUG_COMP 0x29c
|
|
#define CAR_mmFBC_DEBUG_CSR 0x29d
|
|
#define CAR_mmFBC_DEBUG_CSR_RDATA 0x29e
|
|
#define CAR_mmFBC_DEBUG_CSR_WDATA 0x29f
|
|
#define CAR_mmFBC_DEBUG_CSR_RDATA_HI 0x2a0
|
|
#define CAR_mmFBC_DEBUG_CSR_WDATA_HI 0x2a1
|
|
#define CAR_mmFBC_MISC 0x2a2
|
|
#define CAR_mmFBC_STATUS 0x2a3
|
|
#define CAR_mmFBC_TEST_DEBUG_INDEX 0x2a4
|
|
#define CAR_mmFBC_TEST_DEBUG_DATA 0x2a5
|
|
#define CAR_mmFMT_CLAMP_COMPONENT_R 0x1be8
|
|
#define CAR_mmFMT0_FMT_CLAMP_COMPONENT_R 0x1be8
|
|
#define CAR_mmFMT1_FMT_CLAMP_COMPONENT_R 0x1de8
|
|
#define CAR_mmFMT2_FMT_CLAMP_COMPONENT_R 0x1fe8
|
|
#define CAR_mmFMT3_FMT_CLAMP_COMPONENT_R 0x41e8
|
|
#define CAR_mmFMT4_FMT_CLAMP_COMPONENT_R 0x43e8
|
|
#define CAR_mmFMT5_FMT_CLAMP_COMPONENT_R 0x45e8
|
|
#define CAR_mmFMT_CLAMP_COMPONENT_G 0x1be9
|
|
#define CAR_mmFMT0_FMT_CLAMP_COMPONENT_G 0x1be9
|
|
#define CAR_mmFMT1_FMT_CLAMP_COMPONENT_G 0x1de9
|
|
#define CAR_mmFMT2_FMT_CLAMP_COMPONENT_G 0x1fe9
|
|
#define CAR_mmFMT3_FMT_CLAMP_COMPONENT_G 0x41e9
|
|
#define CAR_mmFMT4_FMT_CLAMP_COMPONENT_G 0x43e9
|
|
#define CAR_mmFMT5_FMT_CLAMP_COMPONENT_G 0x45e9
|
|
#define CAR_mmFMT_CLAMP_COMPONENT_B 0x1bea
|
|
#define CAR_mmFMT0_FMT_CLAMP_COMPONENT_B 0x1bea
|
|
#define CAR_mmFMT1_FMT_CLAMP_COMPONENT_B 0x1dea
|
|
#define CAR_mmFMT2_FMT_CLAMP_COMPONENT_B 0x1fea
|
|
#define CAR_mmFMT3_FMT_CLAMP_COMPONENT_B 0x41ea
|
|
#define CAR_mmFMT4_FMT_CLAMP_COMPONENT_B 0x43ea
|
|
#define CAR_mmFMT5_FMT_CLAMP_COMPONENT_B 0x45ea
|
|
#define CAR_mmFMT_DYNAMIC_EXP_CNTL 0x1bed
|
|
#define CAR_mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1bed
|
|
#define CAR_mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1ded
|
|
#define CAR_mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x1fed
|
|
#define CAR_mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x41ed
|
|
#define CAR_mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x43ed
|
|
#define CAR_mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x45ed
|
|
#define CAR_mmFMT_CONTROL 0x1bee
|
|
#define CAR_mmFMT0_FMT_CONTROL 0x1bee
|
|
#define CAR_mmFMT1_FMT_CONTROL 0x1dee
|
|
#define CAR_mmFMT2_FMT_CONTROL 0x1fee
|
|
#define CAR_mmFMT3_FMT_CONTROL 0x41ee
|
|
#define CAR_mmFMT4_FMT_CONTROL 0x43ee
|
|
#define CAR_mmFMT5_FMT_CONTROL 0x45ee
|
|
#define CAR_mmFMT_BIT_DEPTH_CONTROL 0x1bf2
|
|
#define CAR_mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1bf2
|
|
#define CAR_mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1df2
|
|
#define CAR_mmFMT2_FMT_BIT_DEPTH_CONTROL 0x1ff2
|
|
#define CAR_mmFMT3_FMT_BIT_DEPTH_CONTROL 0x41f2
|
|
#define CAR_mmFMT4_FMT_BIT_DEPTH_CONTROL 0x43f2
|
|
#define CAR_mmFMT5_FMT_BIT_DEPTH_CONTROL 0x45f2
|
|
#define CAR_mmFMT_DITHER_RAND_R_SEED 0x1bf3
|
|
#define CAR_mmFMT0_FMT_DITHER_RAND_R_SEED 0x1bf3
|
|
#define CAR_mmFMT1_FMT_DITHER_RAND_R_SEED 0x1df3
|
|
#define CAR_mmFMT2_FMT_DITHER_RAND_R_SEED 0x1ff3
|
|
#define CAR_mmFMT3_FMT_DITHER_RAND_R_SEED 0x41f3
|
|
#define CAR_mmFMT4_FMT_DITHER_RAND_R_SEED 0x43f3
|
|
#define CAR_mmFMT5_FMT_DITHER_RAND_R_SEED 0x45f3
|
|
#define CAR_mmFMT_DITHER_RAND_G_SEED 0x1bf4
|
|
#define CAR_mmFMT0_FMT_DITHER_RAND_G_SEED 0x1bf4
|
|
#define CAR_mmFMT1_FMT_DITHER_RAND_G_SEED 0x1df4
|
|
#define CAR_mmFMT2_FMT_DITHER_RAND_G_SEED 0x1ff4
|
|
#define CAR_mmFMT3_FMT_DITHER_RAND_G_SEED 0x41f4
|
|
#define CAR_mmFMT4_FMT_DITHER_RAND_G_SEED 0x43f4
|
|
#define CAR_mmFMT5_FMT_DITHER_RAND_G_SEED 0x45f4
|
|
#define CAR_mmFMT_DITHER_RAND_B_SEED 0x1bf5
|
|
#define CAR_mmFMT0_FMT_DITHER_RAND_B_SEED 0x1bf5
|
|
#define CAR_mmFMT1_FMT_DITHER_RAND_B_SEED 0x1df5
|
|
#define CAR_mmFMT2_FMT_DITHER_RAND_B_SEED 0x1ff5
|
|
#define CAR_mmFMT3_FMT_DITHER_RAND_B_SEED 0x41f5
|
|
#define CAR_mmFMT4_FMT_DITHER_RAND_B_SEED 0x43f5
|
|
#define CAR_mmFMT5_FMT_DITHER_RAND_B_SEED 0x45f5
|
|
#define CAR_mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6
|
|
#define CAR_mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1bf6
|
|
#define CAR_mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1df6
|
|
#define CAR_mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1ff6
|
|
#define CAR_mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41f6
|
|
#define CAR_mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x43f6
|
|
#define CAR_mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x45f6
|
|
#define CAR_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7
|
|
#define CAR_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1bf7
|
|
#define CAR_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1df7
|
|
#define CAR_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1ff7
|
|
#define CAR_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41f7
|
|
#define CAR_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x43f7
|
|
#define CAR_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x45f7
|
|
#define CAR_mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8
|
|
#define CAR_mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1bf8
|
|
#define CAR_mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1df8
|
|
#define CAR_mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1ff8
|
|
#define CAR_mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41f8
|
|
#define CAR_mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x43f8
|
|
#define CAR_mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x45f8
|
|
#define CAR_mmFMT_CLAMP_CNTL 0x1bf9
|
|
#define CAR_mmFMT0_FMT_CLAMP_CNTL 0x1bf9
|
|
#define CAR_mmFMT1_FMT_CLAMP_CNTL 0x1df9
|
|
#define CAR_mmFMT2_FMT_CLAMP_CNTL 0x1ff9
|
|
#define CAR_mmFMT3_FMT_CLAMP_CNTL 0x41f9
|
|
#define CAR_mmFMT4_FMT_CLAMP_CNTL 0x43f9
|
|
#define CAR_mmFMT5_FMT_CLAMP_CNTL 0x45f9
|
|
#define CAR_mmFMT_CRC_CNTL 0x1bfa
|
|
#define CAR_mmFMT0_FMT_CRC_CNTL 0x1bfa
|
|
#define CAR_mmFMT1_FMT_CRC_CNTL 0x1dfa
|
|
#define CAR_mmFMT2_FMT_CRC_CNTL 0x1ffa
|
|
#define CAR_mmFMT3_FMT_CRC_CNTL 0x41fa
|
|
#define CAR_mmFMT4_FMT_CRC_CNTL 0x43fa
|
|
#define CAR_mmFMT5_FMT_CRC_CNTL 0x45fa
|
|
#define CAR_mmFMT_CRC_SIG_RED_GREEN_MASK 0x1bfb
|
|
#define CAR_mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1bfb
|
|
#define CAR_mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1dfb
|
|
#define CAR_mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x1ffb
|
|
#define CAR_mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x41fb
|
|
#define CAR_mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x43fb
|
|
#define CAR_mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x45fb
|
|
#define CAR_mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc
|
|
#define CAR_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1bfc
|
|
#define CAR_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1dfc
|
|
#define CAR_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1ffc
|
|
#define CAR_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41fc
|
|
#define CAR_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x43fc
|
|
#define CAR_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x45fc
|
|
#define CAR_mmFMT_CRC_SIG_RED_GREEN 0x1bfd
|
|
#define CAR_mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1bfd
|
|
#define CAR_mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1dfd
|
|
#define CAR_mmFMT2_FMT_CRC_SIG_RED_GREEN 0x1ffd
|
|
#define CAR_mmFMT3_FMT_CRC_SIG_RED_GREEN 0x41fd
|
|
#define CAR_mmFMT4_FMT_CRC_SIG_RED_GREEN 0x43fd
|
|
#define CAR_mmFMT5_FMT_CRC_SIG_RED_GREEN 0x45fd
|
|
#define CAR_mmFMT_CRC_SIG_BLUE_CONTROL 0x1bfe
|
|
#define CAR_mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1bfe
|
|
#define CAR_mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1dfe
|
|
#define CAR_mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x1ffe
|
|
#define CAR_mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x41fe
|
|
#define CAR_mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x43fe
|
|
#define CAR_mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x45fe
|
|
#define CAR_mmFMT_DEBUG_CNTL 0x1bff
|
|
#define CAR_mmFMT0_FMT_DEBUG_CNTL 0x1bff
|
|
#define CAR_mmFMT1_FMT_DEBUG_CNTL 0x1dff
|
|
#define CAR_mmFMT2_FMT_DEBUG_CNTL 0x1fff
|
|
#define CAR_mmFMT3_FMT_DEBUG_CNTL 0x41ff
|
|
#define CAR_mmFMT4_FMT_DEBUG_CNTL 0x43ff
|
|
#define CAR_mmFMT5_FMT_DEBUG_CNTL 0x45ff
|
|
#define CAR_mmFMT_TEST_DEBUG_INDEX 0x1beb
|
|
#define CAR_mmFMT0_FMT_TEST_DEBUG_INDEX 0x1beb
|
|
#define CAR_mmFMT1_FMT_TEST_DEBUG_INDEX 0x1deb
|
|
#define CAR_mmFMT2_FMT_TEST_DEBUG_INDEX 0x1feb
|
|
#define CAR_mmFMT3_FMT_TEST_DEBUG_INDEX 0x41eb
|
|
#define CAR_mmFMT4_FMT_TEST_DEBUG_INDEX 0x43eb
|
|
#define CAR_mmFMT5_FMT_TEST_DEBUG_INDEX 0x45eb
|
|
#define CAR_mmFMT_TEST_DEBUG_DATA 0x1bec
|
|
#define CAR_mmFMT0_FMT_TEST_DEBUG_DATA 0x1bec
|
|
#define CAR_mmFMT1_FMT_TEST_DEBUG_DATA 0x1dec
|
|
#define CAR_mmFMT2_FMT_TEST_DEBUG_DATA 0x1fec
|
|
#define CAR_mmFMT3_FMT_TEST_DEBUG_DATA 0x41ec
|
|
#define CAR_mmFMT4_FMT_TEST_DEBUG_DATA 0x43ec
|
|
#define CAR_mmFMT5_FMT_TEST_DEBUG_DATA 0x45ec
|
|
#define CAR_ixFMT_DEBUG0 0x1
|
|
#define CAR_ixFMT_DEBUG1 0x2
|
|
#define CAR_ixFMT_DEBUG2 0x3
|
|
#define CAR_ixFMT_DEBUG_ID 0x0
|
|
#define CAR_mmLB_DATA_FORMAT 0x1ac0
|
|
#define CAR_mmLB0_LB_DATA_FORMAT 0x1ac0
|
|
#define CAR_mmLB1_LB_DATA_FORMAT 0x1cc0
|
|
#define CAR_mmLB2_LB_DATA_FORMAT 0x1ec0
|
|
#define CAR_mmLB3_LB_DATA_FORMAT 0x40c0
|
|
#define CAR_mmLB4_LB_DATA_FORMAT 0x42c0
|
|
#define CAR_mmLB5_LB_DATA_FORMAT 0x44c0
|
|
#define CAR_mmLB_MEMORY_CTRL 0x1ac1
|
|
#define CAR_mmLB0_LB_MEMORY_CTRL 0x1ac1
|
|
#define CAR_mmLB1_LB_MEMORY_CTRL 0x1cc1
|
|
#define CAR_mmLB2_LB_MEMORY_CTRL 0x1ec1
|
|
#define CAR_mmLB3_LB_MEMORY_CTRL 0x40c1
|
|
#define CAR_mmLB4_LB_MEMORY_CTRL 0x42c1
|
|
#define CAR_mmLB5_LB_MEMORY_CTRL 0x44c1
|
|
#define CAR_mmLB_MEMORY_SIZE_STATUS 0x1ac2
|
|
#define CAR_mmLB0_LB_MEMORY_SIZE_STATUS 0x1ac2
|
|
#define CAR_mmLB1_LB_MEMORY_SIZE_STATUS 0x1cc2
|
|
#define CAR_mmLB2_LB_MEMORY_SIZE_STATUS 0x1ec2
|
|
#define CAR_mmLB3_LB_MEMORY_SIZE_STATUS 0x40c2
|
|
#define CAR_mmLB4_LB_MEMORY_SIZE_STATUS 0x42c2
|
|
#define CAR_mmLB5_LB_MEMORY_SIZE_STATUS 0x44c2
|
|
#define CAR_mmLB_DESKTOP_HEIGHT 0x1ac3
|
|
#define CAR_mmLB0_LB_DESKTOP_HEIGHT 0x1ac3
|
|
#define CAR_mmLB1_LB_DESKTOP_HEIGHT 0x1cc3
|
|
#define CAR_mmLB2_LB_DESKTOP_HEIGHT 0x1ec3
|
|
#define CAR_mmLB3_LB_DESKTOP_HEIGHT 0x40c3
|
|
#define CAR_mmLB4_LB_DESKTOP_HEIGHT 0x42c3
|
|
#define CAR_mmLB5_LB_DESKTOP_HEIGHT 0x44c3
|
|
#define CAR_mmLB_VLINE_START_END 0x1ac4
|
|
#define CAR_mmLB0_LB_VLINE_START_END 0x1ac4
|
|
#define CAR_mmLB1_LB_VLINE_START_END 0x1cc4
|
|
#define CAR_mmLB2_LB_VLINE_START_END 0x1ec4
|
|
#define CAR_mmLB3_LB_VLINE_START_END 0x40c4
|
|
#define CAR_mmLB4_LB_VLINE_START_END 0x42c4
|
|
#define CAR_mmLB5_LB_VLINE_START_END 0x44c4
|
|
#define CAR_mmLB_VLINE2_START_END 0x1ac5
|
|
#define CAR_mmLB0_LB_VLINE2_START_END 0x1ac5
|
|
#define CAR_mmLB1_LB_VLINE2_START_END 0x1cc5
|
|
#define CAR_mmLB2_LB_VLINE2_START_END 0x1ec5
|
|
#define CAR_mmLB3_LB_VLINE2_START_END 0x40c5
|
|
#define CAR_mmLB4_LB_VLINE2_START_END 0x42c5
|
|
#define CAR_mmLB5_LB_VLINE2_START_END 0x44c5
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#define CAR_mmLB_V_COUNTER 0x1ac6
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#define CAR_mmLB0_LB_V_COUNTER 0x1ac6
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#define CAR_mmLB1_LB_V_COUNTER 0x1cc6
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#define CAR_mmLB2_LB_V_COUNTER 0x1ec6
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#define CAR_mmLB3_LB_V_COUNTER 0x40c6
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#define CAR_mmLB4_LB_V_COUNTER 0x42c6
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#define CAR_mmLB5_LB_V_COUNTER 0x44c6
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#define CAR_mmLB_SNAPSHOT_V_COUNTER 0x1ac7
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#define CAR_mmLB0_LB_SNAPSHOT_V_COUNTER 0x1ac7
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#define CAR_mmLB1_LB_SNAPSHOT_V_COUNTER 0x1cc7
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#define CAR_mmLB2_LB_SNAPSHOT_V_COUNTER 0x1ec7
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#define CAR_mmLB3_LB_SNAPSHOT_V_COUNTER 0x40c7
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#define CAR_mmLB4_LB_SNAPSHOT_V_COUNTER 0x42c7
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#define CAR_mmLB5_LB_SNAPSHOT_V_COUNTER 0x44c7
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#define CAR_mmLB_INTERRUPT_MASK 0x1ac8
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#define CAR_mmLB0_LB_INTERRUPT_MASK 0x1ac8
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#define CAR_mmLB1_LB_INTERRUPT_MASK 0x1cc8
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#define CAR_mmLB2_LB_INTERRUPT_MASK 0x1ec8
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#define CAR_mmLB3_LB_INTERRUPT_MASK 0x40c8
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#define CAR_mmLB4_LB_INTERRUPT_MASK 0x42c8
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#define CAR_mmLB5_LB_INTERRUPT_MASK 0x44c8
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#define CAR_mmLB_VLINE_STATUS 0x1ac9
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#define CAR_mmLB0_LB_VLINE_STATUS 0x1ac9
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#define CAR_mmLB1_LB_VLINE_STATUS 0x1cc9
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#define CAR_mmLB2_LB_VLINE_STATUS 0x1ec9
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#define CAR_mmLB3_LB_VLINE_STATUS 0x40c9
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#define CAR_mmLB4_LB_VLINE_STATUS 0x42c9
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#define CAR_mmLB5_LB_VLINE_STATUS 0x44c9
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#define CAR_mmLB_VLINE2_STATUS 0x1aca
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#define CAR_mmLB0_LB_VLINE2_STATUS 0x1aca
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#define CAR_mmLB1_LB_VLINE2_STATUS 0x1cca
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#define CAR_mmLB2_LB_VLINE2_STATUS 0x1eca
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#define CAR_mmLB3_LB_VLINE2_STATUS 0x40ca
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#define CAR_mmLB4_LB_VLINE2_STATUS 0x42ca
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#define CAR_mmLB5_LB_VLINE2_STATUS 0x44ca
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#define CAR_mmLB_VBLANK_STATUS 0x1acb
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#define CAR_mmLB0_LB_VBLANK_STATUS 0x1acb
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#define CAR_mmLB1_LB_VBLANK_STATUS 0x1ccb
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#define CAR_mmLB2_LB_VBLANK_STATUS 0x1ecb
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#define CAR_mmLB3_LB_VBLANK_STATUS 0x40cb
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#define CAR_mmLB4_LB_VBLANK_STATUS 0x42cb
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#define CAR_mmLB5_LB_VBLANK_STATUS 0x44cb
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#define CAR_mmLB_SYNC_RESET_SEL 0x1acc
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#define CAR_mmLB0_LB_SYNC_RESET_SEL 0x1acc
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#define CAR_mmLB1_LB_SYNC_RESET_SEL 0x1ccc
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#define CAR_mmLB2_LB_SYNC_RESET_SEL 0x1ecc
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#define CAR_mmLB3_LB_SYNC_RESET_SEL 0x40cc
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#define CAR_mmLB4_LB_SYNC_RESET_SEL 0x42cc
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#define CAR_mmLB5_LB_SYNC_RESET_SEL 0x44cc
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#define CAR_mmLB_BLACK_KEYER_R_CR 0x1acd
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#define CAR_mmLB0_LB_BLACK_KEYER_R_CR 0x1acd
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#define CAR_mmLB1_LB_BLACK_KEYER_R_CR 0x1ccd
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#define CAR_mmLB2_LB_BLACK_KEYER_R_CR 0x1ecd
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#define CAR_mmLB3_LB_BLACK_KEYER_R_CR 0x40cd
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#define CAR_mmLB4_LB_BLACK_KEYER_R_CR 0x42cd
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#define CAR_mmLB5_LB_BLACK_KEYER_R_CR 0x44cd
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#define CAR_mmLB_BLACK_KEYER_G_Y 0x1ace
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#define CAR_mmLB0_LB_BLACK_KEYER_G_Y 0x1ace
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#define CAR_mmLB1_LB_BLACK_KEYER_G_Y 0x1cce
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#define CAR_mmLB2_LB_BLACK_KEYER_G_Y 0x1ece
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#define CAR_mmLB3_LB_BLACK_KEYER_G_Y 0x40ce
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#define CAR_mmLB4_LB_BLACK_KEYER_G_Y 0x42ce
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#define CAR_mmLB5_LB_BLACK_KEYER_G_Y 0x44ce
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#define CAR_mmLB_BLACK_KEYER_B_CB 0x1acf
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#define CAR_mmLB0_LB_BLACK_KEYER_B_CB 0x1acf
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#define CAR_mmLB1_LB_BLACK_KEYER_B_CB 0x1ccf
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#define CAR_mmLB2_LB_BLACK_KEYER_B_CB 0x1ecf
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#define CAR_mmLB3_LB_BLACK_KEYER_B_CB 0x40cf
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#define CAR_mmLB4_LB_BLACK_KEYER_B_CB 0x42cf
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#define CAR_mmLB5_LB_BLACK_KEYER_B_CB 0x44cf
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#define CAR_mmLB_KEYER_COLOR_CTRL 0x1ad0
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#define CAR_mmLB0_LB_KEYER_COLOR_CTRL 0x1ad0
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#define CAR_mmLB1_LB_KEYER_COLOR_CTRL 0x1cd0
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#define CAR_mmLB2_LB_KEYER_COLOR_CTRL 0x1ed0
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#define CAR_mmLB3_LB_KEYER_COLOR_CTRL 0x40d0
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#define CAR_mmLB4_LB_KEYER_COLOR_CTRL 0x42d0
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#define CAR_mmLB5_LB_KEYER_COLOR_CTRL 0x44d0
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#define CAR_mmLB_KEYER_COLOR_R_CR 0x1ad1
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#define CAR_mmLB0_LB_KEYER_COLOR_R_CR 0x1ad1
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#define CAR_mmLB1_LB_KEYER_COLOR_R_CR 0x1cd1
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#define CAR_mmLB2_LB_KEYER_COLOR_R_CR 0x1ed1
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#define CAR_mmLB3_LB_KEYER_COLOR_R_CR 0x40d1
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#define CAR_mmLB4_LB_KEYER_COLOR_R_CR 0x42d1
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#define CAR_mmLB5_LB_KEYER_COLOR_R_CR 0x44d1
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#define CAR_mmLB_KEYER_COLOR_G_Y 0x1ad2
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#define CAR_mmLB0_LB_KEYER_COLOR_G_Y 0x1ad2
|
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#define CAR_mmLB1_LB_KEYER_COLOR_G_Y 0x1cd2
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#define CAR_mmLB2_LB_KEYER_COLOR_G_Y 0x1ed2
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#define CAR_mmLB3_LB_KEYER_COLOR_G_Y 0x40d2
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|
#define CAR_mmLB4_LB_KEYER_COLOR_G_Y 0x42d2
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#define CAR_mmLB5_LB_KEYER_COLOR_G_Y 0x44d2
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#define CAR_mmLB_KEYER_COLOR_B_CB 0x1ad3
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#define CAR_mmLB0_LB_KEYER_COLOR_B_CB 0x1ad3
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#define CAR_mmLB1_LB_KEYER_COLOR_B_CB 0x1cd3
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#define CAR_mmLB2_LB_KEYER_COLOR_B_CB 0x1ed3
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#define CAR_mmLB3_LB_KEYER_COLOR_B_CB 0x40d3
|
|
#define CAR_mmLB4_LB_KEYER_COLOR_B_CB 0x42d3
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|
#define CAR_mmLB5_LB_KEYER_COLOR_B_CB 0x44d3
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|
#define CAR_mmLB_KEYER_COLOR_REP_R_CR 0x1ad4
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|
#define CAR_mmLB0_LB_KEYER_COLOR_REP_R_CR 0x1ad4
|
|
#define CAR_mmLB1_LB_KEYER_COLOR_REP_R_CR 0x1cd4
|
|
#define CAR_mmLB2_LB_KEYER_COLOR_REP_R_CR 0x1ed4
|
|
#define CAR_mmLB3_LB_KEYER_COLOR_REP_R_CR 0x40d4
|
|
#define CAR_mmLB4_LB_KEYER_COLOR_REP_R_CR 0x42d4
|
|
#define CAR_mmLB5_LB_KEYER_COLOR_REP_R_CR 0x44d4
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|
#define CAR_mmLB_KEYER_COLOR_REP_G_Y 0x1ad5
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#define CAR_mmLB0_LB_KEYER_COLOR_REP_G_Y 0x1ad5
|
|
#define CAR_mmLB1_LB_KEYER_COLOR_REP_G_Y 0x1cd5
|
|
#define CAR_mmLB2_LB_KEYER_COLOR_REP_G_Y 0x1ed5
|
|
#define CAR_mmLB3_LB_KEYER_COLOR_REP_G_Y 0x40d5
|
|
#define CAR_mmLB4_LB_KEYER_COLOR_REP_G_Y 0x42d5
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|
#define CAR_mmLB5_LB_KEYER_COLOR_REP_G_Y 0x44d5
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|
#define CAR_mmLB_KEYER_COLOR_REP_B_CB 0x1ad6
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|
#define CAR_mmLB0_LB_KEYER_COLOR_REP_B_CB 0x1ad6
|
|
#define CAR_mmLB1_LB_KEYER_COLOR_REP_B_CB 0x1cd6
|
|
#define CAR_mmLB2_LB_KEYER_COLOR_REP_B_CB 0x1ed6
|
|
#define CAR_mmLB3_LB_KEYER_COLOR_REP_B_CB 0x40d6
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|
#define CAR_mmLB4_LB_KEYER_COLOR_REP_B_CB 0x42d6
|
|
#define CAR_mmLB5_LB_KEYER_COLOR_REP_B_CB 0x44d6
|
|
#define CAR_mmLB_BUFFER_LEVEL_STATUS 0x1ad7
|
|
#define CAR_mmLB0_LB_BUFFER_LEVEL_STATUS 0x1ad7
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|
#define CAR_mmLB1_LB_BUFFER_LEVEL_STATUS 0x1cd7
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#define CAR_mmLB2_LB_BUFFER_LEVEL_STATUS 0x1ed7
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|
#define CAR_mmLB3_LB_BUFFER_LEVEL_STATUS 0x40d7
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|
#define CAR_mmLB4_LB_BUFFER_LEVEL_STATUS 0x42d7
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#define CAR_mmLB5_LB_BUFFER_LEVEL_STATUS 0x44d7
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#define CAR_mmLB_BUFFER_URGENCY_CTRL 0x1ad8
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#define CAR_mmLB0_LB_BUFFER_URGENCY_CTRL 0x1ad8
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#define CAR_mmLB1_LB_BUFFER_URGENCY_CTRL 0x1cd8
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#define CAR_mmLB2_LB_BUFFER_URGENCY_CTRL 0x1ed8
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#define CAR_mmLB3_LB_BUFFER_URGENCY_CTRL 0x40d8
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#define CAR_mmLB4_LB_BUFFER_URGENCY_CTRL 0x42d8
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#define CAR_mmLB5_LB_BUFFER_URGENCY_CTRL 0x44d8
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#define CAR_mmLB_BUFFER_URGENCY_STATUS 0x1ad9
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#define CAR_mmLB0_LB_BUFFER_URGENCY_STATUS 0x1ad9
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#define CAR_mmLB1_LB_BUFFER_URGENCY_STATUS 0x1cd9
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#define CAR_mmLB2_LB_BUFFER_URGENCY_STATUS 0x1ed9
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#define CAR_mmLB3_LB_BUFFER_URGENCY_STATUS 0x40d9
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|
#define CAR_mmLB4_LB_BUFFER_URGENCY_STATUS 0x42d9
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#define CAR_mmLB5_LB_BUFFER_URGENCY_STATUS 0x44d9
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#define CAR_mmLB_BUFFER_STATUS 0x1ada
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#define CAR_mmLB0_LB_BUFFER_STATUS 0x1ada
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#define CAR_mmLB1_LB_BUFFER_STATUS 0x1cda
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|
#define CAR_mmLB2_LB_BUFFER_STATUS 0x1eda
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#define CAR_mmLB3_LB_BUFFER_STATUS 0x40da
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#define CAR_mmLB4_LB_BUFFER_STATUS 0x42da
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|
#define CAR_mmLB5_LB_BUFFER_STATUS 0x44da
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#define CAR_mmLB_NO_OUTSTANDING_REQ_STATUS 0x1adc
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|
#define CAR_mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1adc
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|
#define CAR_mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1cdc
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|
#define CAR_mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x1edc
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|
#define CAR_mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x40dc
|
|
#define CAR_mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x42dc
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|
#define CAR_mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x44dc
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|
#define CAR_mmMVP_AFR_FLIP_MODE 0x1ae0
|
|
#define CAR_mmLB0_MVP_AFR_FLIP_MODE 0x1ae0
|
|
#define CAR_mmLB1_MVP_AFR_FLIP_MODE 0x1ce0
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#define CAR_mmLB2_MVP_AFR_FLIP_MODE 0x1ee0
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|
#define CAR_mmLB3_MVP_AFR_FLIP_MODE 0x40e0
|
|
#define CAR_mmLB4_MVP_AFR_FLIP_MODE 0x42e0
|
|
#define CAR_mmLB5_MVP_AFR_FLIP_MODE 0x44e0
|
|
#define CAR_mmMVP_AFR_FLIP_FIFO_CNTL 0x1ae1
|
|
#define CAR_mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1ae1
|
|
#define CAR_mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1ce1
|
|
#define CAR_mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x1ee1
|
|
#define CAR_mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x40e1
|
|
#define CAR_mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x42e1
|
|
#define CAR_mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x44e1
|
|
#define CAR_mmMVP_FLIP_LINE_NUM_INSERT 0x1ae2
|
|
#define CAR_mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ae2
|
|
#define CAR_mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1ce2
|
|
#define CAR_mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x1ee2
|
|
#define CAR_mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x40e2
|
|
#define CAR_mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x42e2
|
|
#define CAR_mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x44e2
|
|
#define CAR_mmDC_MVP_LB_CONTROL 0x1ae3
|
|
#define CAR_mmLB0_DC_MVP_LB_CONTROL 0x1ae3
|
|
#define CAR_mmLB1_DC_MVP_LB_CONTROL 0x1ce3
|
|
#define CAR_mmLB2_DC_MVP_LB_CONTROL 0x1ee3
|
|
#define CAR_mmLB3_DC_MVP_LB_CONTROL 0x40e3
|
|
#define CAR_mmLB4_DC_MVP_LB_CONTROL 0x42e3
|
|
#define CAR_mmLB5_DC_MVP_LB_CONTROL 0x44e3
|
|
#define CAR_mmLB_DEBUG 0x1ae4
|
|
#define CAR_mmLB0_LB_DEBUG 0x1ae4
|
|
#define CAR_mmLB1_LB_DEBUG 0x1ce4
|
|
#define CAR_mmLB2_LB_DEBUG 0x1ee4
|
|
#define CAR_mmLB3_LB_DEBUG 0x40e4
|
|
#define CAR_mmLB4_LB_DEBUG 0x42e4
|
|
#define CAR_mmLB5_LB_DEBUG 0x44e4
|
|
#define CAR_mmLB_DEBUG2 0x1ae5
|
|
#define CAR_mmLB0_LB_DEBUG2 0x1ae5
|
|
#define CAR_mmLB1_LB_DEBUG2 0x1ce5
|
|
#define CAR_mmLB2_LB_DEBUG2 0x1ee5
|
|
#define CAR_mmLB3_LB_DEBUG2 0x40e5
|
|
#define CAR_mmLB4_LB_DEBUG2 0x42e5
|
|
#define CAR_mmLB5_LB_DEBUG2 0x44e5
|
|
#define CAR_mmLB_DEBUG3 0x1ae6
|
|
#define CAR_mmLB0_LB_DEBUG3 0x1ae6
|
|
#define CAR_mmLB1_LB_DEBUG3 0x1ce6
|
|
#define CAR_mmLB2_LB_DEBUG3 0x1ee6
|
|
#define CAR_mmLB3_LB_DEBUG3 0x40e6
|
|
#define CAR_mmLB4_LB_DEBUG3 0x42e6
|
|
#define CAR_mmLB5_LB_DEBUG3 0x44e6
|
|
#define CAR_mmLB_TEST_DEBUG_INDEX 0x1afe
|
|
#define CAR_mmLB0_LB_TEST_DEBUG_INDEX 0x1afe
|
|
#define CAR_mmLB1_LB_TEST_DEBUG_INDEX 0x1cfe
|
|
#define CAR_mmLB2_LB_TEST_DEBUG_INDEX 0x1efe
|
|
#define CAR_mmLB3_LB_TEST_DEBUG_INDEX 0x40fe
|
|
#define CAR_mmLB4_LB_TEST_DEBUG_INDEX 0x42fe
|
|
#define CAR_mmLB5_LB_TEST_DEBUG_INDEX 0x44fe
|
|
#define CAR_mmLB_TEST_DEBUG_DATA 0x1aff
|
|
#define CAR_mmLB0_LB_TEST_DEBUG_DATA 0x1aff
|
|
#define CAR_mmLB1_LB_TEST_DEBUG_DATA 0x1cff
|
|
#define CAR_mmLB2_LB_TEST_DEBUG_DATA 0x1eff
|
|
#define CAR_mmLB3_LB_TEST_DEBUG_DATA 0x40ff
|
|
#define CAR_mmLB4_LB_TEST_DEBUG_DATA 0x42ff
|
|
#define CAR_mmLB5_LB_TEST_DEBUG_DATA 0x44ff
|
|
#define CAR_mmLBV_DATA_FORMAT 0x463c
|
|
#define CAR_mmLBV_MEMORY_CTRL 0x463d
|
|
#define CAR_mmLBV_MEMORY_SIZE_STATUS 0x463e
|
|
#define CAR_mmLBV_DESKTOP_HEIGHT 0x463f
|
|
#define CAR_mmLBV_VLINE_START_END 0x4640
|
|
#define CAR_mmLBV_VLINE2_START_END 0x4641
|
|
#define CAR_mmLBV_V_COUNTER 0x4642
|
|
#define CAR_mmLBV_SNAPSHOT_V_COUNTER 0x4643
|
|
#define CAR_mmLBV_V_COUNTER_CHROMA 0x4644
|
|
#define CAR_mmLBV_SNAPSHOT_V_COUNTER_CHROMA 0x4645
|
|
#define CAR_mmLBV_INTERRUPT_MASK 0x4646
|
|
#define CAR_mmLBV_VLINE_STATUS 0x4647
|
|
#define CAR_mmLBV_VLINE2_STATUS 0x4648
|
|
#define CAR_mmLBV_VBLANK_STATUS 0x4649
|
|
#define CAR_mmLBV_SYNC_RESET_SEL 0x464a
|
|
#define CAR_mmLBV_BLACK_KEYER_R_CR 0x464b
|
|
#define CAR_mmLBV_BLACK_KEYER_G_Y 0x464c
|
|
#define CAR_mmLBV_BLACK_KEYER_B_CB 0x464d
|
|
#define CAR_mmLBV_KEYER_COLOR_CTRL 0x464e
|
|
#define CAR_mmLBV_KEYER_COLOR_R_CR 0x464f
|
|
#define CAR_mmLBV_KEYER_COLOR_G_Y 0x4650
|
|
#define CAR_mmLBV_KEYER_COLOR_B_CB 0x4651
|
|
#define CAR_mmLBV_KEYER_COLOR_REP_R_CR 0x4652
|
|
#define CAR_mmLBV_KEYER_COLOR_REP_G_Y 0x4653
|
|
#define CAR_mmLBV_KEYER_COLOR_REP_B_CB 0x4654
|
|
#define CAR_mmLBV_BUFFER_LEVEL_STATUS 0x4655
|
|
#define CAR_mmLBV_BUFFER_URGENCY_CTRL 0x4656
|
|
#define CAR_mmLBV_BUFFER_URGENCY_STATUS 0x4657
|
|
#define CAR_mmLBV_BUFFER_STATUS 0x4658
|
|
#define CAR_mmLBV_NO_OUTSTANDING_REQ_STATUS 0x4659
|
|
#define CAR_mmLBV_DEBUG 0x465a
|
|
#define CAR_mmLBV_DEBUG2 0x465b
|
|
#define CAR_mmLBV_DEBUG3 0x465c
|
|
#define CAR_mmLBV_TEST_DEBUG_INDEX 0x4666
|
|
#define CAR_mmLBV_TEST_DEBUG_DATA 0x4667
|
|
#define CAR_mmMVP_CONTROL1 0x2ac
|
|
#define CAR_mmMVP_CONTROL2 0x2ad
|
|
#define CAR_mmMVP_FIFO_CONTROL 0x2ae
|
|
#define CAR_mmMVP_FIFO_STATUS 0x2af
|
|
#define CAR_mmMVP_SLAVE_STATUS 0x2b0
|
|
#define CAR_mmMVP_INBAND_CNTL_CAP 0x2b1
|
|
#define CAR_mmMVP_BLACK_KEYER 0x2b2
|
|
#define CAR_mmMVP_CRC_CNTL 0x2b3
|
|
#define CAR_mmMVP_CRC_RESULT_BLUE_GREEN 0x2b4
|
|
#define CAR_mmMVP_CRC_RESULT_RED 0x2b5
|
|
#define CAR_mmMVP_CONTROL3 0x2b6
|
|
#define CAR_mmMVP_RECEIVE_CNT_CNTL1 0x2b7
|
|
#define CAR_mmMVP_RECEIVE_CNT_CNTL2 0x2b8
|
|
#define CAR_mmMVP_DEBUG 0x2bb
|
|
#define CAR_mmMVP_TEST_DEBUG_INDEX 0x2b9
|
|
#define CAR_mmMVP_TEST_DEBUG_DATA 0x2ba
|
|
#define CAR_ixMVP_DEBUG_12 0xc
|
|
#define CAR_ixMVP_DEBUG_13 0xd
|
|
#define CAR_ixMVP_DEBUG_14 0xe
|
|
#define CAR_ixMVP_DEBUG_15 0xf
|
|
#define CAR_ixMVP_DEBUG_16 0x10
|
|
#define CAR_ixMVP_DEBUG_17 0x11
|
|
#define CAR_mmSCL_COEF_RAM_SELECT 0x1b40
|
|
#define CAR_mmSCL0_SCL_COEF_RAM_SELECT 0x1b40
|
|
#define CAR_mmSCL1_SCL_COEF_RAM_SELECT 0x1d40
|
|
#define CAR_mmSCL2_SCL_COEF_RAM_SELECT 0x1f40
|
|
#define CAR_mmSCL3_SCL_COEF_RAM_SELECT 0x4140
|
|
#define CAR_mmSCL4_SCL_COEF_RAM_SELECT 0x4340
|
|
#define CAR_mmSCL5_SCL_COEF_RAM_SELECT 0x4540
|
|
#define CAR_mmSCL_COEF_RAM_TAP_DATA 0x1b41
|
|
#define CAR_mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1b41
|
|
#define CAR_mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1d41
|
|
#define CAR_mmSCL2_SCL_COEF_RAM_TAP_DATA 0x1f41
|
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#define CAR_mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4141
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#define CAR_mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4341
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#define CAR_mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4541
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#define CAR_mmSCL_MODE 0x1b42
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#define CAR_mmSCL0_SCL_MODE 0x1b42
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#define CAR_mmSCL1_SCL_MODE 0x1d42
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#define CAR_mmSCL2_SCL_MODE 0x1f42
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#define CAR_mmSCL3_SCL_MODE 0x4142
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#define CAR_mmSCL4_SCL_MODE 0x4342
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#define CAR_mmSCL5_SCL_MODE 0x4542
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#define CAR_mmSCL_TAP_CONTROL 0x1b43
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#define CAR_mmSCL0_SCL_TAP_CONTROL 0x1b43
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#define CAR_mmSCL1_SCL_TAP_CONTROL 0x1d43
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#define CAR_mmSCL2_SCL_TAP_CONTROL 0x1f43
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#define CAR_mmSCL3_SCL_TAP_CONTROL 0x4143
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#define CAR_mmSCL4_SCL_TAP_CONTROL 0x4343
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#define CAR_mmSCL5_SCL_TAP_CONTROL 0x4543
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#define CAR_mmSCL_CONTROL 0x1b44
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#define CAR_mmSCL0_SCL_CONTROL 0x1b44
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#define CAR_mmSCL1_SCL_CONTROL 0x1d44
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#define CAR_mmSCL2_SCL_CONTROL 0x1f44
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#define CAR_mmSCL3_SCL_CONTROL 0x4144
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#define CAR_mmSCL4_SCL_CONTROL 0x4344
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#define CAR_mmSCL5_SCL_CONTROL 0x4544
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#define CAR_mmSCL_BYPASS_CONTROL 0x1b45
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#define CAR_mmSCL0_SCL_BYPASS_CONTROL 0x1b45
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#define CAR_mmSCL1_SCL_BYPASS_CONTROL 0x1d45
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#define CAR_mmSCL2_SCL_BYPASS_CONTROL 0x1f45
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#define CAR_mmSCL3_SCL_BYPASS_CONTROL 0x4145
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#define CAR_mmSCL4_SCL_BYPASS_CONTROL 0x4345
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#define CAR_mmSCL5_SCL_BYPASS_CONTROL 0x4545
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#define CAR_mmSCL_MANUAL_REPLICATE_CONTROL 0x1b46
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#define CAR_mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1b46
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#define CAR_mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1d46
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#define CAR_mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x1f46
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#define CAR_mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4146
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#define CAR_mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4346
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#define CAR_mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4546
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#define CAR_mmSCL_AUTOMATIC_MODE_CONTROL 0x1b47
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#define CAR_mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1b47
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#define CAR_mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1d47
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#define CAR_mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x1f47
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#define CAR_mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4147
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#define CAR_mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4347
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#define CAR_mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4547
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#define CAR_mmSCL_HORZ_FILTER_CONTROL 0x1b48
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#define CAR_mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1b48
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#define CAR_mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1d48
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#define CAR_mmSCL2_SCL_HORZ_FILTER_CONTROL 0x1f48
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#define CAR_mmSCL3_SCL_HORZ_FILTER_CONTROL 0x4148
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#define CAR_mmSCL4_SCL_HORZ_FILTER_CONTROL 0x4348
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#define CAR_mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4548
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#define CAR_mmSCL_HORZ_FILTER_SCALE_RATIO 0x1b49
|
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#define CAR_mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1b49
|
|
#define CAR_mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1d49
|
|
#define CAR_mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x1f49
|
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#define CAR_mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x4149
|
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#define CAR_mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x4349
|
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#define CAR_mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4549
|
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#define CAR_mmSCL_HORZ_FILTER_INIT 0x1b4a
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#define CAR_mmSCL0_SCL_HORZ_FILTER_INIT 0x1b4a
|
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#define CAR_mmSCL1_SCL_HORZ_FILTER_INIT 0x1d4a
|
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#define CAR_mmSCL2_SCL_HORZ_FILTER_INIT 0x1f4a
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#define CAR_mmSCL3_SCL_HORZ_FILTER_INIT 0x414a
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#define CAR_mmSCL4_SCL_HORZ_FILTER_INIT 0x434a
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#define CAR_mmSCL5_SCL_HORZ_FILTER_INIT 0x454a
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#define CAR_mmSCL_VERT_FILTER_CONTROL 0x1b4b
|
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#define CAR_mmSCL0_SCL_VERT_FILTER_CONTROL 0x1b4b
|
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#define CAR_mmSCL1_SCL_VERT_FILTER_CONTROL 0x1d4b
|
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#define CAR_mmSCL2_SCL_VERT_FILTER_CONTROL 0x1f4b
|
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#define CAR_mmSCL3_SCL_VERT_FILTER_CONTROL 0x414b
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#define CAR_mmSCL4_SCL_VERT_FILTER_CONTROL 0x434b
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|
#define CAR_mmSCL5_SCL_VERT_FILTER_CONTROL 0x454b
|
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#define CAR_mmSCL_VERT_FILTER_SCALE_RATIO 0x1b4c
|
|
#define CAR_mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1b4c
|
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#define CAR_mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1d4c
|
|
#define CAR_mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x1f4c
|
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#define CAR_mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x414c
|
|
#define CAR_mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x434c
|
|
#define CAR_mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x454c
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#define CAR_mmSCL_VERT_FILTER_INIT 0x1b4d
|
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#define CAR_mmSCL0_SCL_VERT_FILTER_INIT 0x1b4d
|
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#define CAR_mmSCL1_SCL_VERT_FILTER_INIT 0x1d4d
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#define CAR_mmSCL2_SCL_VERT_FILTER_INIT 0x1f4d
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|
#define CAR_mmSCL3_SCL_VERT_FILTER_INIT 0x414d
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|
#define CAR_mmSCL4_SCL_VERT_FILTER_INIT 0x434d
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|
#define CAR_mmSCL5_SCL_VERT_FILTER_INIT 0x454d
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#define CAR_mmSCL_VERT_FILTER_INIT_BOT 0x1b4e
|
|
#define CAR_mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1b4e
|
|
#define CAR_mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1d4e
|
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#define CAR_mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x1f4e
|
|
#define CAR_mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x414e
|
|
#define CAR_mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x434e
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|
#define CAR_mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x454e
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|
#define CAR_mmSCL_ROUND_OFFSET 0x1b4f
|
|
#define CAR_mmSCL0_SCL_ROUND_OFFSET 0x1b4f
|
|
#define CAR_mmSCL1_SCL_ROUND_OFFSET 0x1d4f
|
|
#define CAR_mmSCL2_SCL_ROUND_OFFSET 0x1f4f
|
|
#define CAR_mmSCL3_SCL_ROUND_OFFSET 0x414f
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|
#define CAR_mmSCL4_SCL_ROUND_OFFSET 0x434f
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|
#define CAR_mmSCL5_SCL_ROUND_OFFSET 0x454f
|
|
#define CAR_mmSCL_UPDATE 0x1b51
|
|
#define CAR_mmSCL0_SCL_UPDATE 0x1b51
|
|
#define CAR_mmSCL1_SCL_UPDATE 0x1d51
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|
#define CAR_mmSCL2_SCL_UPDATE 0x1f51
|
|
#define CAR_mmSCL3_SCL_UPDATE 0x4151
|
|
#define CAR_mmSCL4_SCL_UPDATE 0x4351
|
|
#define CAR_mmSCL5_SCL_UPDATE 0x4551
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|
#define CAR_mmSCL_F_SHARP_CONTROL 0x1b53
|
|
#define CAR_mmSCL0_SCL_F_SHARP_CONTROL 0x1b53
|
|
#define CAR_mmSCL1_SCL_F_SHARP_CONTROL 0x1d53
|
|
#define CAR_mmSCL2_SCL_F_SHARP_CONTROL 0x1f53
|
|
#define CAR_mmSCL3_SCL_F_SHARP_CONTROL 0x4153
|
|
#define CAR_mmSCL4_SCL_F_SHARP_CONTROL 0x4353
|
|
#define CAR_mmSCL5_SCL_F_SHARP_CONTROL 0x4553
|
|
#define CAR_mmSCL_ALU_CONTROL 0x1b54
|
|
#define CAR_mmSCL0_SCL_ALU_CONTROL 0x1b54
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#define CAR_mmSCL1_SCL_ALU_CONTROL 0x1d54
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|
#define CAR_mmSCL2_SCL_ALU_CONTROL 0x1f54
|
|
#define CAR_mmSCL3_SCL_ALU_CONTROL 0x4154
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#define CAR_mmSCL4_SCL_ALU_CONTROL 0x4354
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#define CAR_mmSCL5_SCL_ALU_CONTROL 0x4554
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|
#define CAR_mmSCL_COEF_RAM_CONFLICT_STATUS 0x1b55
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|
#define CAR_mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1b55
|
|
#define CAR_mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1d55
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#define CAR_mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x1f55
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#define CAR_mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4155
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#define CAR_mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4355
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#define CAR_mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4555
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#define CAR_mmVIEWPORT_START_SECONDARY 0x1b5b
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#define CAR_mmSCL0_VIEWPORT_START_SECONDARY 0x1b5b
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|
#define CAR_mmSCL1_VIEWPORT_START_SECONDARY 0x1d5b
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#define CAR_mmSCL2_VIEWPORT_START_SECONDARY 0x1f5b
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#define CAR_mmSCL3_VIEWPORT_START_SECONDARY 0x415b
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#define CAR_mmSCL4_VIEWPORT_START_SECONDARY 0x435b
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#define CAR_mmSCL5_VIEWPORT_START_SECONDARY 0x455b
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#define CAR_mmVIEWPORT_START 0x1b5c
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#define CAR_mmSCL0_VIEWPORT_START 0x1b5c
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#define CAR_mmSCL1_VIEWPORT_START 0x1d5c
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#define CAR_mmSCL2_VIEWPORT_START 0x1f5c
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#define CAR_mmSCL3_VIEWPORT_START 0x415c
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#define CAR_mmSCL4_VIEWPORT_START 0x435c
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#define CAR_mmSCL5_VIEWPORT_START 0x455c
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|
#define CAR_mmVIEWPORT_SIZE 0x1b5d
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#define CAR_mmSCL0_VIEWPORT_SIZE 0x1b5d
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#define CAR_mmSCL1_VIEWPORT_SIZE 0x1d5d
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#define CAR_mmSCL2_VIEWPORT_SIZE 0x1f5d
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#define CAR_mmSCL3_VIEWPORT_SIZE 0x415d
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#define CAR_mmSCL4_VIEWPORT_SIZE 0x435d
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#define CAR_mmSCL5_VIEWPORT_SIZE 0x455d
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#define CAR_mmEXT_OVERSCAN_LEFT_RIGHT 0x1b5e
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#define CAR_mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1b5e
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#define CAR_mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1d5e
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#define CAR_mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x1f5e
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#define CAR_mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x415e
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#define CAR_mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x435e
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#define CAR_mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x455e
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#define CAR_mmEXT_OVERSCAN_TOP_BOTTOM 0x1b5f
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#define CAR_mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1b5f
|
|
#define CAR_mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1d5f
|
|
#define CAR_mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x1f5f
|
|
#define CAR_mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x415f
|
|
#define CAR_mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x435f
|
|
#define CAR_mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x455f
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|
#define CAR_mmSCL_MODE_CHANGE_DET1 0x1b60
|
|
#define CAR_mmSCL0_SCL_MODE_CHANGE_DET1 0x1b60
|
|
#define CAR_mmSCL1_SCL_MODE_CHANGE_DET1 0x1d60
|
|
#define CAR_mmSCL2_SCL_MODE_CHANGE_DET1 0x1f60
|
|
#define CAR_mmSCL3_SCL_MODE_CHANGE_DET1 0x4160
|
|
#define CAR_mmSCL4_SCL_MODE_CHANGE_DET1 0x4360
|
|
#define CAR_mmSCL5_SCL_MODE_CHANGE_DET1 0x4560
|
|
#define CAR_mmSCL_MODE_CHANGE_DET2 0x1b61
|
|
#define CAR_mmSCL0_SCL_MODE_CHANGE_DET2 0x1b61
|
|
#define CAR_mmSCL1_SCL_MODE_CHANGE_DET2 0x1d61
|
|
#define CAR_mmSCL2_SCL_MODE_CHANGE_DET2 0x1f61
|
|
#define CAR_mmSCL3_SCL_MODE_CHANGE_DET2 0x4161
|
|
#define CAR_mmSCL4_SCL_MODE_CHANGE_DET2 0x4361
|
|
#define CAR_mmSCL5_SCL_MODE_CHANGE_DET2 0x4561
|
|
#define CAR_mmSCL_MODE_CHANGE_DET3 0x1b62
|
|
#define CAR_mmSCL0_SCL_MODE_CHANGE_DET3 0x1b62
|
|
#define CAR_mmSCL1_SCL_MODE_CHANGE_DET3 0x1d62
|
|
#define CAR_mmSCL2_SCL_MODE_CHANGE_DET3 0x1f62
|
|
#define CAR_mmSCL3_SCL_MODE_CHANGE_DET3 0x4162
|
|
#define CAR_mmSCL4_SCL_MODE_CHANGE_DET3 0x4362
|
|
#define CAR_mmSCL5_SCL_MODE_CHANGE_DET3 0x4562
|
|
#define CAR_mmSCL_MODE_CHANGE_MASK 0x1b63
|
|
#define CAR_mmSCL0_SCL_MODE_CHANGE_MASK 0x1b63
|
|
#define CAR_mmSCL1_SCL_MODE_CHANGE_MASK 0x1d63
|
|
#define CAR_mmSCL2_SCL_MODE_CHANGE_MASK 0x1f63
|
|
#define CAR_mmSCL3_SCL_MODE_CHANGE_MASK 0x4163
|
|
#define CAR_mmSCL4_SCL_MODE_CHANGE_MASK 0x4363
|
|
#define CAR_mmSCL5_SCL_MODE_CHANGE_MASK 0x4563
|
|
#define CAR_mmSCL_DEBUG2 0x1b69
|
|
#define CAR_mmSCL0_SCL_DEBUG2 0x1b69
|
|
#define CAR_mmSCL1_SCL_DEBUG2 0x1d69
|
|
#define CAR_mmSCL2_SCL_DEBUG2 0x1f69
|
|
#define CAR_mmSCL3_SCL_DEBUG2 0x4169
|
|
#define CAR_mmSCL4_SCL_DEBUG2 0x4369
|
|
#define CAR_mmSCL5_SCL_DEBUG2 0x4569
|
|
#define CAR_mmSCL_DEBUG 0x1b6a
|
|
#define CAR_mmSCL0_SCL_DEBUG 0x1b6a
|
|
#define CAR_mmSCL1_SCL_DEBUG 0x1d6a
|
|
#define CAR_mmSCL2_SCL_DEBUG 0x1f6a
|
|
#define CAR_mmSCL3_SCL_DEBUG 0x416a
|
|
#define CAR_mmSCL4_SCL_DEBUG 0x436a
|
|
#define CAR_mmSCL5_SCL_DEBUG 0x456a
|
|
#define CAR_mmSCL_TEST_DEBUG_INDEX 0x1b6b
|
|
#define CAR_mmSCL0_SCL_TEST_DEBUG_INDEX 0x1b6b
|
|
#define CAR_mmSCL1_SCL_TEST_DEBUG_INDEX 0x1d6b
|
|
#define CAR_mmSCL2_SCL_TEST_DEBUG_INDEX 0x1f6b
|
|
#define CAR_mmSCL3_SCL_TEST_DEBUG_INDEX 0x416b
|
|
#define CAR_mmSCL4_SCL_TEST_DEBUG_INDEX 0x436b
|
|
#define CAR_mmSCL5_SCL_TEST_DEBUG_INDEX 0x456b
|
|
#define CAR_mmSCL_TEST_DEBUG_DATA 0x1b6c
|
|
#define CAR_mmSCL0_SCL_TEST_DEBUG_DATA 0x1b6c
|
|
#define CAR_mmSCL1_SCL_TEST_DEBUG_DATA 0x1d6c
|
|
#define CAR_mmSCL2_SCL_TEST_DEBUG_DATA 0x1f6c
|
|
#define CAR_mmSCL3_SCL_TEST_DEBUG_DATA 0x416c
|
|
#define CAR_mmSCL4_SCL_TEST_DEBUG_DATA 0x436c
|
|
#define CAR_mmSCL5_SCL_TEST_DEBUG_DATA 0x456c
|
|
#define CAR_mmSCLV_COEF_RAM_SELECT 0x4670
|
|
#define CAR_mmSCLV_COEF_RAM_TAP_DATA 0x4671
|
|
#define CAR_mmSCLV_MODE 0x4672
|
|
#define CAR_mmSCLV_TAP_CONTROL 0x4673
|
|
#define CAR_mmSCLV_CONTROL 0x4674
|
|
#define CAR_mmSCLV_MANUAL_REPLICATE_CONTROL 0x4675
|
|
#define CAR_mmSCLV_AUTOMATIC_MODE_CONTROL 0x4676
|
|
#define CAR_mmSCLV_HORZ_FILTER_CONTROL 0x4677
|
|
#define CAR_mmSCLV_HORZ_FILTER_SCALE_RATIO 0x4678
|
|
#define CAR_mmSCLV_HORZ_FILTER_INIT 0x4679
|
|
#define CAR_mmSCLV_HORZ_FILTER_SCALE_RATIO_C 0x467a
|
|
#define CAR_mmSCLV_HORZ_FILTER_INIT_C 0x467b
|
|
#define CAR_mmSCLV_VERT_FILTER_CONTROL 0x467c
|
|
#define CAR_mmSCLV_VERT_FILTER_SCALE_RATIO 0x467d
|
|
#define CAR_mmSCLV_VERT_FILTER_INIT 0x467e
|
|
#define CAR_mmSCLV_VERT_FILTER_INIT_BOT 0x467f
|
|
#define CAR_mmSCLV_VERT_FILTER_SCALE_RATIO_C 0x4680
|
|
#define CAR_mmSCLV_VERT_FILTER_INIT_C 0x4681
|
|
#define CAR_mmSCLV_VERT_FILTER_INIT_BOT_C 0x4682
|
|
#define CAR_mmSCLV_ROUND_OFFSET 0x4683
|
|
#define CAR_mmSCLV_UPDATE 0x4684
|
|
#define CAR_mmSCLV_ALU_CONTROL 0x4685
|
|
#define CAR_mmSCLV_VIEWPORT_START 0x4686
|
|
#define CAR_mmSCLV_VIEWPORT_START_SECONDARY 0x4687
|
|
#define CAR_mmSCLV_VIEWPORT_SIZE 0x4688
|
|
#define CAR_mmSCLV_VIEWPORT_START_C 0x4689
|
|
#define CAR_mmSCLV_VIEWPORT_START_SECONDARY_C 0x468a
|
|
#define CAR_mmSCLV_VIEWPORT_SIZE_C 0x468b
|
|
#define CAR_mmSCLV_EXT_OVERSCAN_LEFT_RIGHT 0x468c
|
|
#define CAR_mmSCLV_EXT_OVERSCAN_TOP_BOTTOM 0x468d
|
|
#define CAR_mmSCLV_MODE_CHANGE_DET1 0x468e
|
|
#define CAR_mmSCLV_MODE_CHANGE_DET2 0x468f
|
|
#define CAR_mmSCLV_MODE_CHANGE_DET3 0x4690
|
|
#define CAR_mmSCLV_MODE_CHANGE_MASK 0x4691
|
|
#define CAR_mmSCLV_HORZ_FILTER_INIT_BOT 0x4692
|
|
#define CAR_mmSCLV_HORZ_FILTER_INIT_BOT_C 0x4693
|
|
#define CAR_mmSCLV_DEBUG2 0x4694
|
|
#define CAR_mmSCLV_DEBUG 0x4695
|
|
#define CAR_mmSCLV_TEST_DEBUG_INDEX 0x4696
|
|
#define CAR_mmSCLV_TEST_DEBUG_DATA 0x4697
|
|
#define CAR_mmCOL_MAN_UPDATE 0x46a4
|
|
#define CAR_mmCOL_MAN_INPUT_CSC_CONTROL 0x46a5
|
|
#define CAR_mmINPUT_CSC_C11_C12_A 0x46a6
|
|
#define CAR_mmINPUT_CSC_C13_C14_A 0x46a7
|
|
#define CAR_mmINPUT_CSC_C21_C22_A 0x46a8
|
|
#define CAR_mmINPUT_CSC_C23_C24_A 0x46a9
|
|
#define CAR_mmINPUT_CSC_C31_C32_A 0x46aa
|
|
#define CAR_mmINPUT_CSC_C33_C34_A 0x46ab
|
|
#define CAR_mmINPUT_CSC_C11_C12_B 0x46ac
|
|
#define CAR_mmINPUT_CSC_C13_C14_B 0x46ad
|
|
#define CAR_mmINPUT_CSC_C21_C22_B 0x46ae
|
|
#define CAR_mmINPUT_CSC_C23_C24_B 0x46af
|
|
#define CAR_mmINPUT_CSC_C31_C32_B 0x46b0
|
|
#define CAR_mmINPUT_CSC_C33_C34_B 0x46b1
|
|
#define CAR_mmPRESCALE_CONTROL 0x46b2
|
|
#define CAR_mmPRESCALE_VALUES_R 0x46b3
|
|
#define CAR_mmPRESCALE_VALUES_G 0x46b4
|
|
#define CAR_mmPRESCALE_VALUES_B 0x46b5
|
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#define CAR_mmCOL_MAN_OUTPUT_CSC_CONTROL 0x46b6
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#define CAR_mmOUTPUT_CSC_C11_C12_A 0x46b7
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#define CAR_mmOUTPUT_CSC_C13_C14_A 0x46b8
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#define CAR_mmOUTPUT_CSC_C21_C22_A 0x46b9
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#define CAR_mmOUTPUT_CSC_C23_C24_A 0x46ba
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#define CAR_mmOUTPUT_CSC_C31_C32_A 0x46bb
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#define CAR_mmOUTPUT_CSC_C33_C34_A 0x46bc
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#define CAR_mmOUTPUT_CSC_C11_C12_B 0x46bd
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#define CAR_mmOUTPUT_CSC_C13_C14_B 0x46be
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#define CAR_mmOUTPUT_CSC_C21_C22_B 0x46bf
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#define CAR_mmOUTPUT_CSC_C23_C24_B 0x46c0
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#define CAR_mmOUTPUT_CSC_C31_C32_B 0x46c1
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#define CAR_mmOUTPUT_CSC_C33_C34_B 0x46c2
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#define CAR_mmDENORM_CLAMP_CONTROL 0x46c3
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#define CAR_mmDENORM_CLAMP_RANGE_R_CR 0x46c4
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#define CAR_mmDENORM_CLAMP_RANGE_G_Y 0x46c5
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#define CAR_mmDENORM_CLAMP_RANGE_B_CB 0x46c6
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#define CAR_mmCOL_MAN_FP_CONVERTED_FIELD 0x46c7
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#define CAR_mmGAMMA_CORR_CONTROL 0x46c8
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#define CAR_mmGAMMA_CORR_LUT_INDEX 0x46c9
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#define CAR_mmGAMMA_CORR_LUT_DATA 0x46ca
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#define CAR_mmGAMMA_CORR_LUT_WRITE_EN_MASK 0x46cb
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#define CAR_mmGAMMA_CORR_CNTLA_START_CNTL 0x46cc
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#define CAR_mmGAMMA_CORR_CNTLA_SLOPE_CNTL 0x46cd
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#define CAR_mmGAMMA_CORR_CNTLA_END_CNTL1 0x46ce
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#define CAR_mmGAMMA_CORR_CNTLA_END_CNTL2 0x46cf
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#define CAR_mmGAMMA_CORR_CNTLA_REGION_0_1 0x46d0
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#define CAR_mmGAMMA_CORR_CNTLA_REGION_2_3 0x46d1
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#define CAR_mmGAMMA_CORR_CNTLA_REGION_4_5 0x46d2
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#define CAR_mmGAMMA_CORR_CNTLA_REGION_6_7 0x46d3
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#define CAR_mmGAMMA_CORR_CNTLA_REGION_8_9 0x46d4
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#define CAR_mmGAMMA_CORR_CNTLA_REGION_10_11 0x46d5
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#define CAR_mmGAMMA_CORR_CNTLA_REGION_12_13 0x46d6
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#define CAR_mmGAMMA_CORR_CNTLA_REGION_14_15 0x46d7
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#define CAR_mmGAMMA_CORR_CNTLB_START_CNTL 0x46d8
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#define CAR_mmGAMMA_CORR_CNTLB_SLOPE_CNTL 0x46d9
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#define CAR_mmGAMMA_CORR_CNTLB_END_CNTL1 0x46da
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#define CAR_mmGAMMA_CORR_CNTLB_END_CNTL2 0x46db
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#define CAR_mmGAMMA_CORR_CNTLB_REGION_0_1 0x46dc
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#define CAR_mmGAMMA_CORR_CNTLB_REGION_2_3 0x46dd
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#define CAR_mmGAMMA_CORR_CNTLB_REGION_4_5 0x46de
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#define CAR_mmGAMMA_CORR_CNTLB_REGION_6_7 0x46df
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#define CAR_mmGAMMA_CORR_CNTLB_REGION_8_9 0x46e0
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#define CAR_mmGAMMA_CORR_CNTLB_REGION_10_11 0x46e1
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#define CAR_mmGAMMA_CORR_CNTLB_REGION_12_13 0x46e2
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#define CAR_mmGAMMA_CORR_CNTLB_REGION_14_15 0x46e3
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#define CAR_mmPACK_FIFO_ERROR 0x46e4
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#define CAR_mmOUTPUT_FIFO_ERROR 0x46e5
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#define CAR_mmINPUT_GAMMA_LUT_AUTOFILL 0x46e6
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#define CAR_mmINPUT_GAMMA_LUT_RW_INDEX 0x46e7
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#define CAR_mmINPUT_GAMMA_LUT_SEQ_COLOR 0x46e8
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#define CAR_mmINPUT_GAMMA_LUT_PWL_DATA 0x46e9
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#define CAR_mmINPUT_GAMMA_LUT_30_COLOR 0x46ea
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#define CAR_mmCOL_MAN_INPUT_GAMMA_CONTROL1 0x46eb
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#define CAR_mmCOL_MAN_INPUT_GAMMA_CONTROL2 0x46ec
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#define CAR_mmINPUT_GAMMA_BW_OFFSETS_B 0x46ed
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#define CAR_mmINPUT_GAMMA_BW_OFFSETS_G 0x46ee
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#define CAR_mmINPUT_GAMMA_BW_OFFSETS_R 0x46ef
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#define CAR_mmCOL_MAN_DEBUG_CONTROL 0x46f0
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#define CAR_mmCOL_MAN_TEST_DEBUG_INDEX 0x46f1
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#define CAR_mmCOL_MAN_TEST_DEBUG_DATA 0x46f3
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#define CAR_mmUNP_GRPH_ENABLE 0x4600
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#define CAR_mmUNP_GRPH_CONTROL 0x4601
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#define CAR_mmUNP_GRPH_CONTROL_C 0x4602
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#define CAR_mmUNP_GRPH_CONTROL_EXP 0x4603
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#define CAR_mmUNP_GRPH_SWAP_CNTL 0x4605
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#define CAR_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L 0x4606
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#define CAR_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C 0x4607
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#define CAR_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L 0x4608
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#define CAR_mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x4609
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#define CAR_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L 0x460a
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#define CAR_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C 0x460b
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#define CAR_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x460c
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#define CAR_mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x460d
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#define CAR_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L 0x460e
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#define CAR_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C 0x460f
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#define CAR_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L 0x4610
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#define CAR_mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x4611
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#define CAR_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L 0x4612
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#define CAR_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C 0x4613
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#define CAR_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L 0x4614
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#define CAR_mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C 0x4615
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#define CAR_mmUNP_GRPH_PITCH_L 0x4616
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#define CAR_mmUNP_GRPH_PITCH_C 0x4617
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#define CAR_mmUNP_GRPH_SURFACE_OFFSET_X_L 0x4618
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#define CAR_mmUNP_GRPH_SURFACE_OFFSET_X_C 0x4619
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#define CAR_mmUNP_GRPH_SURFACE_OFFSET_Y_L 0x461a
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#define CAR_mmUNP_GRPH_SURFACE_OFFSET_Y_C 0x461b
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#define CAR_mmUNP_GRPH_X_START_L 0x461c
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#define CAR_mmUNP_GRPH_X_START_C 0x461d
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#define CAR_mmUNP_GRPH_Y_START_L 0x461e
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#define CAR_mmUNP_GRPH_Y_START_C 0x461f
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#define CAR_mmUNP_GRPH_X_END_L 0x4620
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#define CAR_mmUNP_GRPH_X_END_C 0x4621
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#define CAR_mmUNP_GRPH_Y_END_L 0x4622
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#define CAR_mmUNP_GRPH_Y_END_C 0x4623
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#define CAR_mmUNP_GRPH_UPDATE 0x4624
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#define CAR_mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT 0x463a
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#define CAR_mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L 0x4625
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#define CAR_mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C 0x4626
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#define CAR_mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L 0x4627
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#define CAR_mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C 0x4628
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#define CAR_mmUNP_DVMM_PTE_CONTROL 0x4629
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#define CAR_mmUNP_DVMM_PTE_CONTROL_C 0x4604
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#define CAR_mmUNP_DVMM_PTE_ARB_CONTROL 0x462a
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#define CAR_mmUNP_DVMM_PTE_ARB_CONTROL_C 0x462d
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#define CAR_mmUNP_GRPH_INTERRUPT_STATUS 0x462b
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#define CAR_mmUNP_GRPH_INTERRUPT_CONTROL 0x462c
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#define CAR_mmUNP_GRPH_STEREOSYNC_FLIP 0x462e
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#define CAR_mmUNP_FLIP_CONTROL 0x462f
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#define CAR_mmUNP_CRC_CONTROL 0x4630
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#define CAR_mmUNP_CRC_MASK 0x4631
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#define CAR_mmUNP_CRC_CURRENT 0x4632
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#define CAR_mmUNP_CRC_LAST 0x4633
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#define CAR_mmUNP_LB_DATA_GAP_BETWEEN_CHUNK 0x4634
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#define CAR_mmUNP_HW_ROTATION 0x4635
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#define CAR_mmUNP_DEBUG 0x4636
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#define CAR_mmUNP_DEBUG2 0x4637
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#define CAR_mmUNP_DVMM_DEBUG 0x463b
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#define CAR_mmUNP_TEST_DEBUG_INDEX 0x4638
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#define CAR_mmUNP_TEST_DEBUG_DATA 0x4639
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#define CAR_mmGENMO_WT 0xf0
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#define CAR_mmGENMO_RD 0xf3
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#define CAR_mmGENENB 0xf0
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#define CAR_mmGENFC_WT 0xee
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#define CAR_mmVGA0_GENFC_WT 0xee
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#define CAR_mmVGA1_GENFC_WT 0xf6
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#define CAR_mmGENFC_RD 0xf2
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#define CAR_mmGENS0 0xf0
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#define CAR_mmGENS1 0xee
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#define CAR_mmVGA0_GENS1 0xee
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#define CAR_mmVGA1_GENS1 0xf6
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#define CAR_mmDAC_DATA 0xf2
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#define CAR_mmDAC_MASK 0xf1
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#define CAR_mmDAC_R_INDEX 0xf1
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#define CAR_mmDAC_W_INDEX 0xf2
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#define CAR_mmSEQ8_IDX 0xf1
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#define CAR_mmSEQ8_DATA 0xf1
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#define CAR_ixSEQ00 0x0
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#define CAR_ixSEQ01 0x1
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#define CAR_ixSEQ02 0x2
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#define CAR_ixSEQ03 0x3
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#define CAR_ixSEQ04 0x4
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#define CAR_mmCRTC8_IDX 0xed
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#define CAR_mmVGA0_CRTC8_IDX 0xed
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#define CAR_mmVGA1_CRTC8_IDX 0xf5
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#define CAR_mmCRTC8_DATA 0xed
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#define CAR_mmVGA0_CRTC8_DATA 0xed
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#define CAR_mmVGA1_CRTC8_DATA 0xf5
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#define CAR_ixCRT00 0x0
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#define CAR_ixCRT01 0x1
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#define CAR_ixCRT02 0x2
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#define CAR_ixCRT03 0x3
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#define CAR_ixCRT04 0x4
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#define CAR_ixCRT05 0x5
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#define CAR_ixCRT06 0x6
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#define CAR_ixCRT07 0x7
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#define CAR_ixCRT08 0x8
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#define CAR_ixCRT09 0x9
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#define CAR_ixCRT0A 0xa
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#define CAR_ixCRT0B 0xb
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#define CAR_ixCRT0C 0xc
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#define CAR_ixCRT0D 0xd
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#define CAR_ixCRT0E 0xe
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#define CAR_ixCRT0F 0xf
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#define CAR_ixCRT10 0x10
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#define CAR_ixCRT11 0x11
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#define CAR_ixCRT12 0x12
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#define CAR_ixCRT13 0x13
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#define CAR_ixCRT14 0x14
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#define CAR_ixCRT15 0x15
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#define CAR_ixCRT16 0x16
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#define CAR_ixCRT17 0x17
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#define CAR_ixCRT18 0x18
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#define CAR_ixCRT1E 0x1e
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#define CAR_ixCRT1F 0x1f
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#define CAR_ixCRT22 0x22
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#define CAR_mmGRPH8_IDX 0xf3
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#define CAR_mmGRPH8_DATA 0xf3
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#define CAR_ixGRA00 0x0
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#define CAR_ixGRA01 0x1
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#define CAR_ixGRA02 0x2
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#define CAR_ixGRA03 0x3
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#define CAR_ixGRA04 0x4
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#define CAR_ixGRA05 0x5
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#define CAR_ixGRA06 0x6
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#define CAR_ixGRA07 0x7
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#define CAR_ixGRA08 0x8
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#define CAR_mmATTRX 0xf0
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#define CAR_mmATTRDW 0xf0
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#define CAR_mmATTRDR 0xf0
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#define CAR_ixATTR00 0x0
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#define CAR_ixATTR01 0x1
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#define CAR_ixATTR02 0x2
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#define CAR_ixATTR03 0x3
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#define CAR_ixATTR04 0x4
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#define CAR_ixATTR05 0x5
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#define CAR_ixATTR06 0x6
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#define CAR_ixATTR07 0x7
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#define CAR_ixATTR08 0x8
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#define CAR_ixATTR09 0x9
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#define CAR_ixATTR0A 0xa
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#define CAR_ixATTR0B 0xb
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#define CAR_ixATTR0C 0xc
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#define CAR_ixATTR0D 0xd
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#define CAR_ixATTR0E 0xe
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#define CAR_ixATTR0F 0xf
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#define CAR_ixATTR10 0x10
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#define CAR_ixATTR11 0x11
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#define CAR_ixATTR12 0x12
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#define CAR_ixATTR13 0x13
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#define CAR_ixATTR14 0x14
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#define CAR_mmVGA_RENDER_CONTROL 0xc0
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#define CAR_mmVGA_SOURCE_SELECT 0xfc
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#define CAR_mmVGA_SEQUENCER_RESET_CONTROL 0xc1
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#define CAR_mmVGA_MODE_CONTROL 0xc2
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#define CAR_mmVGA_SURFACE_PITCH_SELECT 0xc3
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#define CAR_mmVGA_MEMORY_BASE_ADDRESS 0xc4
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#define CAR_mmVGA_MEMORY_BASE_ADDRESS_HIGH 0xc9
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#define CAR_mmVGA_DISPBUF1_SURFACE_ADDR 0xc6
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#define CAR_mmVGA_DISPBUF2_SURFACE_ADDR 0xc8
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#define CAR_mmVGA_HDP_CONTROL 0xca
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#define CAR_mmVGA_CACHE_CONTROL 0xcb
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#define CAR_mmD1VGA_CONTROL 0xcc
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#define CAR_mmD2VGA_CONTROL 0xce
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#define CAR_mmD3VGA_CONTROL 0xf8
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#define CAR_mmD4VGA_CONTROL 0xf9
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#define CAR_mmD5VGA_CONTROL 0xfa
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#define CAR_mmD6VGA_CONTROL 0xfb
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#define CAR_mmVGA_HW_DEBUG 0xcf
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#define CAR_mmVGA_STATUS 0xd0
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#define CAR_mmVGA_INTERRUPT_CONTROL 0xd1
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#define CAR_mmVGA_STATUS_CLEAR 0xd2
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#define CAR_mmVGA_INTERRUPT_STATUS 0xd3
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#define CAR_mmVGA_MAIN_CONTROL 0xd4
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#define CAR_mmVGA_TEST_CONTROL 0xd5
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#define CAR_mmVGA_DEBUG_READBACK_INDEX 0xd6
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#define CAR_mmVGA_DEBUG_READBACK_DATA 0xd7
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#define CAR_mmVGA_MEM_WRITE_PAGE_ADDR 0x12
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#define CAR_mmVGA_MEM_READ_PAGE_ADDR 0x13
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#define CAR_mmVGA_TEST_DEBUG_INDEX 0xc5
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#define CAR_mmVGA_TEST_DEBUG_DATA 0xc7
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#define CAR_ixVGADCC_DBG_DCCIF_C 0x7e
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#define CAR_mmBPHYC_DAC_MACRO_CNTL 0x48b9
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#define CAR_mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x48ba
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#define CAR_mmPLL_REF_DIV 0x1700
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#define CAR_mmBPHYC_PLL0_PLL_REF_DIV 0x1700
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#define CAR_mmBPHYC_PLL1_PLL_REF_DIV 0x172a
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#define CAR_mmBPHYC_PLL2_PLL_REF_DIV 0x1754
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#define CAR_mmPLL_FB_DIV 0x1701
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#define CAR_mmBPHYC_PLL0_PLL_FB_DIV 0x1701
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#define CAR_mmBPHYC_PLL1_PLL_FB_DIV 0x172b
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#define CAR_mmBPHYC_PLL2_PLL_FB_DIV 0x1755
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#define CAR_mmPLL_POST_DIV 0x1702
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#define CAR_mmBPHYC_PLL0_PLL_POST_DIV 0x1702
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#define CAR_mmBPHYC_PLL1_PLL_POST_DIV 0x172c
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#define CAR_mmBPHYC_PLL2_PLL_POST_DIV 0x1756
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#define CAR_mmPLL_SS_AMOUNT_DSFRAC 0x1703
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#define CAR_mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703
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#define CAR_mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC 0x172d
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#define CAR_mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1757
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#define CAR_mmPLL_SS_CNTL 0x1704
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#define CAR_mmBPHYC_PLL0_PLL_SS_CNTL 0x1704
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#define CAR_mmBPHYC_PLL1_PLL_SS_CNTL 0x172e
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#define CAR_mmBPHYC_PLL2_PLL_SS_CNTL 0x1758
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#define CAR_mmPLL_DS_CNTL 0x1705
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#define CAR_mmBPHYC_PLL0_PLL_DS_CNTL 0x1705
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#define CAR_mmBPHYC_PLL1_PLL_DS_CNTL 0x172f
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#define CAR_mmBPHYC_PLL2_PLL_DS_CNTL 0x1759
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#define CAR_mmPLL_IDCLK_CNTL 0x1706
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#define CAR_mmBPHYC_PLL0_PLL_IDCLK_CNTL 0x1706
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#define CAR_mmBPHYC_PLL1_PLL_IDCLK_CNTL 0x1730
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#define CAR_mmBPHYC_PLL2_PLL_IDCLK_CNTL 0x175a
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#define CAR_mmPLL_CNTL 0x1707
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#define CAR_mmBPHYC_PLL0_PLL_CNTL 0x1707
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#define CAR_mmBPHYC_PLL1_PLL_CNTL 0x1731
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#define CAR_mmBPHYC_PLL2_PLL_CNTL 0x175b
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#define CAR_mmPLL_ANALOG 0x1708
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#define CAR_mmBPHYC_PLL0_PLL_ANALOG 0x1708
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#define CAR_mmBPHYC_PLL1_PLL_ANALOG 0x1732
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#define CAR_mmBPHYC_PLL2_PLL_ANALOG 0x175c
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#define CAR_mmPLL_VREG_CNTL 0x1709
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#define CAR_mmBPHYC_PLL0_PLL_VREG_CNTL 0x1709
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#define CAR_mmBPHYC_PLL1_PLL_VREG_CNTL 0x1733
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#define CAR_mmBPHYC_PLL2_PLL_VREG_CNTL 0x175d
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#define CAR_mmPLL_UNLOCK_DETECT_CNTL 0x170a
|
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#define CAR_mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170a
|
|
#define CAR_mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL 0x1734
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|
#define CAR_mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL 0x175e
|
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#define CAR_mmPLL_DEBUG_CNTL 0x170b
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#define CAR_mmBPHYC_PLL0_PLL_DEBUG_CNTL 0x170b
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#define CAR_mmBPHYC_PLL1_PLL_DEBUG_CNTL 0x1735
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#define CAR_mmBPHYC_PLL2_PLL_DEBUG_CNTL 0x175f
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#define CAR_mmPLL_UPDATE_LOCK 0x170c
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#define CAR_mmBPHYC_PLL0_PLL_UPDATE_LOCK 0x170c
|
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#define CAR_mmBPHYC_PLL1_PLL_UPDATE_LOCK 0x1736
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#define CAR_mmBPHYC_PLL2_PLL_UPDATE_LOCK 0x1760
|
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#define CAR_mmPLL_UPDATE_CNTL 0x170d
|
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#define CAR_mmBPHYC_PLL0_PLL_UPDATE_CNTL 0x170d
|
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#define CAR_mmBPHYC_PLL1_PLL_UPDATE_CNTL 0x1737
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#define CAR_mmBPHYC_PLL2_PLL_UPDATE_CNTL 0x1761
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|
#define CAR_mmPLL_XOR_LOCK 0x1710
|
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#define CAR_mmBPHYC_PLL0_PLL_XOR_LOCK 0x1710
|
|
#define CAR_mmBPHYC_PLL1_PLL_XOR_LOCK 0x173a
|
|
#define CAR_mmBPHYC_PLL2_PLL_XOR_LOCK 0x1764
|
|
#define CAR_mmPLL_ANALOG_CNTL 0x1711
|
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#define CAR_mmBPHYC_PLL0_PLL_ANALOG_CNTL 0x1711
|
|
#define CAR_mmBPHYC_PLL1_PLL_ANALOG_CNTL 0x173b
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#define CAR_mmBPHYC_PLL2_PLL_ANALOG_CNTL 0x1765
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#define CAR_mmVGA25_PPLL_REF_DIV 0x1712
|
|
#define CAR_mmBPHYC_PLL0_VGA25_PPLL_REF_DIV 0x1712
|
|
#define CAR_mmBPHYC_PLL1_VGA25_PPLL_REF_DIV 0x173c
|
|
#define CAR_mmBPHYC_PLL2_VGA25_PPLL_REF_DIV 0x1766
|
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#define CAR_mmVGA28_PPLL_REF_DIV 0x1713
|
|
#define CAR_mmBPHYC_PLL0_VGA28_PPLL_REF_DIV 0x1713
|
|
#define CAR_mmBPHYC_PLL1_VGA28_PPLL_REF_DIV 0x173d
|
|
#define CAR_mmBPHYC_PLL2_VGA28_PPLL_REF_DIV 0x1767
|
|
#define CAR_mmVGA41_PPLL_REF_DIV 0x1714
|
|
#define CAR_mmBPHYC_PLL0_VGA41_PPLL_REF_DIV 0x1714
|
|
#define CAR_mmBPHYC_PLL1_VGA41_PPLL_REF_DIV 0x173e
|
|
#define CAR_mmBPHYC_PLL2_VGA41_PPLL_REF_DIV 0x1768
|
|
#define CAR_mmVGA25_PPLL_FB_DIV 0x1715
|
|
#define CAR_mmBPHYC_PLL0_VGA25_PPLL_FB_DIV 0x1715
|
|
#define CAR_mmBPHYC_PLL1_VGA25_PPLL_FB_DIV 0x173f
|
|
#define CAR_mmBPHYC_PLL2_VGA25_PPLL_FB_DIV 0x1769
|
|
#define CAR_mmVGA28_PPLL_FB_DIV 0x1716
|
|
#define CAR_mmBPHYC_PLL0_VGA28_PPLL_FB_DIV 0x1716
|
|
#define CAR_mmBPHYC_PLL1_VGA28_PPLL_FB_DIV 0x1740
|
|
#define CAR_mmBPHYC_PLL2_VGA28_PPLL_FB_DIV 0x176a
|
|
#define CAR_mmVGA41_PPLL_FB_DIV 0x1717
|
|
#define CAR_mmBPHYC_PLL0_VGA41_PPLL_FB_DIV 0x1717
|
|
#define CAR_mmBPHYC_PLL1_VGA41_PPLL_FB_DIV 0x1741
|
|
#define CAR_mmBPHYC_PLL2_VGA41_PPLL_FB_DIV 0x176b
|
|
#define CAR_mmVGA25_PPLL_POST_DIV 0x1718
|
|
#define CAR_mmBPHYC_PLL0_VGA25_PPLL_POST_DIV 0x1718
|
|
#define CAR_mmBPHYC_PLL1_VGA25_PPLL_POST_DIV 0x1742
|
|
#define CAR_mmBPHYC_PLL2_VGA25_PPLL_POST_DIV 0x176c
|
|
#define CAR_mmVGA28_PPLL_POST_DIV 0x1719
|
|
#define CAR_mmBPHYC_PLL0_VGA28_PPLL_POST_DIV 0x1719
|
|
#define CAR_mmBPHYC_PLL1_VGA28_PPLL_POST_DIV 0x1743
|
|
#define CAR_mmBPHYC_PLL2_VGA28_PPLL_POST_DIV 0x176d
|
|
#define CAR_mmVGA41_PPLL_POST_DIV 0x171a
|
|
#define CAR_mmBPHYC_PLL0_VGA41_PPLL_POST_DIV 0x171a
|
|
#define CAR_mmBPHYC_PLL1_VGA41_PPLL_POST_DIV 0x1744
|
|
#define CAR_mmBPHYC_PLL2_VGA41_PPLL_POST_DIV 0x176e
|
|
#define CAR_mmVGA25_PPLL_ANALOG 0x171b
|
|
#define CAR_mmBPHYC_PLL0_VGA25_PPLL_ANALOG 0x171b
|
|
#define CAR_mmBPHYC_PLL1_VGA25_PPLL_ANALOG 0x1745
|
|
#define CAR_mmBPHYC_PLL2_VGA25_PPLL_ANALOG 0x176f
|
|
#define CAR_mmVGA28_PPLL_ANALOG 0x171c
|
|
#define CAR_mmBPHYC_PLL0_VGA28_PPLL_ANALOG 0x171c
|
|
#define CAR_mmBPHYC_PLL1_VGA28_PPLL_ANALOG 0x1746
|
|
#define CAR_mmBPHYC_PLL2_VGA28_PPLL_ANALOG 0x1770
|
|
#define CAR_mmVGA41_PPLL_ANALOG 0x171d
|
|
#define CAR_mmBPHYC_PLL0_VGA41_PPLL_ANALOG 0x171d
|
|
#define CAR_mmBPHYC_PLL1_VGA41_PPLL_ANALOG 0x1747
|
|
#define CAR_mmBPHYC_PLL2_VGA41_PPLL_ANALOG 0x1771
|
|
#define CAR_mmDISPPLL_BG_CNTL 0x171e
|
|
#define CAR_mmBPHYC_PLL0_DISPPLL_BG_CNTL 0x171e
|
|
#define CAR_mmBPHYC_PLL1_DISPPLL_BG_CNTL 0x1748
|
|
#define CAR_mmBPHYC_PLL2_DISPPLL_BG_CNTL 0x1772
|
|
#define CAR_mmPPLL_DIV_UPDATE_DEBUG 0x171f
|
|
#define CAR_mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG 0x171f
|
|
#define CAR_mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG 0x1749
|
|
#define CAR_mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG 0x1773
|
|
#define CAR_mmPPLL_STATUS_DEBUG 0x1720
|
|
#define CAR_mmBPHYC_PLL0_PPLL_STATUS_DEBUG 0x1720
|
|
#define CAR_mmBPHYC_PLL1_PPLL_STATUS_DEBUG 0x174a
|
|
#define CAR_mmBPHYC_PLL2_PPLL_STATUS_DEBUG 0x1774
|
|
#define CAR_mmPPLL_DEBUG_MUX_CNTL 0x1721
|
|
#define CAR_mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL 0x1721
|
|
#define CAR_mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL 0x174b
|
|
#define CAR_mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL 0x1775
|
|
#define CAR_mmPPLL_SPARE0 0x1722
|
|
#define CAR_mmBPHYC_PLL0_PPLL_SPARE0 0x1722
|
|
#define CAR_mmBPHYC_PLL1_PPLL_SPARE0 0x174c
|
|
#define CAR_mmBPHYC_PLL2_PPLL_SPARE0 0x1776
|
|
#define CAR_mmPPLL_SPARE1 0x1723
|
|
#define CAR_mmBPHYC_PLL0_PPLL_SPARE1 0x1723
|
|
#define CAR_mmBPHYC_PLL1_PPLL_SPARE1 0x174d
|
|
#define CAR_mmBPHYC_PLL2_PPLL_SPARE1 0x1777
|
|
#define CAR_mmUNIPHY_TX_CONTROL1 0x48c0
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1 0x48c0
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1 0x48e0
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1 0x4900
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1 0x4920
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1 0x4940
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1 0x4960
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1 0x4980
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL1 0x49c0
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL1 0x49e0
|
|
#define CAR_mmUNIPHY_TX_CONTROL2 0x48c1
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2 0x48c1
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2 0x48e1
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2 0x4901
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2 0x4921
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2 0x4941
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2 0x4961
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2 0x4981
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL2 0x49c1
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL2 0x49e1
|
|
#define CAR_mmUNIPHY_TX_CONTROL3 0x48c2
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3 0x48c2
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3 0x48e2
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3 0x4902
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3 0x4922
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3 0x4942
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3 0x4962
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3 0x4982
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL3 0x49c2
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL3 0x49e2
|
|
#define CAR_mmUNIPHY_TX_CONTROL4 0x48c3
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4 0x48c3
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4 0x48e3
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4 0x4903
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4 0x4923
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4 0x4943
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4 0x4963
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4 0x4983
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL4 0x49c3
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL4 0x49e3
|
|
#define CAR_mmUNIPHY_POWER_CONTROL 0x48c4
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL 0x48c4
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL 0x48e4
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL 0x4904
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL 0x4924
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL 0x4944
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL 0x4964
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL 0x4984
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_POWER_CONTROL 0x49c4
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_POWER_CONTROL 0x49e4
|
|
#define CAR_mmUNIPHY_PLL_FBDIV 0x48c5
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV 0x48c5
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV 0x48e5
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV 0x4905
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV 0x4925
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV 0x4945
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV 0x4965
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV 0x4985
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_PLL_FBDIV 0x49c5
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_PLL_FBDIV 0x49e5
|
|
#define CAR_mmUNIPHY_PLL_CONTROL1 0x48c6
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1 0x48c6
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1 0x48e6
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1 0x4906
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1 0x4926
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1 0x4946
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1 0x4966
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1 0x4986
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL1 0x49c6
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL1 0x49e6
|
|
#define CAR_mmUNIPHY_PLL_CONTROL2 0x48c7
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2 0x48c7
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2 0x48e7
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2 0x4907
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2 0x4927
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2 0x4947
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2 0x4967
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2 0x4987
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL2 0x49c7
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL2 0x49e7
|
|
#define CAR_mmUNIPHY_PLL_SS_STEP_SIZE 0x48c8
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x48c8
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x48e8
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x4908
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x4928
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x4948
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x4968
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE 0x4988
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_STEP_SIZE 0x49c8
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_STEP_SIZE 0x49e8
|
|
#define CAR_mmUNIPHY_PLL_SS_CNTL 0x48c9
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x48c9
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x48e9
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x4909
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x4929
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x4949
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x4969
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL 0x4989
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_CNTL 0x49c9
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_CNTL 0x49e9
|
|
#define CAR_mmUNIPHY_DATA_SYNCHRONIZATION 0x48ca
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x48ca
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x48ea
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x490a
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x492a
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x494a
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x496a
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION 0x498a
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_DATA_SYNCHRONIZATION 0x49ca
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_DATA_SYNCHRONIZATION 0x49ea
|
|
#define CAR_mmUNIPHY_REG_TEST_OUTPUT 0x48cb
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x48cb
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x48eb
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x490b
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x492b
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x494b
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x496b
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT 0x498b
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT 0x49cb
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT 0x49eb
|
|
#define CAR_mmUNIPHY_ANG_BIST_CNTL 0x48cc
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x48cc
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x48ec
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x490c
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x492c
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x494c
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x496c
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL 0x498c
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_ANG_BIST_CNTL 0x49cc
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_ANG_BIST_CNTL 0x49ec
|
|
#define CAR_mmUNIPHY_REG_TEST_OUTPUT2 0x48cd
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2 0x48cd
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2 0x48ed
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2 0x490d
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2 0x492d
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2 0x494d
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2 0x496d
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2 0x498d
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT2 0x49cd
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT2 0x49ed
|
|
#define CAR_mmUNIPHY_TMDP_REG0 0x48ce
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0 0x48ce
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0 0x48ee
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0 0x490e
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0 0x492e
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0 0x494e
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0 0x496e
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0 0x498e
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG0 0x49ce
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG0 0x49ee
|
|
#define CAR_mmUNIPHY_TMDP_REG1 0x48cf
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1 0x48cf
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1 0x48ef
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1 0x490f
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1 0x492f
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1 0x494f
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1 0x496f
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1 0x498f
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG1 0x49cf
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG1 0x49ef
|
|
#define CAR_mmUNIPHY_TMDP_REG2 0x48d0
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2 0x48d0
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2 0x48f0
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2 0x4910
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2 0x4930
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2 0x4950
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2 0x4970
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2 0x4990
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG2 0x49d0
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG2 0x49f0
|
|
#define CAR_mmUNIPHY_TMDP_REG3 0x48d1
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3 0x48d1
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3 0x48f1
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3 0x4911
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3 0x4931
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|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3 0x4951
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|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3 0x4971
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|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3 0x4991
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG3 0x49d1
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|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG3 0x49f1
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|
#define CAR_mmUNIPHY_TMDP_REG4 0x48d2
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4 0x48d2
|
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#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4 0x48f2
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4 0x4912
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4 0x4932
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|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4 0x4952
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|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4 0x4972
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|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4 0x4992
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG4 0x49d2
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|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG4 0x49f2
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|
#define CAR_mmUNIPHY_TMDP_REG5 0x48d3
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5 0x48d3
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5 0x48f3
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5 0x4913
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|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5 0x4933
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5 0x4953
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|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5 0x4973
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5 0x4993
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG5 0x49d3
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG5 0x49f3
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|
#define CAR_mmUNIPHY_TMDP_REG6 0x48d4
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|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6 0x48d4
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6 0x48f4
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6 0x4914
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6 0x4934
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6 0x4954
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|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6 0x4974
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|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6 0x4994
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG6 0x49d4
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|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG6 0x49f4
|
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#define CAR_mmUNIPHY_TPG_CONTROL 0x48d5
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL 0x48d5
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL 0x48f5
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL 0x4915
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL 0x4935
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL 0x4955
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL 0x4975
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL 0x4995
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TPG_CONTROL 0x49d5
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TPG_CONTROL 0x49f5
|
|
#define CAR_mmUNIPHY_TPG_SEED 0x48d6
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED 0x48d6
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED 0x48f6
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED 0x4916
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED 0x4936
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED 0x4956
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED 0x4976
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED 0x4996
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_TPG_SEED 0x49d6
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_TPG_SEED 0x49f6
|
|
#define CAR_mmUNIPHY_DEBUG 0x48d7
|
|
#define CAR_mmBPHYC_UNIPHY0_UNIPHY_DEBUG 0x48d7
|
|
#define CAR_mmBPHYC_UNIPHY1_UNIPHY_DEBUG 0x48f7
|
|
#define CAR_mmBPHYC_UNIPHY2_UNIPHY_DEBUG 0x4917
|
|
#define CAR_mmBPHYC_UNIPHY3_UNIPHY_DEBUG 0x4937
|
|
#define CAR_mmBPHYC_UNIPHY4_UNIPHY_DEBUG 0x4957
|
|
#define CAR_mmBPHYC_UNIPHY5_UNIPHY_DEBUG 0x4977
|
|
#define CAR_mmBPHYC_UNIPHY6_UNIPHY_DEBUG 0x4997
|
|
#define CAR_mmBPHYC_UNIPHY7_UNIPHY_DEBUG 0x49d7
|
|
#define CAR_mmBPHYC_UNIPHY8_UNIPHY_DEBUG 0x49f7
|
|
#define CAR_mmDPG_PIPE_ARBITRATION_CONTROL1 0x1b30
|
|
#define CAR_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1b30
|
|
#define CAR_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1d30
|
|
#define CAR_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x1f30
|
|
#define CAR_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4130
|
|
#define CAR_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4330
|
|
#define CAR_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4530
|
|
#define CAR_mmDPG_PIPE_ARBITRATION_CONTROL2 0x1b31
|
|
#define CAR_mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1b31
|
|
#define CAR_mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1d31
|
|
#define CAR_mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x1f31
|
|
#define CAR_mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4131
|
|
#define CAR_mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4331
|
|
#define CAR_mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4531
|
|
#define CAR_mmDPG_WATERMARK_MASK_CONTROL 0x1b32
|
|
#define CAR_mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 0x1b32
|
|
#define CAR_mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 0x1d32
|
|
#define CAR_mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 0x1f32
|
|
#define CAR_mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 0x4132
|
|
#define CAR_mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 0x4332
|
|
#define CAR_mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 0x4532
|
|
#define CAR_mmDPG_PIPE_URGENCY_CONTROL 0x1b33
|
|
#define CAR_mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1b33
|
|
#define CAR_mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1d33
|
|
#define CAR_mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x1f33
|
|
#define CAR_mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4133
|
|
#define CAR_mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4333
|
|
#define CAR_mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4533
|
|
#define CAR_mmDPG_PIPE_DPM_CONTROL 0x1b34
|
|
#define CAR_mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1b34
|
|
#define CAR_mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1d34
|
|
#define CAR_mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x1f34
|
|
#define CAR_mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4134
|
|
#define CAR_mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4334
|
|
#define CAR_mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4534
|
|
#define CAR_mmDPG_PIPE_STUTTER_CONTROL 0x1b35
|
|
#define CAR_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1b35
|
|
#define CAR_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1d35
|
|
#define CAR_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x1f35
|
|
#define CAR_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4135
|
|
#define CAR_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4335
|
|
#define CAR_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4535
|
|
#define CAR_mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36
|
|
#define CAR_mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1b36
|
|
#define CAR_mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1d36
|
|
#define CAR_mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1f36
|
|
#define CAR_mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136
|
|
#define CAR_mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4336
|
|
#define CAR_mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4536
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|
#define CAR_mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37
|
|
#define CAR_mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1b37
|
|
#define CAR_mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1d37
|
|
#define CAR_mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1f37
|
|
#define CAR_mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137
|
|
#define CAR_mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4337
|
|
#define CAR_mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4537
|
|
#define CAR_mmDPG_REPEATER_PROGRAM 0x1b3a
|
|
#define CAR_mmDMIF_PG0_DPG_REPEATER_PROGRAM 0x1b3a
|
|
#define CAR_mmDMIF_PG1_DPG_REPEATER_PROGRAM 0x1d3a
|
|
#define CAR_mmDMIF_PG2_DPG_REPEATER_PROGRAM 0x1f3a
|
|
#define CAR_mmDMIF_PG3_DPG_REPEATER_PROGRAM 0x413a
|
|
#define CAR_mmDMIF_PG4_DPG_REPEATER_PROGRAM 0x433a
|
|
#define CAR_mmDMIF_PG5_DPG_REPEATER_PROGRAM 0x453a
|
|
#define CAR_mmDPG_HW_DEBUG_A 0x1b3b
|
|
#define CAR_mmDMIF_PG0_DPG_HW_DEBUG_A 0x1b3b
|
|
#define CAR_mmDMIF_PG1_DPG_HW_DEBUG_A 0x1d3b
|
|
#define CAR_mmDMIF_PG2_DPG_HW_DEBUG_A 0x1f3b
|
|
#define CAR_mmDMIF_PG3_DPG_HW_DEBUG_A 0x413b
|
|
#define CAR_mmDMIF_PG4_DPG_HW_DEBUG_A 0x433b
|
|
#define CAR_mmDMIF_PG5_DPG_HW_DEBUG_A 0x453b
|
|
#define CAR_mmDPG_HW_DEBUG_B 0x1b3c
|
|
#define CAR_mmDMIF_PG0_DPG_HW_DEBUG_B 0x1b3c
|
|
#define CAR_mmDMIF_PG1_DPG_HW_DEBUG_B 0x1d3c
|
|
#define CAR_mmDMIF_PG2_DPG_HW_DEBUG_B 0x1f3c
|
|
#define CAR_mmDMIF_PG3_DPG_HW_DEBUG_B 0x413c
|
|
#define CAR_mmDMIF_PG4_DPG_HW_DEBUG_B 0x433c
|
|
#define CAR_mmDMIF_PG5_DPG_HW_DEBUG_B 0x453c
|
|
#define CAR_mmDPG_HW_DEBUG_11 0x1b3d
|
|
#define CAR_mmDMIF_PG0_DPG_HW_DEBUG_11 0x1b3d
|
|
#define CAR_mmDMIF_PG1_DPG_HW_DEBUG_11 0x1d3d
|
|
#define CAR_mmDMIF_PG2_DPG_HW_DEBUG_11 0x1f3d
|
|
#define CAR_mmDMIF_PG3_DPG_HW_DEBUG_11 0x413d
|
|
#define CAR_mmDMIF_PG4_DPG_HW_DEBUG_11 0x433d
|
|
#define CAR_mmDMIF_PG5_DPG_HW_DEBUG_11 0x453d
|
|
#define CAR_mmDPG_CHK_PRE_PROC_CNTL 0x1b3e
|
|
#define CAR_mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL 0x1b3e
|
|
#define CAR_mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL 0x1d3e
|
|
#define CAR_mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL 0x1f3e
|
|
#define CAR_mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL 0x413e
|
|
#define CAR_mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL 0x433e
|
|
#define CAR_mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL 0x453e
|
|
#define CAR_mmDPG_TEST_DEBUG_INDEX 0x1b38
|
|
#define CAR_mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1b38
|
|
#define CAR_mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1d38
|
|
#define CAR_mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x1f38
|
|
#define CAR_mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4138
|
|
#define CAR_mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4338
|
|
#define CAR_mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4538
|
|
#define CAR_mmDPG_TEST_DEBUG_DATA 0x1b39
|
|
#define CAR_mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1b39
|
|
#define CAR_mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1d39
|
|
#define CAR_mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x1f39
|
|
#define CAR_mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4139
|
|
#define CAR_mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4339
|
|
#define CAR_mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4539
|
|
#define CAR_mmDPGV0_PIPE_ARBITRATION_CONTROL1 0x4730
|
|
#define CAR_mmDPGV1_PIPE_ARBITRATION_CONTROL1 0x473d
|
|
#define CAR_mmDPGV0_PIPE_ARBITRATION_CONTROL2 0x4731
|
|
#define CAR_mmDPGV1_PIPE_ARBITRATION_CONTROL2 0x473e
|
|
#define CAR_mmDPGV0_WATERMARK_MASK_CONTROL 0x4732
|
|
#define CAR_mmDPGV1_WATERMARK_MASK_CONTROL 0x473f
|
|
#define CAR_mmDPGV0_PIPE_URGENCY_CONTROL 0x4733
|
|
#define CAR_mmDPGV1_PIPE_URGENCY_CONTROL 0x4740
|
|
#define CAR_mmDPGV0_PIPE_DPM_CONTROL 0x4734
|
|
#define CAR_mmDPGV1_PIPE_DPM_CONTROL 0x4741
|
|
#define CAR_mmDPGV0_PIPE_STUTTER_CONTROL 0x4735
|
|
#define CAR_mmDPGV1_PIPE_STUTTER_CONTROL 0x4742
|
|
#define CAR_mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736
|
|
#define CAR_mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4743
|
|
#define CAR_mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737
|
|
#define CAR_mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH 0x4744
|
|
#define CAR_mmDPGV0_REPEATER_PROGRAM 0x4738
|
|
#define CAR_mmDPGV1_REPEATER_PROGRAM 0x4745
|
|
#define CAR_mmDPGV0_HW_DEBUG_A 0x4739
|
|
#define CAR_mmDPGV1_HW_DEBUG_A 0x4746
|
|
#define CAR_mmDPGV0_HW_DEBUG_B 0x473a
|
|
#define CAR_mmDPGV1_HW_DEBUG_B 0x4747
|
|
#define CAR_mmDPGV0_HW_DEBUG_11 0x473b
|
|
#define CAR_mmDPGV1_HW_DEBUG_11 0x4748
|
|
#define CAR_mmDPGV0_CHK_PRE_PROC_CNTL 0x473c
|
|
#define CAR_mmDPGV1_CHK_PRE_PROC_CNTL 0x4749
|
|
#define CAR_mmDPGV_TEST_DEBUG_INDEX 0x474e
|
|
#define CAR_mmDPGV_TEST_DEBUG_DATA 0x474f
|
|
#define CAR_ixDPGV0_DEBUG00_DMIFARB 0x1
|
|
#define CAR_ixDPGV1_DEBUG00_DMIFARB 0x6a
|
|
#define CAR_ixDPGV0_DEBUG01_DMIFARB 0x2
|
|
#define CAR_ixDPGV1_DEBUG01_DMIFARB 0x6b
|
|
#define CAR_ixDPGV0_DEBUG02_DMIFARB 0x3
|
|
#define CAR_ixDPGV1_DEBUG02_DMIFARB 0x6c
|
|
#define CAR_ixDPGV0_DEBUG03_DMIFARB 0x4
|
|
#define CAR_ixDPGV1_DEBUG03_DMIFARB 0x6d
|
|
#define CAR_ixDPGV0_DEBUG04_DMIFARB 0x5
|
|
#define CAR_ixDPGV1_DEBUG04_DMIFARB 0x6e
|
|
#define CAR_ixDPGV0_DEBUG00 0x6
|
|
#define CAR_ixDPGV1_DEBUG00 0x6f
|
|
#define CAR_ixDPGV0_DEBUG01 0x7
|
|
#define CAR_ixDPGV1_DEBUG01 0x70
|
|
#define CAR_ixDPGV0_DEBUG02 0x8
|
|
#define CAR_ixDPGV1_DEBUG02 0x71
|
|
#define CAR_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
|
|
#define CAR_mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
|
|
#define CAR_ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0xf00
|
|
#define CAR_ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0xf02
|
|
#define CAR_ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0xf04
|
|
#define CAR_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
|
|
#define CAR_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
|
|
#define CAR_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
|
|
#define CAR_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
|
|
#define CAR_ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
|
|
#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
|
|
#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
|
|
#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
|
|
#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
|
|
#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
|
|
#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
|
|
#define CAR_ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
|
|
#define CAR_mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x1828
|
|
#define CAR_mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x1829
|
|
#define CAR_mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x182a
|
|
#define CAR_mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x182b
|
|
#define CAR_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x182c
|
|
#define CAR_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x182d
|
|
#define CAR_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x182e
|
|
#define CAR_mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x182f
|
|
#define CAR_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1830
|
|
#define CAR_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x1831
|
|
#define CAR_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1832
|
|
#define CAR_mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1833
|
|
#define CAR_mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x1834
|
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#define CAR_mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x1835
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#define CAR_mmAZALIA_F0_CODEC_DEBUG 0x1836
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#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET0 0x1837
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#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET1 0x1838
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#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET2 0x1839
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#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET3 0x183a
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#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET4 0x183b
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#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET5 0x183c
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#define CAR_mmAZALIA_F0_GTC_GROUP_OFFSET6 0x183d
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#define CAR_mmGLOBAL_CAPABILITIES 0x0
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#define CAR_mmMINOR_VERSION 0x0
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#define CAR_mmMAJOR_VERSION 0x0
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#define CAR_mmOUTPUT_PAYLOAD_CAPABILITY 0x1
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#define CAR_mmINPUT_PAYLOAD_CAPABILITY 0x1
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#define CAR_mmGLOBAL_CONTROL 0x2
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#define CAR_mmWAKE_ENABLE 0x3
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#define CAR_mmSTATE_CHANGE_STATUS 0x3
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#define CAR_mmGLOBAL_STATUS 0x4
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#define CAR_mmOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x6
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#define CAR_mmINPUT_STREAM_PAYLOAD_CAPABILITY 0x6
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#define CAR_mmINTERRUPT_CONTROL 0x8
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#define CAR_mmINTERRUPT_STATUS 0x9
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#define CAR_mmWALL_CLOCK_COUNTER 0xc
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#define CAR_mmSTREAM_SYNCHRONIZATION 0xe
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#define CAR_mmCORB_LOWER_BASE_ADDRESS 0x10
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#define CAR_mmCORB_UPPER_BASE_ADDRESS 0x11
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#define CAR_mmCORB_WRITE_POINTER 0x12
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#define CAR_mmCORB_READ_POINTER 0x12
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#define CAR_mmCORB_CONTROL 0x13
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#define CAR_mmCORB_STATUS 0x13
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#define CAR_mmCORB_SIZE 0x13
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#define CAR_mmRIRB_LOWER_BASE_ADDRESS 0x14
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#define CAR_mmRIRB_UPPER_BASE_ADDRESS 0x15
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#define CAR_mmRIRB_WRITE_POINTER 0x16
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#define CAR_mmRESPONSE_INTERRUPT_COUNT 0x16
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#define CAR_mmRIRB_CONTROL 0x17
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#define CAR_mmRIRB_STATUS 0x17
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#define CAR_mmRIRB_SIZE 0x17
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#define CAR_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x18
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#define CAR_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
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#define CAR_mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
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#define CAR_mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x19
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#define CAR_mmIMMEDIATE_COMMAND_STATUS 0x1a
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#define CAR_mmDMA_POSITION_LOWER_BASE_ADDRESS 0x1c
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#define CAR_mmDMA_POSITION_UPPER_BASE_ADDRESS 0x1d
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#define CAR_mmWALL_CLOCK_COUNTER_ALIAS 0x80c
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#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x20
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#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x21
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#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x22
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#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x23
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#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x24
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#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_FORMAT 0x24
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#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x26
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#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x27
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#define CAR_mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x821
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#define CAR_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x18
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#define CAR_mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x18
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#define CAR_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
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#define CAR_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
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#define CAR_ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
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#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
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#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
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#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
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#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
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#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
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#define CAR_ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
|
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#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
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#define CAR_ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
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#define CAR_ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
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#define CAR_ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
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#define CAR_ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
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#define CAR_ixAUDIO_DESCRIPTOR0 0x1
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#define CAR_ixAUDIO_DESCRIPTOR1 0x2
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#define CAR_ixAUDIO_DESCRIPTOR2 0x3
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#define CAR_ixAUDIO_DESCRIPTOR3 0x4
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#define CAR_ixAUDIO_DESCRIPTOR4 0x5
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#define CAR_ixAUDIO_DESCRIPTOR5 0x6
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#define CAR_ixAUDIO_DESCRIPTOR6 0x7
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#define CAR_ixAUDIO_DESCRIPTOR7 0x8
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#define CAR_ixAUDIO_DESCRIPTOR8 0x9
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#define CAR_ixAUDIO_DESCRIPTOR9 0xa
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#define CAR_ixAUDIO_DESCRIPTOR10 0xb
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#define CAR_ixAUDIO_DESCRIPTOR11 0xc
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#define CAR_ixAUDIO_DESCRIPTOR12 0xd
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#define CAR_ixAUDIO_DESCRIPTOR13 0xe
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x1
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x2
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x3
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x4
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#define CAR_ixSINK_DESCRIPTION0 0x5
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#define CAR_ixSINK_DESCRIPTION1 0x6
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#define CAR_ixSINK_DESCRIPTION2 0x7
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#define CAR_ixSINK_DESCRIPTION3 0x8
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#define CAR_ixSINK_DESCRIPTION4 0x9
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#define CAR_ixSINK_DESCRIPTION5 0xa
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#define CAR_ixSINK_DESCRIPTION6 0xb
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#define CAR_ixSINK_DESCRIPTION7 0xc
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#define CAR_ixSINK_DESCRIPTION8 0xd
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#define CAR_ixSINK_DESCRIPTION9 0xe
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#define CAR_ixSINK_DESCRIPTION10 0xf
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#define CAR_ixSINK_DESCRIPTION11 0x10
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#define CAR_ixSINK_DESCRIPTION12 0x11
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#define CAR_ixSINK_DESCRIPTION13 0x12
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#define CAR_ixSINK_DESCRIPTION14 0x13
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#define CAR_ixSINK_DESCRIPTION15 0x14
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#define CAR_ixSINK_DESCRIPTION16 0x15
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#define CAR_ixSINK_DESCRIPTION17 0x16
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
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#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
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#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
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#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
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#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
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#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
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#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
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#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
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#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
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#define CAR_ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
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#define CAR_ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
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#define CAR_ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
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#define CAR_mmAZALIA_CONTROLLER_CLOCK_GATING 0x17e4
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#define CAR_mmAZALIA_AUDIO_DTO 0x17e5
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#define CAR_mmAZALIA_AUDIO_DTO_CONTROL 0x17e6
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#define CAR_mmAZALIA_SCLK_CONTROL 0x17e7
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#define CAR_mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17e8
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#define CAR_mmAZALIA_DATA_DMA_CONTROL 0x17e9
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#define CAR_mmAZALIA_BDL_DMA_CONTROL 0x17ea
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#define CAR_mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb
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#define CAR_mmAZALIA_CORB_DMA_CONTROL 0x17ec
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#define CAR_mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17f3
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#define CAR_mmAZALIA_CYCLIC_BUFFER_SYNC 0x17f4
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#define CAR_mmAZALIA_GLOBAL_CAPABILITIES 0x17f5
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#define CAR_mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17f6
|
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#define CAR_mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17f7
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#define CAR_mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x17f8
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#define CAR_mmAZALIA_CONTROLLER_DEBUG 0x17f9
|
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#define CAR_mmAZALIA_MEM_PWR_CTRL 0x1810
|
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#define CAR_mmAZALIA_MEM_PWR_STATUS 0x1811
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#define CAR_mmDCI_PG_DEBUG_CONFIG 0x1812
|
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#define CAR_mmAZALIA_INPUT_CRC0_CONTROL0 0x17fb
|
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#define CAR_mmAZALIA_INPUT_CRC0_CONTROL1 0x17fc
|
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#define CAR_mmAZALIA_INPUT_CRC0_CONTROL2 0x17fd
|
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#define CAR_mmAZALIA_INPUT_CRC0_CONTROL3 0x17fe
|
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#define CAR_mmAZALIA_INPUT_CRC0_RESULT 0x17ff
|
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#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL0 0x0
|
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#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL1 0x1
|
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#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL2 0x2
|
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#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL3 0x3
|
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#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL4 0x4
|
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#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL5 0x5
|
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#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL6 0x6
|
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#define CAR_ixAZALIA_INPUT_CRC0_CHANNEL7 0x7
|
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#define CAR_mmAZALIA_INPUT_CRC1_CONTROL0 0x1800
|
|
#define CAR_mmAZALIA_INPUT_CRC1_CONTROL1 0x1801
|
|
#define CAR_mmAZALIA_INPUT_CRC1_CONTROL2 0x1802
|
|
#define CAR_mmAZALIA_INPUT_CRC1_CONTROL3 0x1803
|
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#define CAR_mmAZALIA_INPUT_CRC1_RESULT 0x1804
|
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#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL0 0x0
|
|
#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL1 0x1
|
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#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL2 0x2
|
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#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL3 0x3
|
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#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL4 0x4
|
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#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL5 0x5
|
|
#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL6 0x6
|
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#define CAR_ixAZALIA_INPUT_CRC1_CHANNEL7 0x7
|
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#define CAR_mmAZALIA_CRC0_CONTROL0 0x1805
|
|
#define CAR_mmAZALIA_CRC0_CONTROL1 0x1806
|
|
#define CAR_mmAZALIA_CRC0_CONTROL2 0x1807
|
|
#define CAR_mmAZALIA_CRC0_CONTROL3 0x1808
|
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#define CAR_mmAZALIA_CRC0_RESULT 0x1809
|
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#define CAR_ixAZALIA_CRC0_CHANNEL0 0x0
|
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#define CAR_ixAZALIA_CRC0_CHANNEL1 0x1
|
|
#define CAR_ixAZALIA_CRC0_CHANNEL2 0x2
|
|
#define CAR_ixAZALIA_CRC0_CHANNEL3 0x3
|
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#define CAR_ixAZALIA_CRC0_CHANNEL4 0x4
|
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#define CAR_ixAZALIA_CRC0_CHANNEL5 0x5
|
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#define CAR_ixAZALIA_CRC0_CHANNEL6 0x6
|
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#define CAR_ixAZALIA_CRC0_CHANNEL7 0x7
|
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#define CAR_mmAZALIA_CRC1_CONTROL0 0x180a
|
|
#define CAR_mmAZALIA_CRC1_CONTROL1 0x180b
|
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#define CAR_mmAZALIA_CRC1_CONTROL2 0x180c
|
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#define CAR_mmAZALIA_CRC1_CONTROL3 0x180d
|
|
#define CAR_mmAZALIA_CRC1_RESULT 0x180e
|
|
#define CAR_ixAZALIA_CRC1_CHANNEL0 0x0
|
|
#define CAR_ixAZALIA_CRC1_CHANNEL1 0x1
|
|
#define CAR_ixAZALIA_CRC1_CHANNEL2 0x2
|
|
#define CAR_ixAZALIA_CRC1_CHANNEL3 0x3
|
|
#define CAR_ixAZALIA_CRC1_CHANNEL4 0x4
|
|
#define CAR_ixAZALIA_CRC1_CHANNEL5 0x5
|
|
#define CAR_ixAZALIA_CRC1_CHANNEL6 0x6
|
|
#define CAR_ixAZALIA_CRC1_CHANNEL7 0x7
|
|
#define CAR_mmAZ_TEST_DEBUG_INDEX 0x181f
|
|
#define CAR_mmAZ_TEST_DEBUG_DATA 0x1820
|
|
#define CAR_mmAZALIA_STREAM_INDEX 0x1780
|
|
#define CAR_mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x1780
|
|
#define CAR_mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x1782
|
|
#define CAR_mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x1784
|
|
#define CAR_mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x1786
|
|
#define CAR_mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x1788
|
|
#define CAR_mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x178a
|
|
#define CAR_mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x178c
|
|
#define CAR_mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x178e
|
|
#define CAR_mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x59c0
|
|
#define CAR_mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x59c2
|
|
#define CAR_mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x59c4
|
|
#define CAR_mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x59c6
|
|
#define CAR_mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x59c8
|
|
#define CAR_mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x59ca
|
|
#define CAR_mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x59cc
|
|
#define CAR_mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x59ce
|
|
#define CAR_mmAZALIA_STREAM_DATA 0x1781
|
|
#define CAR_mmAZF0STREAM0_AZALIA_STREAM_DATA 0x1781
|
|
#define CAR_mmAZF0STREAM1_AZALIA_STREAM_DATA 0x1783
|
|
#define CAR_mmAZF0STREAM2_AZALIA_STREAM_DATA 0x1785
|
|
#define CAR_mmAZF0STREAM3_AZALIA_STREAM_DATA 0x1787
|
|
#define CAR_mmAZF0STREAM4_AZALIA_STREAM_DATA 0x1789
|
|
#define CAR_mmAZF0STREAM5_AZALIA_STREAM_DATA 0x178b
|
|
#define CAR_mmAZF0STREAM6_AZALIA_STREAM_DATA 0x178d
|
|
#define CAR_mmAZF0STREAM7_AZALIA_STREAM_DATA 0x178f
|
|
#define CAR_mmAZF0STREAM8_AZALIA_STREAM_DATA 0x59c1
|
|
#define CAR_mmAZF0STREAM9_AZALIA_STREAM_DATA 0x59c3
|
|
#define CAR_mmAZF0STREAM10_AZALIA_STREAM_DATA 0x59c5
|
|
#define CAR_mmAZF0STREAM11_AZALIA_STREAM_DATA 0x59c7
|
|
#define CAR_mmAZF0STREAM12_AZALIA_STREAM_DATA 0x59c9
|
|
#define CAR_mmAZF0STREAM13_AZALIA_STREAM_DATA 0x59cb
|
|
#define CAR_mmAZF0STREAM14_AZALIA_STREAM_DATA 0x59cd
|
|
#define CAR_mmAZF0STREAM15_AZALIA_STREAM_DATA 0x59cf
|
|
#define CAR_ixAZALIA_FIFO_SIZE_CONTROL 0x0
|
|
#define CAR_ixAZALIA_LATENCY_COUNTER_CONTROL 0x1
|
|
#define CAR_ixAZALIA_WORSTCASE_LATENCY_COUNT 0x2
|
|
#define CAR_ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x3
|
|
#define CAR_ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x4
|
|
#define CAR_ixAZALIA_STREAM_DEBUG 0x5
|
|
#define CAR_mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8
|
|
#define CAR_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17a8
|
|
#define CAR_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17ac
|
|
#define CAR_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b0
|
|
#define CAR_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b4
|
|
#define CAR_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17b8
|
|
#define CAR_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17bc
|
|
#define CAR_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c0
|
|
#define CAR_mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x17c4
|
|
#define CAR_mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9
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#define CAR_mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17a9
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#define CAR_mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17ad
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#define CAR_mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b1
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#define CAR_mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b5
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#define CAR_mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17b9
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#define CAR_mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17bd
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#define CAR_mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c1
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#define CAR_mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x17c5
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#define CAR_ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0
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#define CAR_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1
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#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2
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#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3
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#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4
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#define CAR_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x5
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#define CAR_ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6
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#define CAR_ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x7
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#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x8
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#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x9
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#define CAR_ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG 0xa
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#define CAR_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0xc
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#define CAR_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0xd
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#define CAR_ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0xe
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#define CAR_ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20
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#define CAR_ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x21
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x23
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x24
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2a
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2b
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2c
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2d
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2e
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2f
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x57
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x58
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
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#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x59
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#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x5a
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#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x5b
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#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x5c
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#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x5d
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#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x5e
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#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x5f
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#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x60
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#define CAR_ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x61
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#define CAR_ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x62
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x63
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x65
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x67
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x68
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x69
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#define CAR_ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x6a
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#define CAR_ixAZALIA_F0_AUDIO_ENABLE_STATUS 0x6b
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#define CAR_ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x6c
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#define CAR_ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x6d
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#define CAR_ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x6e
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#define CAR_mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4
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#define CAR_mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d4
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#define CAR_mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59d8
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#define CAR_mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59dc
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#define CAR_mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e0
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#define CAR_mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e4
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#define CAR_mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59e8
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#define CAR_mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59ec
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#define CAR_mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x59f0
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#define CAR_mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5
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#define CAR_mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d5
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#define CAR_mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59d9
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#define CAR_mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59dd
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#define CAR_mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e1
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#define CAR_mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e5
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#define CAR_mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59e9
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#define CAR_mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59ed
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#define CAR_mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x59f1
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#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0
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#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x1
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#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2
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#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x3
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#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x4
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#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x5
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#define CAR_ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x20
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x21
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x22
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x23
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x24
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x36
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x37
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x38
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x53
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x54
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x55
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x67
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x68
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x64
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x65
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#define CAR_ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x66
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#define CAR_mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x18
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#define CAR_mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x18
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#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
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#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
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#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
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#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
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#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
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#define CAR_ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
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#define CAR_ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
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#define CAR_mmBLND_CONTROL 0x1b6d
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#define CAR_mmBLND0_BLND_CONTROL 0x1b6d
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#define CAR_mmBLND1_BLND_CONTROL 0x1d6d
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#define CAR_mmBLND2_BLND_CONTROL 0x1f6d
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#define CAR_mmBLND3_BLND_CONTROL 0x416d
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#define CAR_mmBLND4_BLND_CONTROL 0x436d
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#define CAR_mmBLND5_BLND_CONTROL 0x456d
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#define CAR_mmBLND_SM_CONTROL2 0x1b6e
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#define CAR_mmBLND0_BLND_SM_CONTROL2 0x1b6e
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#define CAR_mmBLND1_BLND_SM_CONTROL2 0x1d6e
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#define CAR_mmBLND2_BLND_SM_CONTROL2 0x1f6e
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#define CAR_mmBLND3_BLND_SM_CONTROL2 0x416e
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#define CAR_mmBLND4_BLND_SM_CONTROL2 0x436e
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#define CAR_mmBLND5_BLND_SM_CONTROL2 0x456e
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#define CAR_mmBLND_CONTROL2 0x1b6f
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#define CAR_mmBLND0_BLND_CONTROL2 0x1b6f
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#define CAR_mmBLND1_BLND_CONTROL2 0x1d6f
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#define CAR_mmBLND2_BLND_CONTROL2 0x1f6f
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#define CAR_mmBLND3_BLND_CONTROL2 0x416f
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#define CAR_mmBLND4_BLND_CONTROL2 0x436f
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#define CAR_mmBLND5_BLND_CONTROL2 0x456f
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#define CAR_mmBLND_UPDATE 0x1b70
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#define CAR_mmBLND0_BLND_UPDATE 0x1b70
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#define CAR_mmBLND1_BLND_UPDATE 0x1d70
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#define CAR_mmBLND2_BLND_UPDATE 0x1f70
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#define CAR_mmBLND3_BLND_UPDATE 0x4170
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#define CAR_mmBLND4_BLND_UPDATE 0x4370
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#define CAR_mmBLND5_BLND_UPDATE 0x4570
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#define CAR_mmBLND_UNDERFLOW_INTERRUPT 0x1b71
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#define CAR_mmBLND0_BLND_UNDERFLOW_INTERRUPT 0x1b71
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#define CAR_mmBLND1_BLND_UNDERFLOW_INTERRUPT 0x1d71
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#define CAR_mmBLND2_BLND_UNDERFLOW_INTERRUPT 0x1f71
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#define CAR_mmBLND3_BLND_UNDERFLOW_INTERRUPT 0x4171
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#define CAR_mmBLND4_BLND_UNDERFLOW_INTERRUPT 0x4371
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#define CAR_mmBLND5_BLND_UNDERFLOW_INTERRUPT 0x4571
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#define CAR_mmBLND_V_UPDATE_LOCK 0x1b73
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#define CAR_mmBLND0_BLND_V_UPDATE_LOCK 0x1b73
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#define CAR_mmBLND1_BLND_V_UPDATE_LOCK 0x1d73
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#define CAR_mmBLND2_BLND_V_UPDATE_LOCK 0x1f73
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#define CAR_mmBLND3_BLND_V_UPDATE_LOCK 0x4173
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#define CAR_mmBLND4_BLND_V_UPDATE_LOCK 0x4373
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#define CAR_mmBLND5_BLND_V_UPDATE_LOCK 0x4573
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#define CAR_mmBLND_REG_UPDATE_STATUS 0x1b77
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#define CAR_mmBLND0_BLND_REG_UPDATE_STATUS 0x1b77
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#define CAR_mmBLND1_BLND_REG_UPDATE_STATUS 0x1d77
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#define CAR_mmBLND2_BLND_REG_UPDATE_STATUS 0x1f77
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#define CAR_mmBLND3_BLND_REG_UPDATE_STATUS 0x4177
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#define CAR_mmBLND4_BLND_REG_UPDATE_STATUS 0x4377
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#define CAR_mmBLND5_BLND_REG_UPDATE_STATUS 0x4577
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#define CAR_mmBLND_DEBUG 0x1b74
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#define CAR_mmBLND0_BLND_DEBUG 0x1b74
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#define CAR_mmBLND1_BLND_DEBUG 0x1d74
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#define CAR_mmBLND2_BLND_DEBUG 0x1f74
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#define CAR_mmBLND3_BLND_DEBUG 0x4174
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#define CAR_mmBLND4_BLND_DEBUG 0x4374
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#define CAR_mmBLND5_BLND_DEBUG 0x4574
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#define CAR_mmBLND_TEST_DEBUG_INDEX 0x1b75
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#define CAR_mmBLND0_BLND_TEST_DEBUG_INDEX 0x1b75
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#define CAR_mmBLND1_BLND_TEST_DEBUG_INDEX 0x1d75
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#define CAR_mmBLND2_BLND_TEST_DEBUG_INDEX 0x1f75
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#define CAR_mmBLND3_BLND_TEST_DEBUG_INDEX 0x4175
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#define CAR_mmBLND4_BLND_TEST_DEBUG_INDEX 0x4375
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#define CAR_mmBLND5_BLND_TEST_DEBUG_INDEX 0x4575
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#define CAR_mmBLND_TEST_DEBUG_DATA 0x1b76
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#define CAR_mmBLND0_BLND_TEST_DEBUG_DATA 0x1b76
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#define CAR_mmBLND1_BLND_TEST_DEBUG_DATA 0x1d76
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#define CAR_mmBLND2_BLND_TEST_DEBUG_DATA 0x1f76
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#define CAR_mmBLND3_BLND_TEST_DEBUG_DATA 0x4176
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#define CAR_mmBLND4_BLND_TEST_DEBUG_DATA 0x4376
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#define CAR_mmBLND5_BLND_TEST_DEBUG_DATA 0x4576
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#define CAR_mmWB_ENABLE 0x5e18
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#define CAR_mmWB_EC_CONFIG 0x5e19
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#define CAR_mmCNV_MODE 0x5e1a
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#define CAR_mmCNV_WINDOW_START 0x5e1b
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#define CAR_mmCNV_WINDOW_SIZE 0x5e1c
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#define CAR_mmCNV_UPDATE 0x5e1d
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#define CAR_mmCNV_SOURCE_SIZE 0x5e1e
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#define CAR_mmCNV_CSC_CONTROL 0x5e1f
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#define CAR_mmCNV_CSC_C11_C12 0x5e20
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#define CAR_mmCNV_CSC_C13_C14 0x5e21
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#define CAR_mmCNV_CSC_C21_C22 0x5e22
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#define CAR_mmCNV_CSC_C23_C24 0x5e23
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#define CAR_mmCNV_CSC_C31_C32 0x5e24
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#define CAR_mmCNV_CSC_C33_C34 0x5e25
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#define CAR_mmCNV_CSC_ROUND_OFFSET_R 0x5e26
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#define CAR_mmCNV_CSC_ROUND_OFFSET_G 0x5e27
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#define CAR_mmCNV_CSC_ROUND_OFFSET_B 0x5e28
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#define CAR_mmCNV_CSC_CLAMP_R 0x5e29
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#define CAR_mmCNV_CSC_CLAMP_G 0x5e2a
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#define CAR_mmCNV_CSC_CLAMP_B 0x5e2b
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#define CAR_mmCNV_TEST_CNTL 0x5e2c
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#define CAR_mmCNV_TEST_CRC_RED 0x5e2d
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#define CAR_mmCNV_TEST_CRC_GREEN 0x5e2e
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#define CAR_mmCNV_TEST_CRC_BLUE 0x5e2f
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#define CAR_mmWB_DEBUG_CTRL 0x5e30
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#define CAR_mmWB_DBG_MODE 0x5e31
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#define CAR_mmWB_HW_DEBUG 0x5e32
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#define CAR_mmCNV_INPUT_SELECT 0x5e33
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#define CAR_mmWB_SOFT_RESET 0x5e36
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#define CAR_mmCNV_TEST_DEBUG_INDEX 0x5e34
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#define CAR_mmCNV_TEST_DEBUG_DATA 0x5e35
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#define CAR_mmDCFE_CLOCK_CONTROL 0x1b00
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#define CAR_mmDCFE0_DCFE_CLOCK_CONTROL 0x1b00
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#define CAR_mmDCFE1_DCFE_CLOCK_CONTROL 0x1d00
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#define CAR_mmDCFE2_DCFE_CLOCK_CONTROL 0x1f00
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#define CAR_mmDCFE3_DCFE_CLOCK_CONTROL 0x4100
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#define CAR_mmDCFE4_DCFE_CLOCK_CONTROL 0x4300
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#define CAR_mmDCFE5_DCFE_CLOCK_CONTROL 0x4500
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#define CAR_mmDCFE_SOFT_RESET 0x1b01
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#define CAR_mmDCFE0_DCFE_SOFT_RESET 0x1b01
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#define CAR_mmDCFE1_DCFE_SOFT_RESET 0x1d01
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#define CAR_mmDCFE2_DCFE_SOFT_RESET 0x1f01
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#define CAR_mmDCFE3_DCFE_SOFT_RESET 0x4101
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#define CAR_mmDCFE4_DCFE_SOFT_RESET 0x4301
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#define CAR_mmDCFE5_DCFE_SOFT_RESET 0x4501
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#define CAR_mmDCFE_DBG_CONFIG 0x1b02
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#define CAR_mmDCFE0_DCFE_DBG_CONFIG 0x1b02
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#define CAR_mmDCFE1_DCFE_DBG_CONFIG 0x1d02
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#define CAR_mmDCFE2_DCFE_DBG_CONFIG 0x1f02
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#define CAR_mmDCFE3_DCFE_DBG_CONFIG 0x4102
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#define CAR_mmDCFE4_DCFE_DBG_CONFIG 0x4302
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#define CAR_mmDCFE5_DCFE_DBG_CONFIG 0x4502
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#define CAR_mmDCFE_MEM_PWR_CTRL 0x1b03
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#define CAR_mmDCFE0_DCFE_MEM_PWR_CTRL 0x1b03
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#define CAR_mmDCFE1_DCFE_MEM_PWR_CTRL 0x1d03
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#define CAR_mmDCFE2_DCFE_MEM_PWR_CTRL 0x1f03
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#define CAR_mmDCFE3_DCFE_MEM_PWR_CTRL 0x4103
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#define CAR_mmDCFE4_DCFE_MEM_PWR_CTRL 0x4303
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#define CAR_mmDCFE5_DCFE_MEM_PWR_CTRL 0x4503
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#define CAR_mmDCFE_MEM_PWR_CTRL2 0x1b04
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#define CAR_mmDCFE0_DCFE_MEM_PWR_CTRL2 0x1b04
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#define CAR_mmDCFE1_DCFE_MEM_PWR_CTRL2 0x1d04
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#define CAR_mmDCFE2_DCFE_MEM_PWR_CTRL2 0x1f04
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#define CAR_mmDCFE3_DCFE_MEM_PWR_CTRL2 0x4104
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#define CAR_mmDCFE4_DCFE_MEM_PWR_CTRL2 0x4304
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#define CAR_mmDCFE5_DCFE_MEM_PWR_CTRL2 0x4504
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#define CAR_mmDCFE_MEM_PWR_STATUS 0x1b05
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#define CAR_mmDCFE0_DCFE_MEM_PWR_STATUS 0x1b05
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#define CAR_mmDCFE1_DCFE_MEM_PWR_STATUS 0x1d05
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#define CAR_mmDCFE2_DCFE_MEM_PWR_STATUS 0x1f05
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#define CAR_mmDCFE3_DCFE_MEM_PWR_STATUS 0x4105
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#define CAR_mmDCFE4_DCFE_MEM_PWR_STATUS 0x4305
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#define CAR_mmDCFE5_DCFE_MEM_PWR_STATUS 0x4505
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#define CAR_mmDCFE_MISC 0x1b06
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#define CAR_mmDCFE0_DCFE_MISC 0x1b06
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#define CAR_mmDCFE1_DCFE_MISC 0x1d06
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#define CAR_mmDCFE2_DCFE_MISC 0x1f06
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#define CAR_mmDCFE3_DCFE_MISC 0x4106
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#define CAR_mmDCFE4_DCFE_MISC 0x4306
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#define CAR_mmDCFE5_DCFE_MISC 0x4506
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#define CAR_mmDCFEV_CLOCK_CONTROL 0x46f4
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#define CAR_mmDCFEV_SOFT_RESET 0x46f5
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#define CAR_mmDCFEV_DMIFV_CLOCK_CONTROL 0x46f6
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#define CAR_mmDCFEV_DBG_CONFIG 0x46f7
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#define CAR_mmDCFEV_DMIFV_MEM_PWR_CTRL 0x46f8
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#define CAR_mmDCFEV_DMIFV_MEM_PWR_STATUS 0x46f9
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#define CAR_mmDCFEV_MEM_PWR_CTRL 0x46fa
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#define CAR_mmDCFEV_MEM_PWR_CTRL2 0x46fb
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#define CAR_mmDCFEV_MEM_PWR_STATUS 0x46fc
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#define CAR_mmDCFEV_DMIFV_DEBUG 0x46fd
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#define CAR_mmDCFEV_MISC 0x46fe
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#define CAR_mmDC_HPD_INT_STATUS 0x1898
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#define CAR_mmHPD0_DC_HPD_INT_STATUS 0x1898
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#define CAR_mmHPD1_DC_HPD_INT_STATUS 0x18a0
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#define CAR_mmHPD2_DC_HPD_INT_STATUS 0x18a8
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#define CAR_mmHPD3_DC_HPD_INT_STATUS 0x18b0
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#define CAR_mmHPD4_DC_HPD_INT_STATUS 0x18b8
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#define CAR_mmHPD5_DC_HPD_INT_STATUS 0x18c0
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#define CAR_mmDC_HPD_INT_CONTROL 0x1899
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#define CAR_mmHPD0_DC_HPD_INT_CONTROL 0x1899
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#define CAR_mmHPD1_DC_HPD_INT_CONTROL 0x18a1
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#define CAR_mmHPD2_DC_HPD_INT_CONTROL 0x18a9
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#define CAR_mmHPD3_DC_HPD_INT_CONTROL 0x18b1
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#define CAR_mmHPD4_DC_HPD_INT_CONTROL 0x18b9
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#define CAR_mmHPD5_DC_HPD_INT_CONTROL 0x18c1
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#define CAR_mmDC_HPD_CONTROL 0x189a
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#define CAR_mmHPD0_DC_HPD_CONTROL 0x189a
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#define CAR_mmHPD1_DC_HPD_CONTROL 0x18a2
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#define CAR_mmHPD2_DC_HPD_CONTROL 0x18aa
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#define CAR_mmHPD3_DC_HPD_CONTROL 0x18b2
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#define CAR_mmHPD4_DC_HPD_CONTROL 0x18ba
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#define CAR_mmHPD5_DC_HPD_CONTROL 0x18c2
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#define CAR_mmDC_HPD_FAST_TRAIN_CNTL 0x189b
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#define CAR_mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x189b
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#define CAR_mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x18a3
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#define CAR_mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x18ab
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#define CAR_mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x18b3
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#define CAR_mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x18bb
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#define CAR_mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x18c3
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#define CAR_mmDC_HPD_TOGGLE_FILT_CNTL 0x189c
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#define CAR_mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x189c
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#define CAR_mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x18a4
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#define CAR_mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x18ac
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#define CAR_mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x18b4
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#define CAR_mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x18bc
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#define CAR_mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x18c4
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#define CAR_mmDCO_SCRATCH0 0x184e
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#define CAR_mmDCO_SCRATCH1 0x184f
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#define CAR_mmDCO_SCRATCH2 0x1850
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#define CAR_mmDCO_SCRATCH3 0x1851
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#define CAR_mmDCO_SCRATCH4 0x1852
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#define CAR_mmDCO_SCRATCH5 0x1853
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#define CAR_mmDCO_SCRATCH6 0x1854
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#define CAR_mmDCO_SCRATCH7 0x1855
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#define CAR_mmDCE_VCE_CONTROL 0x1856
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#define CAR_mmDISP_INTERRUPT_STATUS 0x1857
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#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE 0x1858
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#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE2 0x1859
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#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE3 0x185a
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#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE4 0x185b
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#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE5 0x185c
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#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE6 0x185d
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#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE7 0x185e
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#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE8 0x185f
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#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE9 0x1860
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#define CAR_mmDISP_INTERRUPT_STATUS_CONTINUE10 0x1875
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#define CAR_mmDCO_MEM_PWR_STATUS 0x1861
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#define CAR_mmDCO_MEM_PWR_STATUS1 0x1874
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#define CAR_mmDCO_MEM_PWR_CTRL 0x1862
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#define CAR_mmDCO_MEM_PWR_CTRL2 0x1863
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#define CAR_mmDCO_CLK_CNTL 0x1864
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#define CAR_mmDCO_CLK_CNTL2 0x1876
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#define CAR_mmDCO_CLK_CNTL3 0x1877
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#define CAR_mmDPDBG_CNTL 0x1866
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#define CAR_mmDPDBG_INTERRUPT 0x1867
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#define CAR_mmDCO_POWER_MANAGEMENT_CNTL 0x1868
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#define CAR_mmDCO_SOFT_RESET 0x1871
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#define CAR_mmDIG_SOFT_RESET 0x1872
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#define CAR_mmDIG_SOFT_RESET_2 0x186a
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#define CAR_mmDCO_STEREOSYNC_SEL 0x186e
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#define CAR_mmDCO_TEST_DEBUG_INDEX 0x186f
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#define CAR_mmDCO_TEST_DEBUG_DATA 0x1870
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#define CAR_mmDC_I2C_CONTROL 0x16d4
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#define CAR_mmDC_I2C_ARBITRATION 0x16d5
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#define CAR_mmDC_I2C_INTERRUPT_CONTROL 0x16d6
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#define CAR_mmDC_I2C_SW_STATUS 0x16d7
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#define CAR_mmDC_I2C_DDC1_HW_STATUS 0x16d8
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#define CAR_mmDC_I2C_DDC2_HW_STATUS 0x16d9
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#define CAR_mmDC_I2C_DDC3_HW_STATUS 0x16da
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#define CAR_mmDC_I2C_DDC4_HW_STATUS 0x16db
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#define CAR_mmDC_I2C_DDC5_HW_STATUS 0x16dc
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#define CAR_mmDC_I2C_DDC6_HW_STATUS 0x16dd
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#define CAR_mmDC_I2C_DDC1_SPEED 0x16de
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#define CAR_mmDC_I2C_DDC1_SETUP 0x16df
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#define CAR_mmDC_I2C_DDC2_SPEED 0x16e0
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#define CAR_mmDC_I2C_DDC2_SETUP 0x16e1
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#define CAR_mmDC_I2C_DDC3_SPEED 0x16e2
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#define CAR_mmDC_I2C_DDC3_SETUP 0x16e3
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#define CAR_mmDC_I2C_DDC4_SPEED 0x16e4
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#define CAR_mmDC_I2C_DDC4_SETUP 0x16e5
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#define CAR_mmDC_I2C_DDC5_SPEED 0x16e6
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#define CAR_mmDC_I2C_DDC5_SETUP 0x16e7
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#define CAR_mmDC_I2C_DDC6_SPEED 0x16e8
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#define CAR_mmDC_I2C_DDC6_SETUP 0x16e9
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#define CAR_mmDC_I2C_TRANSACTION0 0x16ea
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#define CAR_mmDC_I2C_TRANSACTION1 0x16eb
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#define CAR_mmDC_I2C_TRANSACTION2 0x16ec
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#define CAR_mmDC_I2C_TRANSACTION3 0x16ed
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#define CAR_mmDC_I2C_DATA 0x16ee
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#define CAR_mmDC_I2C_DDCVGA_HW_STATUS 0x16ef
|
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#define CAR_mmDC_I2C_DDCVGA_SPEED 0x16f0
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#define CAR_mmDC_I2C_DDCVGA_SETUP 0x16f1
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#define CAR_mmDC_I2C_EDID_DETECT_CTRL 0x16f2
|
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#define CAR_mmDC_I2C_READ_REQUEST_INTERRUPT 0x16f3
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#define CAR_mmGENERIC_I2C_CONTROL 0x16f4
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#define CAR_mmGENERIC_I2C_INTERRUPT_CONTROL 0x16f5
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#define CAR_mmGENERIC_I2C_STATUS 0x16f6
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#define CAR_mmGENERIC_I2C_SPEED 0x16f7
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#define CAR_mmGENERIC_I2C_SETUP 0x16f8
|
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#define CAR_mmGENERIC_I2C_TRANSACTION 0x16f9
|
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#define CAR_mmGENERIC_I2C_DATA 0x16fa
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#define CAR_mmGENERIC_I2C_PIN_SELECTION 0x16fb
|
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#define CAR_mmGENERIC_I2C_PIN_DEBUG 0x16fc
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#define CAR_mmBLNDV_CONTROL 0x476d
|
|
#define CAR_mmBLNDV_SM_CONTROL2 0x476e
|
|
#define CAR_mmBLNDV_CONTROL2 0x476f
|
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#define CAR_mmBLNDV_UPDATE 0x4770
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#define CAR_mmBLNDV_UNDERFLOW_INTERRUPT 0x4771
|
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#define CAR_mmBLNDV_V_UPDATE_LOCK 0x4773
|
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#define CAR_mmBLNDV_REG_UPDATE_STATUS 0x4777
|
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#define CAR_mmBLNDV_DEBUG 0x4774
|
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#define CAR_mmBLNDV_TEST_DEBUG_INDEX 0x4775
|
|
#define CAR_mmBLNDV_TEST_DEBUG_DATA 0x4776
|
|
#define CAR_mmCRTCV_H_BLANK_EARLY_NUM 0x477d
|
|
#define CAR_mmCRTCV_H_TOTAL 0x4780
|
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#define CAR_mmCRTCV_H_BLANK_START_END 0x4781
|
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#define CAR_mmCRTCV_H_SYNC_A 0x4782
|
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#define CAR_mmCRTCV_H_SYNC_A_CNTL 0x4783
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#define CAR_mmCRTCV_H_SYNC_B 0x4784
|
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#define CAR_mmCRTCV_H_SYNC_B_CNTL 0x4785
|
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#define CAR_mmCRTCV_VBI_END 0x4786
|
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#define CAR_mmCRTCV_V_TOTAL 0x4787
|
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#define CAR_mmCRTCV_V_TOTAL_MIN 0x4788
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#define CAR_mmCRTCV_V_TOTAL_MAX 0x4789
|
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#define CAR_mmCRTCV_V_TOTAL_CONTROL 0x478a
|
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#define CAR_mmCRTCV_V_TOTAL_INT_STATUS 0x478b
|
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#define CAR_mmCRTCV_VSYNC_NOM_INT_STATUS 0x478c
|
|
#define CAR_mmCRTCV_V_BLANK_START_END 0x478d
|
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#define CAR_mmCRTCV_V_SYNC_A 0x478e
|
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#define CAR_mmCRTCV_V_SYNC_A_CNTL 0x478f
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|
#define CAR_mmCRTCV_V_SYNC_B 0x4790
|
|
#define CAR_mmCRTCV_V_SYNC_B_CNTL 0x4791
|
|
#define CAR_mmCRTCV_DTMTEST_CNTL 0x4792
|
|
#define CAR_mmCRTCV_DTMTEST_STATUS_POSITION 0x4793
|
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#define CAR_mmCRTCV_TRIGA_CNTL 0x4794
|
|
#define CAR_mmCRTCV_TRIGA_MANUAL_TRIG 0x4795
|
|
#define CAR_mmCRTCV_TRIGB_CNTL 0x4796
|
|
#define CAR_mmCRTCV_TRIGB_MANUAL_TRIG 0x4797
|
|
#define CAR_mmCRTCV_FORCE_COUNT_NOW_CNTL 0x4798
|
|
#define CAR_mmCRTCV_FLOW_CONTROL 0x4799
|
|
#define CAR_mmCRTCV_STEREO_FORCE_NEXT_EYE 0x479a
|
|
#define CAR_mmCRTCV_AVSYNC_COUNTER 0x479b
|
|
#define CAR_mmCRTCV_CONTROL 0x479c
|
|
#define CAR_mmCRTCV_BLANK_CONTROL 0x479d
|
|
#define CAR_mmCRTCV_INTERLACE_CONTROL 0x479e
|
|
#define CAR_mmCRTCV_INTERLACE_STATUS 0x479f
|
|
#define CAR_mmCRTCV_FIELD_INDICATION_CONTROL 0x47a0
|
|
#define CAR_mmCRTCV_PIXEL_DATA_READBACK0 0x47a1
|
|
#define CAR_mmCRTCV_PIXEL_DATA_READBACK1 0x47a2
|
|
#define CAR_mmCRTCV_STATUS 0x47a3
|
|
#define CAR_mmCRTCV_STATUS_POSITION 0x47a4
|
|
#define CAR_mmCRTCV_NOM_VERT_POSITION 0x47a5
|
|
#define CAR_mmCRTCV_STATUS_FRAME_COUNT 0x47a6
|
|
#define CAR_mmCRTCV_STATUS_VF_COUNT 0x47a7
|
|
#define CAR_mmCRTCV_STATUS_HV_COUNT 0x47a8
|
|
#define CAR_mmCRTCV_COUNT_CONTROL 0x47a9
|
|
#define CAR_mmCRTCV_COUNT_RESET 0x47aa
|
|
#define CAR_mmCRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47ab
|
|
#define CAR_mmCRTCV_VERT_SYNC_CONTROL 0x47ac
|
|
#define CAR_mmCRTCV_STEREO_STATUS 0x47ad
|
|
#define CAR_mmCRTCV_STEREO_CONTROL 0x47ae
|
|
#define CAR_mmCRTCV_SNAPSHOT_STATUS 0x47af
|
|
#define CAR_mmCRTCV_SNAPSHOT_CONTROL 0x47b0
|
|
#define CAR_mmCRTCV_SNAPSHOT_POSITION 0x47b1
|
|
#define CAR_mmCRTCV_SNAPSHOT_FRAME 0x47b2
|
|
#define CAR_mmCRTCV_START_LINE_CONTROL 0x47b3
|
|
#define CAR_mmCRTCV_INTERRUPT_CONTROL 0x47b4
|
|
#define CAR_mmCRTCV_UPDATE_LOCK 0x47b5
|
|
#define CAR_mmCRTCV_DOUBLE_BUFFER_CONTROL 0x47b6
|
|
#define CAR_mmCRTCV_VGA_PARAMETER_CAPTURE_MODE 0x47b7
|
|
#define CAR_mmCRTCV_TEST_PATTERN_CONTROL 0x47ba
|
|
#define CAR_mmCRTCV_TEST_PATTERN_PARAMETERS 0x47bb
|
|
#define CAR_mmCRTCV_TEST_PATTERN_COLOR 0x47bc
|
|
#define CAR_mmCRTCV_MASTER_UPDATE_LOCK 0x47bd
|
|
#define CAR_mmCRTCV_MASTER_UPDATE_MODE 0x47be
|
|
#define CAR_mmCRTCV_MVP_INBAND_CNTL_INSERT 0x47bf
|
|
#define CAR_mmCRTCV_MVP_INBAND_CNTL_INSERT_TIMER 0x47c0
|
|
#define CAR_mmCRTCV_MVP_STATUS 0x47c1
|
|
#define CAR_mmCRTCV_MASTER_EN 0x47c2
|
|
#define CAR_mmCRTCV_ALLOW_STOP_OFF_V_CNT 0x47c3
|
|
#define CAR_mmCRTCV_V_UPDATE_INT_STATUS 0x47c4
|
|
#define CAR_mmCRTCV_OVERSCAN_COLOR 0x47c8
|
|
#define CAR_mmCRTCV_OVERSCAN_COLOR_EXT 0x47c9
|
|
#define CAR_mmCRTCV_BLANK_DATA_COLOR 0x47ca
|
|
#define CAR_mmCRTCV_BLANK_DATA_COLOR_EXT 0x47cb
|
|
#define CAR_mmCRTCV_BLACK_COLOR 0x47cc
|
|
#define CAR_mmCRTCV_BLACK_COLOR_EXT 0x47cd
|
|
#define CAR_mmCRTCV_VERTICAL_INTERRUPT0_POSITION 0x47ce
|
|
#define CAR_mmCRTCV_VERTICAL_INTERRUPT0_CONTROL 0x47cf
|
|
#define CAR_mmCRTCV_VERTICAL_INTERRUPT1_POSITION 0x47d0
|
|
#define CAR_mmCRTCV_VERTICAL_INTERRUPT1_CONTROL 0x47d1
|
|
#define CAR_mmCRTCV_VERTICAL_INTERRUPT2_POSITION 0x47d2
|
|
#define CAR_mmCRTCV_VERTICAL_INTERRUPT2_CONTROL 0x47d3
|
|
#define CAR_mmCRTCV_CRC_CNTL 0x47d4
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#define CAR_mmCRTCV_CRC0_WINDOWA_X_CONTROL 0x47d5
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#define CAR_mmCRTCV_CRC0_WINDOWA_Y_CONTROL 0x47d6
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#define CAR_mmCRTCV_CRC0_WINDOWB_X_CONTROL 0x47d7
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#define CAR_mmCRTCV_CRC0_WINDOWB_Y_CONTROL 0x47d8
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#define CAR_mmCRTCV_CRC0_DATA_RG 0x47d9
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#define CAR_mmCRTCV_CRC0_DATA_B 0x47da
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#define CAR_mmCRTCV_CRC1_WINDOWA_X_CONTROL 0x47db
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#define CAR_mmCRTCV_CRC1_WINDOWA_Y_CONTROL 0x47dc
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#define CAR_mmCRTCV_CRC1_WINDOWB_X_CONTROL 0x47dd
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#define CAR_mmCRTCV_CRC1_WINDOWB_Y_CONTROL 0x47de
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#define CAR_mmCRTCV_CRC1_DATA_RG 0x47df
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#define CAR_mmCRTCV_CRC1_DATA_B 0x47e0
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#define CAR_mmCRTCV_STATIC_SCREEN_CONTROL 0x47e7
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#define CAR_mmCRTCV_3D_STRUCTURE_CONTROL 0x4778
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#define CAR_mmCRTCV_GSL_VSYNC_GAP 0x4779
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#define CAR_mmCRTCV_GSL_WINDOW 0x477a
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#define CAR_mmCRTCV_GSL_CONTROL 0x477b
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#define CAR_mmCRTCV_TEST_DEBUG_INDEX 0x47c6
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#define CAR_mmCRTCV_TEST_DEBUG_DATA 0x47c7
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#define CAR_mmXDMA_MC_PCIE_CLIENT_CONFIG 0x3e0
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#define CAR_mmXDMA_LOCAL_SURFACE_TILING1 0x3e1
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#define CAR_mmXDMA_LOCAL_SURFACE_TILING2 0x3e2
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#define CAR_mmXDMA_INTERRUPT 0x3e3
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#define CAR_mmXDMA_CLOCK_GATING_CNTL 0x3e4
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#define CAR_mmXDMA_MEM_POWER_CNTL 0x3e6
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#define CAR_mmXDMA_IF_BIF_STATUS 0x3e7
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#define CAR_mmXDMA_PERF_MEAS_STATUS 0x3e8
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#define CAR_mmXDMA_IF_STATUS 0x3e9
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#define CAR_mmXDMA_TEST_DEBUG_INDEX 0x3ea
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#define CAR_mmXDMA_TEST_DEBUG_DATA 0x3eb
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#define CAR_mmXDMA_RBBMIF_RDWR_CNTL 0x3f8
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#define CAR_mmXDMA_PG_CONTROL 0x3f9
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#define CAR_mmXDMA_PG_WDATA 0x3fa
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#define CAR_mmXDMA_PG_STATUS 0x3fb
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#define CAR_mmXDMA_AON_TEST_DEBUG_INDEX 0x3fc
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#define CAR_mmXDMA_AON_TEST_DEBUG_DATA 0x3fd
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#define CAR_mmXDMA_MSTR_CNTL 0x3ec
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#define CAR_mmXDMA_MSTR_STATUS 0x3ed
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#define CAR_mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x3ee
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#define CAR_mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x3ef
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#define CAR_mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x3f0
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#define CAR_mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x3f1
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#define CAR_mmXDMA_MSTR_CMD_URGENT_CNTL 0x3f2
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#define CAR_mmXDMA_MSTR_MEM_URGENT_CNTL 0x3f3
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#define CAR_mmXDMA_MSTR_PCIE_NACK_STATUS 0x3f5
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#define CAR_mmXDMA_MSTR_MEM_NACK_STATUS 0x3f6
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#define CAR_mmXDMA_MSTR_VSYNC_GSL_CHECK 0x3f7
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#define CAR_mmXDMA_MSTR_PIPE_CNTL 0x400
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#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL 0x400
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#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL 0x410
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#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL 0x420
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#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL 0x430
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#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL 0x440
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#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL 0x450
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#define CAR_mmXDMA_MSTR_READ_COMMAND 0x401
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#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND 0x401
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#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND 0x411
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#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND 0x421
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#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND 0x431
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#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND 0x441
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#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND 0x451
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#define CAR_mmXDMA_MSTR_CHANNEL_DIM 0x402
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#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM 0x402
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#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM 0x412
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#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM 0x422
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#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM 0x432
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#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM 0x442
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#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM 0x452
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#define CAR_mmXDMA_MSTR_HEIGHT 0x403
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#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT 0x403
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#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT 0x413
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#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT 0x423
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#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT 0x433
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#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT 0x443
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#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT 0x453
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#define CAR_mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x404
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#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE 0x404
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#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE 0x414
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#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE 0x424
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#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE 0x434
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#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE 0x444
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#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE 0x454
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#define CAR_mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405
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#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x405
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#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x415
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#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x425
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#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x435
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#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x445
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#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x455
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#define CAR_mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x406
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#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x406
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#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x416
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#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x426
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#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x436
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#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x446
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#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS 0x456
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#define CAR_mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407
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#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x407
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#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x417
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#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x427
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#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x437
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#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x447
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#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x457
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#define CAR_mmXDMA_MSTR_CACHE_BASE_ADDR 0x408
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#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR 0x408
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#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR 0x418
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#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR 0x428
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#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR 0x438
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#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR 0x448
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#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR 0x458
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#define CAR_mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409
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#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x409
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#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x419
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#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x429
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#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x439
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#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x449
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#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH 0x459
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#define CAR_mmXDMA_MSTR_CACHE 0x40a
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#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE 0x40a
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#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE 0x41a
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#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE 0x42a
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#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE 0x43a
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#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE 0x44a
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#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE 0x45a
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#define CAR_mmXDMA_MSTR_CHANNEL_START 0x40b
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#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START 0x40b
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#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START 0x41b
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#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START 0x42b
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#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START 0x43b
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#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START 0x44b
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#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START 0x45b
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#define CAR_mmXDMA_MSTR_PERFMEAS_STATUS 0x40e
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#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS 0x40e
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#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS 0x41e
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#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS 0x42e
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#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS 0x43e
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#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS 0x44e
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#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS 0x45e
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#define CAR_mmXDMA_MSTR_PERFMEAS_CNTL 0x40f
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#define CAR_mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL 0x40f
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#define CAR_mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL 0x41f
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#define CAR_mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL 0x42f
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#define CAR_mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL 0x43f
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#define CAR_mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL 0x44f
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#define CAR_mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL 0x45f
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#define CAR_mmXDMA_SLV_CNTL 0x460
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#define CAR_mmXDMA_SLV_MEM_CLIENT_CONFIG 0x461
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#define CAR_mmXDMA_SLV_SLS_PITCH 0x462
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#define CAR_mmXDMA_SLV_READ_URGENT_CNTL 0x463
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#define CAR_mmXDMA_SLV_WRITE_URGENT_CNTL 0x464
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#define CAR_mmXDMA_SLV_WB_RATE_CNTL 0x465
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#define CAR_mmXDMA_SLV_READ_LATENCY_MINMAX 0x466
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#define CAR_mmXDMA_SLV_READ_LATENCY_AVE 0x467
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#define CAR_mmXDMA_SLV_PCIE_NACK_STATUS 0x468
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#define CAR_mmXDMA_SLV_MEM_NACK_STATUS 0x469
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#define CAR_mmXDMA_SLV_RDRET_BUF_STATUS 0x46a
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#define CAR_mmXDMA_SLV_READ_LATENCY_TIMER 0x46b
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#define CAR_mmXDMA_SLV_FLIP_PENDING 0x46c
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#define CAR_mmXDMA_SLV_CHANNEL_CNTL 0x470
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#define CAR_mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL 0x470
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#define CAR_mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL 0x478
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#define CAR_mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL 0x480
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#define CAR_mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL 0x488
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#define CAR_mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL 0x490
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#define CAR_mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL 0x498
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#define CAR_mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x471
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#define CAR_mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS 0x471
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#define CAR_mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS 0x479
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#define CAR_mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS 0x481
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#define CAR_mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS 0x489
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#define CAR_mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS 0x491
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#define CAR_mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS 0x499
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#define CAR_mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472
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#define CAR_mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x472
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#define CAR_mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x47a
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#define CAR_mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x482
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#define CAR_mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x48a
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#define CAR_mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x492
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#define CAR_mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x49a
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#endif /* DCE_11_0_D_H */
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