* Avoid floating point numbers in the kernel
* Warning would always show if custom swap file in use
* Don't change a custom swap file size if low space occurs
* Ram > 1GB? Don't double the memory for the automatic size
* Heavily based on Hamish Morrison's GCI work with some
modified logic and cleanup. #3723
* Adds automatic swap as well as user specified swap
* Limits:
Automatic: (ram * 2) up to 25% of the disk
User: user specified up to 90% of the disk
* Supports changing the swap disk location
* The ASSERT() I introduced in r44585 was incorrect: when the sub transaction
used block_cache_get_empty() to get the block, there is no original_data for
a reason.
* Added a test case that reproduces this situation.
* The block must be moved to the unused list in this situation, though, or else
it might contain invalid data. Since the block can only be allocated in the
current transaction, this should not be a problem, though, AFAICT.
The lowest 4 bits of the MSR serves as a hint to the hardware to
favor performance or energy saving. 0 means a hint preference for
highest performance while 15 corresponds to the maximum energy
savings. A value of 7 translates into a hint to balance performance
with energy savings.
The default reset value of the MSR is 0. If BIOS doesn't intialize
the MSR, the hardware will run in performance state. This patch
initialize the MSR with value of 7 for balance between performance
and energy savings
Signed-off-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>
* In cache_abort_sub_transaction(), the original_data can already be freed
when the block is being removed from the transaction.
* block_cache::_GetUnusedBlock() no longer frees original/parent data - it
now requires them to be freed already (it makes no sense to have them still
around at this point).
* AFAICT the previous version did not have any negative consequences besides
freeing the original data late.
* cache_abort_sub_transaction() was setting the transaction_next pointer to
NULL in order to remove a block from a transaction -- however, it forgot to
actually remove it from the transaction's block list.
* Minor restructuring.
- If a trace entry has a stack trace, attempt to demangle the associated symbols.
Could be enhanced further to also demangle the arguments but doesn't yet.
Interestingly there are some mangled symbols that our demangler appears to
not handle correctly (gcc4).
Initializing the IO-APIC will initialize the PCI module, which does
read the MSI config of the devices only when MSIs are available.
Since we initialized them only after that, that condition wasn't met.
Later, due to the uninitialized arch info, MSIs were still marked as
available (0xcc = 204 MSIs). Due to the also uninitialized configured
count, they were always deemed busy however, in effect just breaking
MSI support whereever IO-APICs were available.
* cache_abort_transaction() left the block dirty which was causing bug
#8123 as well.
* cache_abort_sub_transaction() did, in addition to not clearing the dirty
flag, not reset the block's transaction member either if the block was
not part of the parent transaction.
This matches layout in ACPICA and keeps a cleaner boundry between
Haiku and ACPICA code. The only haiku specific file in ACPICA is
achaiku.h and it will hopefully be included upstream soon.
Merging will be simpler as we can just replace acpica contents and
fix Jamfile and build errors in our code.
- repnz movsb turns out to not actually be a legal instruction,
resulting in various strings being copied incorrectly, leading to
random crashes in various places. Rework to use loop instead.
Thanks to Alex Smith for helping review changes and offering
improvements.
- Minor cleanups.
- Fixes#8650 properly.
- Replace arch_cpu_user_strlcpy() and arch_cpu_user_memset() with x86 assembly
versions. These correctly handle the fault handler, which had broken again
on gcc4 for the C versions, causing stack corruption in certain error cases.
The other architectures will still need to have corresponding asm variants
added in order for them to not run into the same issue though.
Characters 17, 18 and 19 (device control 1, 2 and 3) become "full block",
"upper filled block" and "lower filled block". Using back- and foreground
color inversion these could be reduced to a single "half block", but
having them available as idividual chars is more convenient.
* On ppc440, the FPU is implemented as an Auxiliary Processing Unit,
we must therefore enable sending commands to it,
in addition to setting the MSR bit.
* While the baremetal arm book I have says mrc, it breaks
verdex and doesn't work on the Pi.
* Moving the page table address to the p15 coprocessor makes
more logical sense anyway... i think mrc was a typo.
* the common part should try to use the U-Boot API when found.
* the arch part can make use of cpu features (like timer register)
* the ppc code enables the FPU in the MSR, since it's used by vsnprintf(),
which at least saves one FP register in its prologue.
* gPeripheralBase keeps track of the device
peripherals before and after mmu_init
* Add ability to disable mmu for troubleshooting
* Remove static FB_BASE, we actually don't know
where the FB is yet. (depends on firmware used)
