Intel changed the PCH interrupt bits between Sandy Bridge and Ivy Bridge
to make space for the 3rd display pipe. Take this into account and check
for the correct bits on the newer devices.
Fixes#11522.
* These aren't tested, but since we go off of DCE
versions for a lot of stuff, they may work.
* AMD doens't include market names in their drivers
anymore, so if we want to label them it will take
additional work.
* This is less pretty, but we need access to the connector
to find the HPD gpio pin mask on the card.
* dp_aux communications seem to work again.
* If you have a DisplayPort item attached to your card you
may want to just unplug it at this point. We attempt DP
link training and it fails. This failure will also cause
other monitors to not function as app_server still isn't
multi-head aware (#10486)
https://github.com/druga/haiku-stuff/tree/master/intel_extreme
Rebased against current sources.
* The BIOS video mode sometimes reports a scaled mode instead of the
physical panel dimensions. Get the data from the VBT table as well, and
use it if the reported resolution is bigger.
* On first boot, force the panel native mode so the user doesn't have to
set it manually.
* Only allow a single head at a time on i855gm, as the card can't drive
both heads at the same time.
* Detect when a new requested mode is the same as the current one, and
skip modesetting in that case. Avoids screen flickering when changing
workspaces.
* Fix some cases of misdetecting which pipes to enable
* They are all over the place.. I give up
* Going off of engineering names and DCE is more accurate
* A lot of this info came from the x.org wiki
* I'd like to transition some of the engineering
name checks to use DCE versions.. they tend to be more
accurate and exact. (in some cases we can't, but most of
the time we can)
* edid1_detailed_timing_raw was missing
a field which threw off the sync bits.
* The result was the monitor will receive
a different sync polarity than it requested.
Most monitors handle this, but it is still
a bug
* Remove non-generic radeon dp_get_lane_count
* Set lane count and link rate at set_display_mode
* Pass entire mode to pll_set vs only pixel clock for DP code
* Add helpers for DP config data to common code
* Obtain more correct link rate
* This puts the registers in a better state and ensures
all model dependant defines are prefixed with card series
* Consolidate evergreen defines into single header
* First steps at getting card command processor wired
up to the ring buffers.
* Code doesn't run yet as I have *no* idea what happens
when these rings are in an invalid state.
* General DisplayPort functions in common dp.cpp
* DP port information struct in common header
* Please don't use this private accelerant common DP
code just yet as it is very early.
* The AtomBIOS timeout fix has made my DP bridge
stop working
* The current DisplayPort code is a little lacking
on DP link training... I think thats the cause.
* This puts the first steps towards DP training
in place.
* I plan on trying to make some of this DP stuff
common accelerant stuff after it works.
* I'd rather this be common code, but I don't have access
to the DisplayPort specifications. If I added it as common
code I would want to be 100% it was complete and variables
were named properly.
* For now putting in radeon_hd private headers
* add temperature query support for Juniper, Sumo, Evergreen, and North Islands
* add missing thermal defines for evergreen cards
* northern island cards use the evergreen thermal calculations
* add a few missing/needed header defines
* show GPU temp in millidegrees C on r600/r700
* evergreen+ support soon
* function may be moved to driver long term once testing done
* add missing chipset ranges
* add a few more older (X1200) PCI ID's (mostly IGP)
* add code to detect and set frame buffer size on old chipsets
* we get to the connector detection currently and fail due to the
lack of legacy support on my X1200 IGP
