There was some mixup with the interrupt registers, still:
- The driver uses 16-bit read/write, but on SandyBridge the register is
32 bits
- There is a global interrupt enable bit, which must be set to unmask
everything else
- The bits for vblank interrupt are not the same on SNB and later PCH
based devices, and the code mixed the two.
Move the computation of the interrupt bits to an helper function, and
use it everywhere to make sure we always use the right bits.
Modesetting
===========
My previous hack was setting the transcoder registers, instead of the
display ones. Do that the way it is designed in the driver instead:
- If there is a transcoder, set its registers, but do not set the
display timings. The display will remain set at its native (and only)
resolution, and panel fitting will adjust the output of the transcoder
to match.
- If there is no transcoder, set the display registers directly to the
native resolution, as it was done on previous generation devices.
- fPipeOffset hacks no longer needed
DPMS
====
It seems the panel control register is not readable on PCH? Anyway, the
code would loop forever waiting for the bit to become unset when turning
the display off. Waiting seems to not be needed, so just remove it as
well as the "unlock" bit, which does not work for me and results in a
black screen.
Remaining hacks
===============
I still need to force HEAD_MODE_A_ANALOG to get output on pipe B (LVDS
display) working. I suspect something is common to the two pipes or not
allocated to the right one.
This version will have less side effects on other generations and help
with getting things to work on SandyBridge and possibly later devices.
Please test and report.
* Detect PCH model based on ISA bridge and save
into shared info for later use.
* On CougarPoint PCH systems, assign pipes via
special CPT registers
* Drop HasPlatformControlHub as PCH should be
based on more than just generation.
* Move current_mode into the accelerant as the
driver doesn't care.
* Record panel_mode in driver and present to accelerant
* eDP, if no EDID and mobile, leave edid incomplete.
Mode set should notice that and fall back to panel_mode
* DisplayPort != DigitalPort
* i2c needs wrapped in DP AUX transaction code
* Mode-setting comes with DP link training as well
* We need to try and share DP code with radeon_hd
* polarity regs move on LVDS vs analog
* add knowledge or transcoder registers, they
exist seperately on PCH-split
* Native resolutions now work on LVDS under i965
* IvyBridge or higher can auto-train.
* Linux doesn't use this feature, however
manual FDI link training is *really*
complex... lets try auto-training first.
* I really hope we can kill head_mode some day
* Break pll code out from mode code
* The LVDS and Digital are smooshed together and
likely need broken apart.
* No impact to non-ValleyView chipsets
* Bump some register locations for VLV
* Only have HDMI port to test with on my ValleyView GPU
and our driver seems to be missing all HDMI and
sideband functionality.
* As ValleyView chipsets seem to be UEFI only, we don't
have VESA fallback, so this shouldn't cause regressions.
(unless we get UEFI framebuffer support)
Intel changed the PCH interrupt bits between Sandy Bridge and Ivy Bridge
to make space for the 3rd display pipe. Take this into account and check
for the correct bits on the newer devices.
Fixes#11522.
https://github.com/druga/haiku-stuff/tree/master/intel_extreme
Rebased against current sources.
* The BIOS video mode sometimes reports a scaled mode instead of the
physical panel dimensions. Get the data from the VBT table as well, and
use it if the reported resolution is bigger.
* On first boot, force the panel native mode so the user doesn't have to
set it manually.
* Only allow a single head at a time on i855gm, as the card can't drive
both heads at the same time.
* Detect when a new requested mode is the same as the current one, and
skip modesetting in that case. Avoids screen flickering when changing
workspaces.
* Fix some cases of misdetecting which pipes to enable
