Alexander von Gluck IV
0ea662e5e9
intel_extreme: Correct panel control register on non-pch
2015-12-15 07:23:21 -06:00
Alexander von Gluck IV
471bc81038
intel_extreme: Fix LVDS pll DAC timing
2015-12-12 00:11:30 -06:00
Alexander von Gluck IV
5202e45a52
intel_extreme: Improve LVDS CLKB desire detection
2015-12-05 11:47:15 -06:00
Alexander von Gluck IV
e587aa9fa3
pll: Cleanup PLL post dividers, add VLV and CHV limits
2015-12-05 11:26:14 -06:00
Alexander von Gluck IV
3cfe299798
intel_extreme: Rework PLL and id PineView as PIN
2015-12-04 13:34:33 -06:00
Alexander von Gluck IV
77b8386d56
intel_extreme: Tweak pll limits on 9xx
2015-11-26 23:43:59 -06:00
Alexander von Gluck IV
f6623f4d99
intel_extreme: program both pll divisors
2015-11-26 22:57:57 -06:00
Alexander von Gluck IV
7217bb117b
intel_extreme: Take a register dump for intel_reg
2015-11-24 16:47:02 -06:00
Alexander von Gluck IV
d7a8a21fa5
intel_extreme: Style fix, no functional change
2015-11-24 12:15:06 -06:00
Alexander von Gluck IV
b01aed8310
intel_extreme: Don't store pipes within ports
...
* Store pipes within accelerant, and tell ports
about them.
* Rebrand DisplayPipe class to Pipe
2015-11-24 12:11:31 -06:00
Alexander von Gluck IV
864275121f
intel_extreme: Fix LVDS polarity flags
2015-11-24 09:41:18 -06:00
Alexander von Gluck IV
bc98dc421e
intel_extreme: Improve LVDS panel control
...
* Disable panel before modification
* Properly wait for panel power
2015-11-23 17:32:40 -06:00
Alexander von Gluck IV
cc891135c8
intel_extreme: return after proper FDI auto-train
2015-11-20 19:21:44 -06:00
Alexander von Gluck IV
874b248894
intel_extreme: Enable FDI PLL's before FDI training
2015-11-20 10:12:30 -06:00
Alexander von Gluck IV
e6fefa6cbf
intel_extreme: More FDI training work
...
* IvyBridge or higher can auto-train.
* Linux doesn't use this feature, however
manual FDI link training is *really*
complex... lets try auto-training first.
2015-11-19 17:49:51 -06:00
Alexander von Gluck IV
aa06863ccd
intel_extreme: Enable / Disable FDI TX/RX
2015-11-19 13:26:55 -06:00
Alexander von Gluck IV
00e0982f68
intel_extreme: First work at programming FDI
2015-11-17 23:28:09 -06:00
Alexander von Gluck IV
32807945aa
intel_extreme: Some basic pipe cleanup
2015-11-17 20:12:41 -06:00
Alexander von Gluck IV
e5494f1bb2
intel_extreme: Fix DP / HDMI gpu register location mixup on die
2015-11-16 20:41:14 -06:00
Alexander von Gluck IV
202ffc8cca
intel_extreme: Bump the VLV offset back a bit and fix port defines
2015-11-16 19:58:51 -06:00
Alexander von Gluck IV
21e840d154
intel_extreme: Cleanup pipe enablement ordering
2015-11-13 14:56:12 -06:00
Alexander von Gluck IV
fa45565eb7
intel_extreme: Add missing vlv offset to south shared
2015-11-13 10:10:54 -06:00
Alexander von Gluck IV
f482afbc22
intel-extreme: Fix N pll limits on 9xx
2015-11-12 19:03:46 -06:00
Alexander von Gluck IV
f979e62e54
intel_extreme: Program more LVDS regs. Set +/- @ lvds port
2015-11-12 18:30:21 -06:00
Alexander von Gluck IV
39f61d2190
intel_extreme: Store current display mode on each port
2015-11-12 16:44:04 -06:00
Alexander von Gluck IV
eb56837dfb
intel_extreme: Disable lvds panel_fitter for now
2015-11-12 16:18:45 -06:00
Alexander von Gluck IV
c7c3bcda8c
intel_extreme: Revert unintended change in 222f5929
2015-11-12 15:43:25 -06:00
Alexander von Gluck IV
222f5929cf
intel_extreme: Make sure we power up the panel after modesetting
2015-11-11 17:25:46 -06:00
Alexander von Gluck IV
de04810814
intel_extreme: Program multiplier divisors
2015-11-10 17:50:54 -06:00
Alexander von Gluck IV
be3f7a8fc5
intel_extreme: tracing cleanup; no functional change
2015-11-10 16:23:37 -06:00
Alexander von Gluck IV
a5a2bf727c
intel_extreme: Let ports pick a pipe if required
2015-11-10 16:00:26 -06:00
Alexander von Gluck IV
4f2b258c32
intel_extreme: Fix LVDS head mode (we'll remove it soon)
2015-11-09 22:26:47 -06:00
Alexander von Gluck IV
92bcdd7935
intel_extreme: Add initial TMDS modesetting code
2015-11-09 09:26:07 -06:00
Alexander von Gluck IV
d442692fab
intel_extreme: Correct DP port registers
2015-11-09 09:15:16 -06:00
Alexander von Gluck IV
328d66d5f0
intel_extreme: Fix ordering of fb set. Uses current_mode
2015-11-08 23:29:56 -06:00
Alexander von Gluck IV
61fbdb0667
intel_extreme: Set mode and pll via pipe-aware class functions
2015-11-08 23:14:46 -06:00
Alexander von Gluck IV
72cecf8765
intel_extreme: Add missing DisplayPipe destructor
2015-11-08 13:58:50 -06:00
Alexander von Gluck IV
6e1ff82f45
intel_extreme: Begin using new DisplayPipe class
2015-11-08 11:58:49 -06:00
Alexander von Gluck IV
37b903fbc8
intel_extreme: Add pipe selection for ports
2015-11-08 10:39:07 -06:00
Alexander von Gluck IV
b809fb52ed
intel_extreme: Add some missing panel registers, masks, shifts
2015-11-04 17:48:06 -06:00
Alexander von Gluck IV
9cd46c7372
intel_extreme: Fix PCH_PANEL STS/CTL register location and define more
2015-11-04 17:29:06 -06:00
Alexander von Gluck IV
c9117774b2
intel_extreme: Improve generation tracing
2015-11-04 17:24:27 -06:00
Alexander von Gluck IV
fb255821eb
intel_extreme: Correct generations based on some Intel help
2015-11-04 16:11:22 -06:00
Alexander von Gluck IV
fa1d593323
intel_gart: Clean up trace code, break apart gtt probe functions
2015-11-03 17:18:58 -06:00
Alexander von Gluck IV
47fba246cc
intel_extreme: Fix IsMobile. That's not how masks work
2015-11-02 20:14:00 -06:00
Alexander von Gluck IV
c86f3dba23
intel_extreme: LVDS cleanup and fixes for later gens
2015-11-02 18:01:18 -06:00
Alexander von Gluck IV
4b6d5b8427
intel_extreme: Drop fatal error on no monitors.
2015-11-02 16:28:04 -06:00
Alexander von Gluck IV
e2e5daf25b
intel_extreme: Add generation index + begin to use in gart
2015-11-02 15:55:05 -06:00
Alexander von Gluck IV
53f5bffe84
intel_gart: Fix gart detection and begin using DeviceType
...
* Correctly identify newly re-assigned cards families
* Begin using new DeviceType class in intel gart code
2015-11-01 20:17:20 -06:00
Alexander von Gluck IV
84b7116da8
intel_extreme: Rework card identification defines
...
* Be more verbose on flag type
* Add additional groups
* Add additional families
* Correctly assign later models
2015-11-01 12:20:10 -06:00
