fixed GeForce AGP/PCIe 6600 PLL trouble (refreshrate), added fifo assignment usage remark. Note that GeForce 6600 and 6800 have the acc and overlay engines still down. Apart from that, they work (if you try the code now, the driver will still hang though..)

Hope to fix these remaining issues soon..


git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10531 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2004-12-24 22:43:06 +00:00
parent 872e52f249
commit ff20b3ad82
2 changed files with 11 additions and 3 deletions

View File

@ -26,8 +26,7 @@ blit
nVidia hardware info:
We should be able to do FIFO assignment setup changes on-the-fly now, using
all the engine-command-handles that are pre-defined on any FIFO channel.
(check channel to be emptied, then re-assign to new command, then use: etc.)
Maybe we can even setup new additional handles to previously unused engine
commands now, and there might even be a chance DMA can be setup(?).
*/
@ -1060,6 +1059,13 @@ static void nv_init_for_3D(void)
}
}
/* fixme? (check this out..)
* Looks like this stuff can be very much simplified and speed-up, as it seems it's not
* nessesary to wait for the engine to become idle before re-assigning channels.
* Because the cmd handles are actually programmed _inside_ the fifo channels, it might
* well be that the assignment is buffered along with the commands that still have to
* be executed!
* (sounds very plausible to me :) */
void nv_acc_assert_fifo(void)
{
/* does every engine cmd this accelerant needs have a FIFO channel? */

View File

@ -1,7 +1,7 @@
/* Read initialisation information from card */
/* some bits are hacks, where PINS is not known */
/* Author:
Rudolf Cornelissen 7/2003-10/2004
Rudolf Cornelissen 7/2003-12/2004
*/
#define MODULE_BIT 0x00002000
@ -2807,7 +2807,9 @@ static void pinsnv30_arch_fake(void)
{
case NV31:
case NV36:
/* fixme? could be all >= NV40 cards have extended PLL's... (these 2 are confirmed) */
case NV40:
case NV43:
/* we have a extended PLL */
si->ps.ext_pll = true;
break;