Added function for setting the CPU state (not implemented yet) and
functions for setting break-/watchpoints (implemented). Break-/watchpoints don't work yet, though. Missing is still the setting of the debug control register DR7 somewhere in the interrupt code and the handling of debug exceptions. git-svn-id: file:///srv/svn/repos/haiku/trunk/current@11509 a95241bf-73f2-0310-859d-f6bbb57e9c96
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Ingo Weinhold
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feeee8dff5
@ -6,8 +6,56 @@
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#include <string.h>
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#include <debugger.h>
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#include <thread.h>
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#include <arch/user_debugger.h>
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#include <arch/thread.h>
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#define B_NO_MORE_BREAKPOINTS B_ERROR
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#define B_NO_MORE_WATCHPOINTS B_ERROR
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#define B_BAD_WATCHPOINT_ALIGNMENT B_ERROR
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#define B_WATCHPOINT_TYPE_NOT_SUPPORTED B_ERROR
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#define B_WATCHPOINT_LENGTH_NOT_SUPPORTED B_ERROR
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#define B_BREAKPOINT_NOT_FOUND B_ERROR
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#define B_WATCHPOINT_NOT_FOUND B_ERROR
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// ToDo: Make those real error codes.
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// maps breakpoint slot index to LEN_i LSB number
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static const uint32 sDR7Len[4] = {
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X86_DR7_LEN0_LSB, X86_DR7_LEN1_LSB, X86_DR7_LEN2_LSB, X86_DR7_LEN3_LSB
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};
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// maps breakpoint slot index to R/W_i LSB number
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static const uint32 sDR7RW[4] = {
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X86_DR7_RW0_LSB, X86_DR7_RW1_LSB, X86_DR7_RW2_LSB, X86_DR7_RW3_LSB
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};
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// maps breakpoint slot index to L_i bit number
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static const uint32 sDR7L[4] = {
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X86_DR7_L0, X86_DR7_L1, X86_DR7_L2, X86_DR7_L3
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};
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void
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arch_clear_team_debug_info(struct arch_team_debug_info *info)
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{
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for (int32 i = 0; i < X86_BREAKPOINT_COUNT; i++)
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info->breakpoints[i].address = NULL;
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info->dr7 = X86_BREAKPOINTS_DISABLED_DR7;
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}
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void
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arch_destroy_team_debug_info(struct arch_team_debug_info *info)
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{
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arch_clear_team_debug_info(info);
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}
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void
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arch_set_debug_cpu_state(const struct debug_cpu_state *cpuState)
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{
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// ToDo: Implement!
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}
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void
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arch_get_debug_cpu_state(struct debug_cpu_state *cpuState)
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@ -15,3 +63,182 @@ arch_get_debug_cpu_state(struct debug_cpu_state *cpuState)
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struct iframe *frame = i386_get_current_iframe();
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memcpy(cpuState, frame, sizeof(debug_cpu_state));
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}
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static status_t
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set_breakpoint(void *address, uint32 type, uint32 length)
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{
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if (!address)
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return B_BAD_VALUE;
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struct thread *thread = thread_get_current_thread();
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status_t error = B_OK;
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cpu_status state = disable_interrupts();
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GRAB_TEAM_DEBUG_INFO_LOCK(thread->team->debug_info);
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arch_team_debug_info &info = thread->team->debug_info.arch_info;
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// check, if there is already a breakpoint at that address
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bool alreadySet = false;
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for (int32 i = 0; i < X86_BREAKPOINT_COUNT; i++) {
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if (info.breakpoints[i].address == address
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&& info.breakpoints[i].type == type) {
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alreadySet = true;
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break;
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}
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}
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if (!alreadySet) {
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// find a free slot
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int32 slot = -1;
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for (int32 i = 0; i < X86_BREAKPOINT_COUNT; i++) {
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if (!info.breakpoints[i].address) {
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slot = i;
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break;
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}
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}
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// init the breakpoint
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if (slot >= 0) {
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info.breakpoints[slot].address = address;
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info.breakpoints[slot].type = type;
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info.breakpoints[slot].length = length;
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info.dr7 |= (length << sDR7Len[slot])
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| (type << sDR7RW[slot])
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| (1 << sDR7L[slot]);
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// set the respective debug address register (DR0-DR3)
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switch (slot) {
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case 0: asm("movl %0, %%dr0" : : "r"(address)); break;
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case 1: asm("movl %0, %%dr1" : : "r"(address)); break;
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case 2: asm("movl %0, %%dr2" : : "r"(address)); break;
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case 3: asm("movl %0, %%dr3" : : "r"(address)); break;
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}
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} else {
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if (type == X86_INSTRUCTION_BREAKPOINT)
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error = B_NO_MORE_BREAKPOINTS;
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else
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error = B_NO_MORE_WATCHPOINTS;
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}
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}
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RELEASE_TEAM_DEBUG_INFO_LOCK(thread->team->debug_info);
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restore_interrupts(state);
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return error;
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}
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static status_t
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clear_breakpoint(void *address, bool watchpoint)
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{
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if (!address)
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return B_BAD_VALUE;
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struct thread *thread = thread_get_current_thread();
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status_t error = B_OK;
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cpu_status state = disable_interrupts();
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GRAB_TEAM_DEBUG_INFO_LOCK(thread->team->debug_info);
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arch_team_debug_info &info = thread->team->debug_info.arch_info;
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// find the breakpoint
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int32 slot = -1;
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for (int32 i = 0; i < X86_BREAKPOINT_COUNT; i++) {
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if (info.breakpoints[i].address == address
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&& (watchpoint
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!= (info.breakpoints[i].type == X86_INSTRUCTION_BREAKPOINT))) {
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slot = i;
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break;
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}
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}
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// clear the breakpoint
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if (slot >= 0) {
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info.breakpoints[slot].address = NULL;
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info.dr7 &= ~((0x3 << sDR7Len[slot])
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| (0x3 << sDR7RW[slot])
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| (1 << sDR7L[slot]));
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} else {
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if (watchpoint)
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error = B_WATCHPOINT_NOT_FOUND;
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else
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error = B_BREAKPOINT_NOT_FOUND;
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}
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RELEASE_TEAM_DEBUG_INFO_LOCK(thread->team->debug_info);
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restore_interrupts(state);
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return error;
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}
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status_t
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arch_set_breakpoint(void *address)
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{
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return set_breakpoint(address, X86_INSTRUCTION_BREAKPOINT,
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X86_BREAKPOINT_LENGTH_1);
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}
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status_t
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arch_clear_breakpoint(void *address)
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{
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return clear_breakpoint(address, false);
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}
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status_t
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arch_set_watchpoint(void *address, uint32 type, int32 length)
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{
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// check type
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uint32 archType;
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switch (type) {
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case B_DATA_WRITE_WATCHPOINT:
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archType = X86_DATA_WRITE_BREAKPOINT;
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break;
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case B_DATA_READ_WRITE_WATCHPOINT:
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archType = X86_DATA_READ_WRITE_BREAKPOINT;
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break;
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case B_DATA_READ_WATCHPOINT:
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default:
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return B_WATCHPOINT_TYPE_NOT_SUPPORTED;
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break;
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}
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// check length and alignment
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uint32 archLength;
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switch (length) {
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case 1:
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archLength = X86_BREAKPOINT_LENGTH_1;
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break;
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case 2:
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if ((uint32)address & 0x1)
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return B_BAD_WATCHPOINT_ALIGNMENT;
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archLength = X86_BREAKPOINT_LENGTH_2;
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break;
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case 4:
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if ((uint32)address & 0x3)
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return B_BAD_WATCHPOINT_ALIGNMENT;
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archLength = X86_BREAKPOINT_LENGTH_4;
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break;
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default:
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return B_WATCHPOINT_LENGTH_NOT_SUPPORTED;
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}
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return set_breakpoint(address, archType, archLength);
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}
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status_t
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arch_clear_watchpoint(void *address)
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{
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return clear_breakpoint(address, false);
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}
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