completed DMA buffer wraparounds. DMA acceleration is now stable on NV11 and NV43. Enjoy.. (still missing acc hooks will be setup asap.)
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10959 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
parent
c3a3ddf246
commit
fc61675c5a
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@ -26,9 +26,8 @@ blit
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nVidia hardware info:
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We should be able to do FIFO assignment setup changes on-the-fly now, using
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all the engine-command-handles that are pre-defined on any FIFO channel.
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We should be able to even setup new additional handles to previously unused engine
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commands now, and DMA use should also be possible.
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Also we should be able to setup new additional handles to previously unused
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engine commands now.
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*/
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/* FIFO channel pointers */
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@ -82,14 +81,12 @@ status_t nv_acc_init()
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/* (setup caches) */
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/* disable caches reassign */
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ACCW(PF_CACHES, 0x00000000);
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//fixme: set this up for DMA use one day..
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/* PFIFO mode for all 32 channels is PIO (instead of DMA) */
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ACCW(PF_MODE, 0x00000000);
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/* cache1 push0 access disabled */
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ACCW(PF_CACH1_PSH0, 0x00000000);
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/* cache1 pull0 access disabled */
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ACCW(PF_CACH1_PUL0, 0x00000000);
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//fixme: set this up for DMA use one day..
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/* cache1 push1 mode = pio (disable DMA use) */
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ACCW(PF_CACH1_PSH1, 0x00000000);
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/* cache1 DMA Put offset = 0 (b2-28) */
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@ -100,10 +97,8 @@ status_t nv_acc_init()
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* instance being b4-19 with baseadress NV_PRAMIN_CTX_0 (0x00700000). */
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/* note:
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* should point to a DMA definition in CTX register space (which is sort of RAM).
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* This define tells the engine where the DMA cmd buffer is and what it's size is;
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* inside that cmd buffer you'll find the engine handles for the FIFO channels,
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* followed by actual issued engine commands. */
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//fixme: set this up for DMA use one day..
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* This define tells the engine where the DMA cmd buffer is and what it's size is.
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* Inside that cmd buffer you'll find the actual issued engine commands. */
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ACCW(PF_CACH1_DMAI, 0x00000000);
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/* cache0 push0 access disabled */
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ACCW(PF_CACH0_PSH0, 0x00000000);
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@ -144,7 +139,6 @@ status_t nv_acc_init()
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* use little endian */
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ACCW(PF_CACH1_DMAF, 0x000f0078);
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/* cache1 DMA push: b0=0 is access disabled */
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//fixme: set this up for DMA use one day..
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ACCW(PF_CACH1_DMAS, 0x00000000);
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/* cache1 push0 access enabled */
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ACCW(PF_CACH1_PSH0, 0x00000001);
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@ -61,8 +61,6 @@ status_t nv_acc_init_dma()
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{
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uint16 cnt;
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uint32 surf_depth, patt_depth;
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//fixme: move to shared info:
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uint32 max;
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/* a hanging engine only recovers from a complete power-down/power-up cycle */
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NV_REG32(NV32_PWRUPCTRL) = 0x13110011;
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@ -555,7 +553,7 @@ status_t nv_acc_init_dma()
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}
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/* all cards: */
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/* setup some clipping: rect size is 32768 x 32768, probably max. setting */
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/* setup clipping: rect size is 32768 x 32768, probably max. setting */
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ACCW(ABS_UCLP_XMIN, 0x00000000);
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ACCW(ABS_UCLP_YMIN, 0x00000000);
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ACCW(ABS_UCLP_XMAX, 0x00007fff);
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@ -584,9 +582,8 @@ status_t nv_acc_init_dma()
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* instance being b4-19 with baseadress NV_PRAMIN_CTX_0 (0x00700000). */
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/* note:
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* should point to a DMA definition in CTX register space (which is sort of RAM).
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* This define tells the engine where the DMA cmd buffer is and what it's size is;
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* inside that cmd buffer you'll find the engine handles for the FIFO channels,
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* followed by actual issued engine commands. */
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* This define tells the engine where the DMA cmd buffer is and what it's size is.
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* Inside that cmd buffer you'll find the actual issued engine commands. */
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ACCW(PF_CACH1_DMAI, 0x0000114e);
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/* cache0 push0 access disabled */
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ACCW(PF_CACH0_PSH0, 0x00000000);
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@ -679,11 +676,15 @@ status_t nv_acc_init_dma()
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* one word is reserved at the end of the DMA buffer to be able to instruct the
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* engine to do a buffer wrap-around!
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* (DMA opcode 'noninc method': issue word $20000000.) */
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/*si->dma.*/max = 8191;
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//testing:
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si->engine.dma.max = 2048 - 1;//8192 - 1;
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/* note the current free space we have left in the DMA buffer */
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si->engine.dma.free = /*si->dma.*/max - si->engine.dma.current /*+ 1*/;
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si->engine.dma.free = si->engine.dma.max - si->engine.dma.current;
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/*** init FIFO via DMA command buffer. ***/
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/* note:
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* we know there's space enough in the command buffer to issue these commands,
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* so no need to wait for room in there. */
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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(NV_GENERAL_FIFO_CH0 | (1 << 18));
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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@ -728,6 +729,9 @@ status_t nv_acc_init_dma()
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// (0x80000000 | si->engine.fifo.handle[7]); /* Textured Triangle (3D only) */
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(0x80000000 | si->engine.fifo.handle[0]);
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/* update the current free space we have left in the DMA buffer */
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si->engine.dma.free = si->engine.dma.max - si->engine.dma.current;
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//fixme: overlay should stay outside the DMA buffer, also add a failsafe
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// space in between both functions as errors might hang the engine!
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/*** Set pixel width ***/
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@ -810,14 +814,55 @@ for (dummy = 0; dummy < 2; dummy++)
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static status_t nv_acc_fifofree_dma(uint16 cmd_size)
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{
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//fixme: implement buffer wraparounds.. (buffer resets when full)
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//for now only executing the first commands issued and drop exec after;
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//this offers testing options already (depending on how much windows are visible,
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//exec remains going say 30 seconds to a few minutes if only blits are enabled.
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// if (si->dma.free >= cmd_size) return B_OK;
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if ((si->engine.dma.current + cmd_size) < 8191) return B_OK;
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//test:
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uint32 dummy;
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return B_ERROR;
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if (si->engine.dma.free < cmd_size)
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{
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//test:
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LOG(4,("ACC_FIFOFREE: level 1; free $%08x, max $%08x, current $%08x\n",
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si->engine.dma.free, si->engine.dma.max, si->engine.dma.current ));
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/* update to actual current situation (free is 'cached') */
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// si->engine.dma.free = si->engine.dma.max - si->engine.dma.current;
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/* check again if we have enough space */
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// if (si->engine.dma.free < cmd_size)
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{
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//test:
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LOG(4,("ACC_FIFOFREE: level 2\n"));
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/* nope, so instruct DMA engine to reset the buffer when it's done */
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si->engine.dma.cmdbuffer[si->engine.dma.current++] = 0x20000000;
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/* reset our buffer pointer, so new commands will be placed at the
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* beginning of the buffer. */
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si->engine.dma.current = 0;
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/* tell the engine to fetch the remaining command(s) in the DMA buffer
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* that where not executed before. */
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nv_start_dma();
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/* fixme if needed:
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* we are assuming here that a large part in the beginning of the DMA
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* cmd buffer is already processed. If this is not true, we need to wait
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* here until the engine becomes idle or so... */
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//test:
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//nv_acc_wait_idle_dma();
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// {
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/* snooze a bit so I do not hammer the bus */
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// snooze (100);
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// }
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for (dummy = 0; dummy < 2; dummy++)
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{
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LOG(4,("ACC_DMA_WRAP: get $%08x\n", NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET +
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si->engine.fifo.handle[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID])])));
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LOG(4,("ACC_DMA_WRAP: put $%08x\n", (si->engine.dma.put << 2)));
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}
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/* update the current free space we have left in the DMA buffer */
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si->engine.dma.free = si->engine.dma.max - si->engine.dma.current;
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}
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}
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return B_OK;
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}
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static void nv_acc_cmd_dma(uint32 cmd, uint16 offset, uint16 size)
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@ -836,6 +881,9 @@ static void nv_acc_cmd_dma(uint32 cmd, uint16 offset, uint16 size)
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* to set a new adress if a gap exists between the previous one and the new one. */
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si->engine.dma.cmdbuffer[si->engine.dma.current++] = ((size << 18) |
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((si->engine.fifo.ch_ptr[cmd] + offset) & 0x0000fffc));
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/* space left after issuing the current command is the cmd AND it's data */
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si->engine.dma.free -= (size + 1);
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}
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/* fixme? (check this out..)
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@ -886,6 +934,9 @@ void nv_acc_assert_fifo_dma(void)
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(0x00000001 + (cnt * 0x00002000));
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}
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/* wait for room in fifo for new FIFO assigment cmds if needed. */
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nv_acc_fifofree_dma(12);
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/* program new FIFO assignments */
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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(NV_GENERAL_FIFO_CH0 | (1 << 18));
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@ -917,6 +968,9 @@ void nv_acc_assert_fifo_dma(void)
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si->engine.dma.cmdbuffer[si->engine.dma.current++] =
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(0x80000000 | si->engine.fifo.handle[5]); /* Bitmap */
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/* update the current free space we have left in the DMA buffer */
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si->engine.dma.free = si->engine.dma.max - si->engine.dma.current;
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/* tell the engine to fetch and execute all (new) commands in the DMA buffer */
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nv_start_dma();
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}
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@ -927,8 +981,7 @@ status_t nv_acc_setup_blit_dma()
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{
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/* setup solid pattern:
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* wait for room in fifo for pattern cmd if needed. */
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//fixme: testing..
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if (nv_acc_fifofree_dma(7) != B_OK) return B_ERROR;
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nv_acc_fifofree_dma(7);
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/* now setup pattern (writing 7 32bit words) */
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nv_acc_cmd_dma(NV_IMAGE_PATTERN, NV_IMAGE_PATTERN_SETSHAPE, 1);
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@ -940,8 +993,7 @@ status_t nv_acc_setup_blit_dma()
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si->engine.dma.cmdbuffer[si->engine.dma.current++] = 0xffffffff; /* SetPattern[1] */
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/* ROP registers (Raster OPeration):
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* wait for room in fifo for ROP cmd if needed. */
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//fixme: testing..
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if (nv_acc_fifofree_dma(2) != B_OK) return B_ERROR;
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nv_acc_fifofree_dma(2);
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/* now setup ROP (writing 2 32bit words) */
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nv_acc_cmd_dma(NV_ROP5_SOLID, NV_ROP5_SOLID_SETROP5, 1);
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@ -956,8 +1008,7 @@ status_t nv_acc_blit_dma(uint16 xs,uint16 ys,uint16 xd,uint16 yd,uint16 w,uint16
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/* instruct engine what to blit:
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* wait for room in fifo for blit cmd if needed. */
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//fixme: testing..
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if (nv_acc_fifofree_dma(4) != B_OK) return B_ERROR;
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nv_acc_fifofree_dma(4);
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/* now setup blit (writing 4 32bit words) */
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nv_acc_cmd_dma(NV_IMAGE_BLIT, NV_IMAGE_BLIT_SOURCEORG, 3);
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