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kernel/x86_64: configure LFENCE as a serializing instruction on AMD

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Change-Id: I152bf41c3479f81fc458abdf8d89874ffa3a08d7
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5691
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>
This commit is contained in:
Jérôme Duval 2022-09-23 19:21:49 +02:00
parent a6e9176bc5
commit fbca1c4088
2 changed files with 14 additions and 0 deletions
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3
headers/private/kernel/arch/x86/arch_cpu.h
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@ -122,6 +122,9 @@
// K8 MSR registers
#define K8_MSR_IPM 0xc0010055
#define MSR_F10H_DE_CFG 0xc0011029
#define DE_CFG_SERIALIZE_LFENCE (1 << 1)
// Hardware P-States MSR registers §14.4.1
// reference https://software.intel.com/content/dam/develop/public/us/en/documents/253669-sdm-vol-3b.pdf

11
src/system/kernel/arch/x86/arch_cpu.cpp
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@ -1496,6 +1496,17 @@ arch_cpu_init_percpu(kernel_args* args, int cpu)
// if RDTSCP is available write cpu number in TSC_AUX
if (x86_check_feature(IA32_FEATURE_AMD_EXT_RDTSCP, FEATURE_EXT_AMD))
x86_write_msr(IA32_MSR_TSC_AUX, cpu);
// make LFENCE a dispatch serializing instruction on AMD 64bit
cpu_ent* cpuEnt = get_cpu_struct();
if (cpuEnt->arch.vendor == VENDOR_AMD) {
uint32 family = cpuEnt->arch.family + cpuEnt->arch.extended_family;
if (family >= 0x10 && family != 0x11) {
uint64 value = x86_read_msr(MSR_F10H_DE_CFG);
if ((value & DE_CFG_SERIALIZE_LFENCE) == 0)
x86_write_msr(MSR_F10H_DE_CFG, value | DE_CFG_SERIALIZE_LFENCE);
}
}
#endif
if (x86_check_feature(IA32_FEATURE_APERFMPERF, FEATURE_6_ECX)) {